Commit Graph

9 Commits

Author SHA1 Message Date
Terje Bergstrom
2aead8a72f gpu: nvgpu: Disable only channel at zcull bind
At zcull bind we disable whole GR engine. This is unnecessary, so
instead disable only the channel and make sure it's unloaded.

Introduces also an API in fifo_gk20a.c to do the channel disable.

gr_gk20a_ctx_zcull_setup() was always passed true as last parameter,
so remove parameter.

Change-Id: I7ae6e101ec7d1ab3f6ee4e9bcc442d23dbd21247
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/787570
2015-10-23 08:30:23 -07:00
Terje Bergstrom
1eded55286 gpu: nvgpu: Use gk20a_mem_phys instead of sg_phys
There were still a couple of places using sg_phys directly. Use new
gk20a_mem_phys() to make the code shorter.

Change-Id: I6eb9b14e0c14a27ec39bacd06ab24e31e99769ca
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/717502
2015-04-04 19:00:43 -07:00
Terje Bergstrom
7290a6cbd5 gpu: nvgpu: Implement common allocator and mem_desc
Introduce mem_desc, which holds all information needed for a buffer.
Implement helper functions for allocation and freeing that use this
data type.

Change-Id: I82c88595d058d4fb8c5c5fbf19d13269e48e422f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/712699
2015-04-04 18:59:26 -07:00
Sam Payne
ce3afaaaf6 gpu: nvgpu: disable ce2 interrupts when unhandled
ce2 interrupts enabled only on gk20a and gm20b when
interrupts are handled through hal

Change-Id: Ib570db8f5f41e71e768b95e781153ec8a5d20015
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/677447
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-04-04 18:08:17 -07:00
Terje Bergstrom
bdb34abd93 gpu: nvgpu: Per-chip PBDMA signature
PBDMA HW signature depends on the chip.

Change-Id: If57d721d9bb77a090f967930a1aa2037bf4a16fe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672922
2015-04-04 18:07:37 -07:00
Terje Bergstrom
d65f23cb9a gpu: nvgpu: Support 512 channels in gm20b
Retrieve channel count from gm20b specific header instead of the
gk20a header. This increases channel count from 128 to 512.

Change-Id: I96d4887432852795f7f526e33f0d3d2458f3af0e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/500623
2015-03-18 12:11:23 -07:00
Aingara Paramakuru
1fd722f592 gpu: nvgpu: support gk20a virtualization
The nvgpu driver now supports using the Tegra graphics virtualization
interfaces to support gk20a in a virtualized environment.

Bug 1509608

Change-Id: I6ede15ee7bf0b0ad8a13e8eb5f557c3516ead676
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/440122
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2015-03-18 12:11:01 -07:00
Terje Bergstrom
07a90307b0 gpu: nvgpu: Implement gm20b fifo recovery
Implement gm20b version of fifo recovery.

Bug 1495967

Change-Id: I2792b217178d157427f49e0c450d4ac620399962
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/394138
Reviewed-on: http://git-master/r/401402
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
2015-03-18 12:09:42 -07:00
Kevin Huang
ea3d83d98b video: tegra: host: add gm20b channel op
Bug 1450792

Change-Id: I09f7c727a773178613fe555eb025ac324da0008e
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/381128
Reviewed-on: http://git-master/r/396373
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
2015-03-18 12:09:39 -07:00