Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ltc
sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507563
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Pbdma which encountered the ctxnotvalid interrupt will stall and
prevent the channel which was loaded at the time the interrupt fired
from being swapped out until the interrupt is cleared.
CTXNOTVALID pbdma interrupt indicates error conditions related
to the *_CTX_VALID fields for a channel. The following
conditions trigger the interrupt:
* CTX_VALID bit for the targeted engine is FALSE
* At channel start/resume, all preemptible eng have CTX_VALID FALSE but:
- CTX_RELOAD is set in CCSR_CHANNEL_STATUS,
- PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or
- PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE
JIRA GPUT19X-47
Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1329372
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In gv11b fbhub num_ltcs is read only, even though
register spec says it is rw. The number of ltcs
are populated by hw and no need for sw to set those
values.
GPUT19X-70
Change-Id: Ib9861894cacb70cf54b4958083e55d39a3a85e19
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1497992
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
tegra/linux path was created to separate Tegra kernel specific
dependencies from common Linux specific dependencies. The split has
not really worked, so merge tegra/linux to common/linux.
JIRA NVGPU-38
Change-Id: I9efe078bfa5dfbef49408db9d8a3738dfda8bd1d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1505169
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Without non-cacheable, gpu filled subcontext data not visible
to cpu without additional l2 flush. Similarly, there will be issues
where cpu updates to subcontext header will not visible to gpu without
additional l2 flush.
Making subcontext header mapping non-cacheable fixes this issue.
Bug 1937331
Change-Id: I8e25b7cac165e7481eec7c9f1f93bc7992183c46
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1505283
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
After enabling l2 write back in gv11b, for committing all
dirty data to sysmem correctly:
Added one fb_flush before l2_flush to commit dirty hshub data to l2/sysmem.
Added one more fb_flush after l2_flush, to commit any new dirty data on
hshub to sysmem.
This done by implementing gv11b specific l2_flush function.
Bug 1937331
Change-Id: Ie30edb12c98c4021783c88750bb4c4ca62e4a7ca
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1503385
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This patch:
- Adds a PMU command needed for enabling ELPG.
i.e. command to update sub-feature mask to enable ELPG.
- Adds a new version of PG-GR init param command function
which uses updated command interface.
JIRA GPUT19X-20.
Change-Id: If969c018e2e28264fdc9c897892eb28b021d12f2
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1504873
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Preempt type should be set to tsg and id should be set to tsgid
in fifo_preempt_r(). Preempt type channel and id set to channel
id does not initiate preemption.
Bug 200289427
Bug 200292090
Bug 200289491
Change-Id: I2ae96c0b9ca8a88a8405f42775744f0879994887
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1497877
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We added duplicate common/linux/nvhost_priv_t19x.h so that the definition of
struct nvgpu_nvhost_dev is available in nvgpu-t19x repo
But instead of duplicating the file, directly include original file with
path #include "common/linux/nvhost_priv.h
Jira NVGPU-29
Change-Id: I5d373227f0f6b2b4670d2fd3ad433a4655df8e4f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1499167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Remove use of linux specifix header files
<linux/nvhost.h> and <linux/nvhost_t194.h>
and use nvgpu specific header file
<nvgpu/nvhost_t19x.h> instead
This is needed to remove all Linux dependencies
from nvgpu driver
Replace all nvhost_*() calls by
nvgpu_nvhost_*() calls from new nvgpu library
Jira NVGPU-29
Change-Id: I32d59628ca5ab3ece80a10eb5aefa150b1da448b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1494648
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Add new abstraction file common/linux/nvhost_t19x.c
for all nvhost APIs exported from linux/nvhost_t194.h
This file will be compiled only if config
CONFIG_TEGRA_GK20A_NVHOST is set
Export the new headers from file <nvgpu/nvhost_t19x.h>
Also add dummy private header file nvhost_priv_t19x.h
to store definition of private structure nvgpu_nvhost_dev
This file should be deleted when nvgpu-t19x repo
is merged into common nvhost repo
Jira NVGPU-29
Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1493792
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
We pass (struct device_attribute *) to gp10b_ecc_stat_create()
and gr_gp10b_ecc_stat_create() and then assign a memory
allocation to this pointer
But since this pointer is local copy to function, static
pointer variables are never set in gr_gp10b_create_sysfs()
This also results in a resource leak since we never free
the storage assigned to local variable
Fix this by adding and passing correct parameter
(struct device_attribute **) so that the address of the
allocation is returned to the caller correctly
Bug 200291879
Coverity id : 2567934
Change-Id: I1b1d329265f4d32739abbbe3a4e419a2af62b874
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1495907
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Only for following instances, mssnvlink <-> hshub will
be interacting in gv11b:
NV_ADDRESS_MAP_MSS_NVLINK_1_BASE
NV_ADDRESS_MAP_MSS_NVLINK_2_BASE
NV_ADDRESS_MAP_MSS_NVLINK_3_BASE
NV_ADDRESS_MAP_MSS_NVLINK_4_BASE
NV_ADDRESS_MAP_MSS_NVLINK_0_BASE doesnt interact with gv11b hshub,
so don't set those credits.
GPUT19X-116
Change-Id: I8c6737293699444ddb1e27936f1c4a2e61871c29
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1493641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
fb_timeout and pbdma_timeout values are already set by h/w to init
values. No need to reinitialize.
JIRA GPUT19X-22
Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1493458
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In pri-silicon environment netlist names keep on changing.
So to keep software backward compatible. do not set
net name. So driver will check available firmwares and
will pick-up the firmware that matches with current hw netlist
major revision.
Change-Id: I6083879fb67481be03bad1eaf6a10d0cb6eb7c09
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1485135
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In t19x, host1x supports sync point through memory mapped
shim layer. So sync-point operations implemented through
semphore methods signaling to this sync-point shim layer.
Added relevant hal functions for this in fifo hal.
JIRA GPUT19X-2
Change-Id: Ia514637d046ba093f4e5afa6cbd06673672fd189
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1258235
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
nvgpu_log/info/warn/err() internally add a \n to the end of the message.
Hence, callers should not include a \n at the end of the message. Doing
so results in duplicate \n being printed, which ends up creating empty
log messages. Remove the duplicate \n from all messages.
Bug 1928311
Change-Id: I21c141934a125e0cc0cead9fb19fa6502235cf06
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-on: http://git-master/r/1487233
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
(1) Re-arrange the structure for ecc counters reporting so multiple
units can be managed
(2) Add counters and handling for additional GPC counters
JIRA: GPUT19X-84
Change-Id: I74fd474d7daf7590fc7f7ddc9837bb692512d208
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485277
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Adding support for ISR handling of GPCCS exceptions
and GCC ECC support
JIRA: GPUT19X-83
Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480997
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache
Volta Resiliency Id - Volta-634
JIRA GPUT19X-113
JIRA GPUT19X-99
Bug 1807553
Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This CL covers the following parity support (uncorrected error),
1) SM's LRF
2) SM's CBU
Volta Resiliency Id - Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-110
Bug 1775457
Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1481791
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
