Currently, nvgpu_vidmem_buf_access_memory() accepts u64 size/offset
values to access memory. However, underlying nvgpu_mem read and write
functions truncate size/offset value to u32. So, any VIDMEM buffer
larger than 4GB will be inaccessible above 4GB by userspace IOCTL.
This patch updates nvgpu_mem_rd_n() and nvgpu_mem_wr_n() to accept
u64 size and u64 offset values.
BUG-2489032
Change-Id: I299742b1813e5e343a96ce25f649a39e792c3393
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2143138
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This patch fixes violations for below listed rules in
nvgpu/common/mm/as.c.
MISRA Rule 10.3 forbids implicit conversion of an essential type to
different or narrower essential type.
MISRA rule 10.4 requires essential type of left hand operand to be same
as right hand operand.
MISRA Rule 21.8 requires the size_t argument of strncpy() to be less
than length of the source string.
Change-Id: I4ff1e4dbbd602baf906af8230c6902249e0223e8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142566
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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Move the PTE size computation from MM to VM where it belongs. This
function is only ever used in vm.c so move it there and make it
static.
This is part of the broader effort to cleanup the top level unit
header files and only expose functions needed by other units in the
top level unit header files.
JIRA NVGPU-3544
Change-Id: Ifd8ed36723eb62e19a7e6563ef52dc9c3adb3f52
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128075
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.
This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.
Jira NVGPU-3476
Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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The vm object num_user_mapped_buffers was declared as an int. However,
it is an unsigned value. Being a signed value required a cast to
unsigned when calling nvgpu_big_zalloc() which causes a CERT-C INT31
violation. So, avoid the cast and use an unsigned type. And fix related
INT30 violations related to num_user_mapped_buffers as well.
To avoid introducing new MISRA/CERT-C violations, update the upstream
user of these changes, fifo/channel.c and make the equivalent uses of
this value, num_mapped_buffers a u32 as well.
JIRA NVGPU-3517
Change-Id: I6f6d9dfe4a0ee16789b8cd17b908a3f3f9c4a40c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127427
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Rule INT31 requires integer conversions do not result in losing or
misinterpreting data. For most cases, use the safe cast operations.
For one case, the conditional operator was being used for s16 values
which were being promoted to ints. So, replace the conditional operator
with an if statement.
JIRA NVGPU-3517
Change-Id: Iac466911b0dd3893e7e7a188e372272b14591b60
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127425
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MISRA rule 21.1 states that #define and #undef shall not be used on
a reserved identifier or reserved macro name. Fix violations of
rule 21.1 in bitops unit.
MISRA rule 21.2 states that a reserved identifier or macro name
shall not be declared. Fix violations of rule 21.2 in bitops unit.
Jira NVGPU-3545
Change-Id: Ie551d7ce5e19287107403f2c991bcc55bd11a4e8
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125842
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CERT-C INT32 states to ensure that operations on signed integers do not
overflow. In page_table.c, the parameter lvl was triggering INT32
violations when adding to the value.
To address these violations, do two things. First, since this is
really an unsigned value, make it a u32. And rather than just make the
INT32 violations INT30 violations, use the safe operations.
JIRA NVGPU-3515
Change-Id: Iabd5e239813c695638988143ee901b1c19a0df5d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125028
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Previously initializing buddy_allocator with size=0 initialized large
memory block. With fixes in buddy_allocator_init() function, size = 0
triggered segmentation fault and so size was temporarily updated to
fixed value.
This patch updates buddy_allocator_init() function to return error if
requested size of buddy_allocator is zero. As kernel VMA is absent for
VGPU, this patch also updates nvgpu_vm_do_init() function to not
allocate kernel VMA with size = 0.
Jira NVGPU-3005
Change-Id: I568fbbff6ac2c66395d1dc5a4b35304c7f4002fb
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113190
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MISRA rule 5.7 doesn't allow reuse of tag or variable names as this
would lead to developer confusion. Patch renames page_alloc_slab_page
struct pointer's local variable name to page_ptr to resolve the
violation. Also, renames function "nvgpu_page_alloc" to
"nvgpu_page_balloc" to remove identifier name overloading.
MISRA rule 10.x forbids from casting value of composite expression to an
object with different essential type category. This patch replaces
multiplication operation to left shift operation.
MISRA rule 15.7 requires every if .. else if construct to be terminated
with an else statement. This patch updates if .. else if condition to
resolve the violation.
MISRA Rule 17.2 doesn't allow recursive call from a function to itself,
as this might lead to stack overflow. Updated nvgpu_page_allocator_init
to call nvgpu_buddy_allocator_init() directly.
MISRA rule 21.6 doesn't allow use of snprintf from standard library.
This patch replaces snprintf call with string functions.
JIRA NVGPU-3338
Change-Id: Ic8cb956edb3c72811752008de192e6e8ba12463e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
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MISRA Rule 17.2 prohibits indirect recursion. nvgpu_allocator_initi()
was calling nvgpu_page_allocator_init(), which in turn was calling back
to nvgpu_allocator_init() to init a buddy allocator. Rather than
calling back to nvgpu_allocator_init(), have nvgpu_page_allocator_init()
call nvgpu_buddy_allocator_init() directly.
JIRA NVGPU-3332
Change-Id: I1102450ae26dda355d5f5dcc3ddb195871c26c32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114028
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
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Fix Rule 4.7 violation for failing to check return value.
Fix Rule 14.2 violation when using the nvgpu_list_for_each_entry_safe
macro by refactoring to use a while loop.
Fix Rule 13.5 violation for using a nvgpu_timeout_expired_msg() in a
logical expression because it can have side effects. This was fixed by
refactoring the while loop.
JIRA NVGPU-3332
Change-Id: I1454db82f766a06d3ffd549de43aad6e1b632928
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114026
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Below MISRA 10.4 violation is reported in nvgpu.common.mm.vm_area
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/vm_area.c:234:
misra_violation: The condition clause expression of the for loop has
persistent side-effects.
Fix this by replacing with a while loop.
Jira NVGPU-3330
Change-Id: Ica6882d6c73dc0d74159f34279d8f91b7494c65c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117059
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Below MISRA 21.6 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".
Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.
Jira NVGPU-3333
Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
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Below MISRA 10.4 violation is reported in nvgpu.common.mm.nvgpu_sgt
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/nvgpu_sgt.c:131:
misra_violation: Essential type of the left hand operand
"mem->mem_flags & 8ULL" (unsigned) is not the same as that of the
right operand "0ULL"(signed).
Fix this by changing right hand operand to 0U.
Jira NVGPU-3334
Change-Id: Ib28bfce363a807ba9f8fa9df9cbb02c636a74898
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117034
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Below MISRA 17.7 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:645:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.bus.bar1_bind" is unused.
Fix this by checking return value and returning an error in
case of failure.
Jira NVGPU-3331
Change-Id: Iab43d630163af782d3cc87989a64062516a4cd92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116706
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