Commit Graph

18 Commits

Author SHA1 Message Date
Divya Singhatwaria
77e3a8c5e4 gpu: nvgpu: ga10b: Add request_idle ce ops
Issue observed:
- In GA10B, it was observed that after recovery happens
  ELPG does not engage.
- It was because, after CE reset, when nvgpu_submit_twod test
  was run to engage ELPG, IDLE_FLIPPED_PWR_OFF signal was asserted.
- This means that when ELPG was engaged (engine is in PWR_OFF),
  some idle signal flips (becomes non-idle) and this causes
  IDLE_SNAP. After IDLE_SNAP is hit, ELPG will not engage further.
- After debugging from WAVES, it was observed that:
  LCE0/LCE1 are not done with the reset sequence.
- The state of these LCE is RESET0. A pri request (pri read
  to NV_CE_PCE_MAP register in CE) is seen that kicks it out of
  RESET0. After this state, it goes through few states to update
  some internal states (states RESET1/RESET2/PCE_MAP etc) and then
  eventually settles down to IDLE state.

Solution:
- Read ce_pce_map_r register in recovery sequence (after ce reset).
- It is observed that when this read is added recovery is complete
  and post that when nvgpu_submit_two test is executed, ELPG is engaging.
- This means that a pri read is needed after CE reset so that it settles
  to idle state properly and post that ELPG can engage properly.

Bug 200734258

Change-Id: I5bb84921ca62a740fde81ffe6c29ccde4ebb341b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554493
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2021-07-15 10:05:02 -07:00
tkudav
0526e7eaa9 gpu: nvgpu: Create CIC-mon and CIC-rm subunits
common.cic unit is divided into common.cic.mon and common.cic.rm
based on rm and mon process split.

CIC-mon subunit includes the code which is utilized in critical
interrupt handling path like initialization, error detection and
error reporting path. CIC-rm subunit includes the code corresponding
to rest of interrupt handling(like collecting error debug data from
registers) and ISR status management (status of deferred interrupts).

Split the CIC APIs and data-members into above two subunits.

JIRA NVGPU-6899

Change-Id: I151b59105ff570607c4a62e974785e9c1323ef69
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2551897
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2021-07-02 09:57:56 -07:00
Sagar Kadamati
3e43f92f21 gpu: nvgpu: add ga10b & ga100 sources
Mass copy ga10b & ga100 sources from nvgpu-next repo.
TOP COMMIT-ID: 98f530e6924c844a1bf46816933a7fe015f3cce1

Jira NVGPU-4771

Change-Id: Ibf7102e9208133f8ef3bd3a98381138d5396d831
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524817
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Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-06-17 12:56:16 -07:00
Tejal Kudav
9f43914933 gpu: nvgpu: Move Intr handling common code to CIC
CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.

Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic

JIRA NVGPU-6899

Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2021-05-31 19:37:31 -07:00
Vedashree Vidwans
2514814851 gpu: nvgpu: common.ce fix MISRA 5.7 errors
Rule 5.7 doesn't allow an identifier to be reused. This patch renames
identifier "ops" to resolve this violation.

Jira NVGPU-6281

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I02da8db6406ccc44b7d8c3037dfd2b062250878f
(cherry-picked from commit 659e54c96d5c8db8ab2f76cd110a11f1e2270c36)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2527279
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2021-05-17 12:56:19 -07:00
Rajesh Devaraj
7e6dcade98 gpu: nvgpu: remove reporting of rstg and nonblock pipe
RSTG_ECC errors are not expected to occur in gv11b since it does
not contains R-stage memory. Hence, the reporting of this error has
been replaced with BUG().

CE_NONBLOCK_PIPE interrupt is used for notification of completion
of copy operation and it is not an error interrupt. Further, this
notification has not been used by CUDA. So, the reporting of CE
NONBLOCK_PIPE has been removed.

JIRA NVGPU-6124
Bug 200616002

Change-Id: Idf027cc27cf854188503d4d4f07d0f54af1da164
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2427125
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
b436877190 gpu: nvgpu: replace nvgpu_log with nvgpu_err for CE stall interrupts
Replace nvgpu_log with nvgpu_err for ce stall interrupt messages.

Jira: NVGPU-5034

Change-Id: I794461431ec6fadc322fe05a4f53f619c5370052
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335702
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Sagar Kamble
98e84b8046 gpu: nvgpu: fix the includes in ce unit
As per the coding guidelines, absolute paths in header inclusion are
prohibited. Fix such instances in ce unit.

JIRA NVGPU-5075

Change-Id: I63ebc576e72a8a666a2c9d207dafc4e96473ea32
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303087
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Sagar Kamble
6fe794bc98 gpu: nvgpu: prepare ce_app.h header
In preparation for SWUD of CG unit, separate CE app related APIs
into separate header ce_app.h.

JIRA NVGPU-4143

Change-Id: I9be8a4f2eee3aaf3af71f5843f957052064d9651
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2221660
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Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2020-12-15 14:10:29 -06:00
Philip Elcan
9169e8c048 gpu: nvgpu: mc: move mc declarations to mc.h
Move declarations that belong to mc from gk20a.h to mc.h where they
belong.

JIRA NVGPU-2532

Change-Id: I91934ff60e2735c61d16459c04507fed6e1c96d7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214421
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2020-12-15 14:10:29 -06:00
Rajesh Devaraj
935c5f6578 gpu: nvgpu: fix misra violations in SDL
This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:

- misra_c_2012_directive_4_7_violation: Calling function
  "nvgpu_report_*_err()" which returns error information without testing
  the error information.

JIRA NVGPU-4025

Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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2020-12-15 14:05:52 -06:00
Thomas Fleury
3659c2f0c1 gpu: nvgpu: tu104: do not map PCE0 to any LCE
Configure PCE/LCE mapping as follows:
- PCE0 (HSHUB) is unconnected
- GR_CE1, LCE4 share PCE1 (HSHUB)
- LCE2 gets PCE2 (FBHUB)
- GR_CE0, LCE3 share PCE3 (FBHUB)

Bug 2494068

Change-Id: I25ddf7976f67f3faf3a9ef8cf79dcd9619ab5e63
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151041
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2019-07-18 14:49:59 -07:00
Deepak Nibade
0e6a305c6a gpu: nvgpu: set CE prod values
Add g->ops.ce.init_prod_values() hal for gv11b and tu104 to initialize
PROD values of CE unit

Bug 2526212

Change-Id: I8e516b292622e09c537feb7830392648116baa7c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150874
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2019-07-17 17:33:53 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-03 02:46:15 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Thomas Fleury
8052ce1d9f gpu: nvgpu: remove inclusion of top hw header in ce
We now use g->ops.top.get_num_lce to retrieve number of logical
copy engines. Remove inclusion of top hw header.

Jira NVGPU-2013

Change-Id: If401d363776c21a3afec084e3fc440b2ba65bcb2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110489
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-02 15:57:05 -07:00
Thomas Fleury
5e12623785 gpu: nvgpu: add HALs for num lce and bar2 fault
Added the following HALs:
- top.get_num_lce
- ce.mthd_buffer_fault_in_bar2_fault

Jira NVGPU-1992

Change-Id: Ib0bd8c862d1f847621c1c04ed3459d17f533009d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099089
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2019-04-19 13:55:53 -07:00
Thomas Fleury
1160f083d4 gpu: nvgpu: move ce code to common/ce and hal/ce
Merged gk20a_ce_delete_context and gk20a_ce_delete_context_priv.

Renamed
- gk20a_init_ce_support -> nvgpu_ce_init_support
- gk20a_ce_destroy -> nvgpu_ce_destroy
- gk20a_ce_suspend -> nvgpu_ce_suspend
- gk20a_ce_create_context -> nvgpu_ce_create_context
- gk20a_ce_delete_context -> nvgpu_ce_delete_context
- gk20a_ce_execute_ops -> nvgpu_ce_execute_ops
- gk20a_ce_prepare_submit -> nvgpu_ce_prepare_submit
- gk20a_ce_put_fences -> nvgpu_ce_put_fences
- gk20a_ce_delete_gpu_context -> nvgpu_ce_delete_gpu_context
- gk20a_ce_get_method_size -> nvgpu_ce_get_method_size
- gk20a_gpu_ctx -> nvgpu_ce_gpu_ctx
- gk20a_gpu_ctx_from_list -> nvgpu_ce_gpu_ctx_from_list
- gk20a_ce_app -> nvgpu_ce_app
- gk20a_ce_debugfs_init -> nvgpu_ce_debugfs_init
- gk20a_get_valid_launch_flags -> nvgpu_ce_get_valid_launch_flags
- gk20a_ce2_isr -> gk20a_ce2_stall_isr
- gp10b_ce_isr -> gp10b_ce_stall_isr
- gv11b_ce_isr -> gv11b_ce_stall_isr

Inlined
- ce*_nonblockpipe_isr
- ce*_blockpipe_isr
- ce*_launcherr_isr

Added ce_priv.h for ce private definitions.

Moved files to common/ce and hal/fifo/ce
- ce2.c -> common/ce2/ce.c
- ce2_gk20a.c -> hal/ce/ce2_gk20a.c
- ce2_gk20a.h -> hal/ce/ce2_gk20a.h
- ce_gp10b.c -> hal/ce/ce_gp10b.c
- ce_gp10b.h -> hal/ce/ce_gp10b.h
- ce_gv11b.c -> hal/ce/ce_gv11b.c
- ce_gv11b.h -> hal/ce/ce_gv11b.h

Updated makefiles and #include directives

Jira NVGPU-1992

Change-Id: Ia6064bf51b7a254085be43a112d056cb6fb6c3b2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093503
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2019-04-19 13:55:11 -07:00