Allocated the following two waiter objects for sync point waith path:
Job tracking and CE threads.
2. QNX channel specific job tracking thread.
The above implementation is only available for QNX.
For Linux, waiter index is skipped.
JIRA NVGPU-3009
Change-Id: If12ad1dc90a24a7b922b205829ca335805c02c3d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292080
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Current volt unit has multiple header files under pmuif folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within volt unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_volt_inf.h from pmuif which only
volt can access.
All public items are moved into include/volt.h which other units can
access
This will help in documentation of items for public items.
NVGPU-4492
Change-Id: Id40bf4922408a55f1e67d071be726839ac57718f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2289114
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From gv11b onwards, FECS ucode returns an ACK for set watchdog
timeout method. Failure to wait for this ACK was leading to races,
and in some cases, the ACK could be mistaken for the reply to the
next method.
In particular, this happened for the discover golden image size
method which is sent after set watchdog timeout.
With instrumented FECS ucode, it takes longer for the code to
process the set watchdog timeout method, and the write to ack
that method could happen after nvgpu driver clears the mailbox to
send the discover image size method.
With an invalid golden context image size, FECS ended up causing
an MMU fault while attempting to save past allocated buffer.
Added NVGPU_GR_FALCON_METHOD_SET_WATCHDOG_TIMEOUT to be used with
gops_gr_falcon.ctrl_ctxsw, and implemented 2 variants:
- gm20b_gr_falcon_ctrl_ctxsw, without ACK
- gv11b_gr_falcon_ctrl_ctxsw, with ACK
Added NVGPU_GR_FALCON_SUBMIT_METHOD_F_LOCKED flag to allow
executing above method without re-acquiring FECS lock. Longer term,
the 'flags' could be added to gop_gr_falcon.ctrl_ctxsw parameters.
Use gops_gr_falcon.ctrl_ctxsw instead of register writes to invoke
set watchdog timeout method in gm20b_gr_falcon_wait_ctxsw_ready.
Also replaced calls to gm20b_gr_falcon_ctrl_ctxsw to
gops_gr.falcon.ctrl_ctxsw when appropriate, since there are
multiple variants (gm20b, gp10b and gv11b).
Last, fixed clearing of mailbox 0 in gm20b_gr_falcon_bind_instblk.
Bug 200586923
Change-Id: I653b9a216555eec8cd4bb01d6f202bc77b75a939
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287340
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Fix the issue in DIV_ROUND_CLOSEST implementation. Current
implementation will have issues for an input of two negative
numbers. For example, Input values of a = -13 and divisor = -5
should ideally give result as 3. But because of the third condition
check ie.(val) > 0, the result would be given incorrectly as 2
with the current implementation. Modify the condition to handle
two negative number division.
Jira NVGPU-4478
Change-Id: Ifb3f58b4ff742abbb59fda328c1b5facdcb1b38b
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284320
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Address following code inspection gaps:
1. Fix the header guards for *gating_reglist.h files.
2. Remove ctxsw_firmware slcg/blcg mention from doxygen
comments as that hal is removed.
3. Add therm slcg function and description to doxygen.
4. Add defgroups for including enums/macros in swud.
JIRA NVGPU-4797
Change-Id: I26f2e50b556bcac1486175143ab070f0c3c56c36
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2288030
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Address following issues uncovered during inspection:
1. Remove the doxygen comment from nvgpu_wait_for_deferred_interrupts
definition.
2. Use NVGPU_MC_INTR_STALLING instead of hardcoding the index.
3. Define doxygen groups NVGPU_MC_UNIT_ENUMS,
NVGPU_MC_INTR_TYPE_DEFINES, NVGPU_MC_INTR_UNIT_DEFINES and
NVGPU_MC_INTR_ENABLE_DEFINES.
4. Update the doxygen comments.
5. Fix the cleanup, typo in the description of the test
test_wait_for_deferred_interrupts.
JIRA NVGPU-4795
Change-Id: Ifc6756832aabf9dd42ee174eb1373495e6d38c86
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287627
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For integration testing in safety build, we need to test ctxsw firmware
error codes. inorder to test this, we need some instrumentation in
nvgpu driver.
Added below instrumentation for CTXSW FW error code integration testing.
1. Reduce the ctxsw watchdog time, so ctxsw watchdog always triggered.
Use CONFIG_NVGPU_CTXSW_FW_ERROR_WDT_TESTING for testing watchdog
2. Submit unsupported method to CTXSW FW, it will trigger err.
Use CONFIG_NVGPU_CTXSW_FW_ERROR_CODE_TESTING for testing err code.
JIRA NVGPU-4471
Change-Id: Ib45a946b3e38d3b6dd5bbee277c5d3e7c55521c0
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284048
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Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
- "include/trace/events/gk20a.h" file was having GPL2 license
(which should not used for QNX code). This file was used for
compiling linux userspace driver("libnvgpu-drv.so") and was used for
unit testing on QNX.
- This patch removes stubs in "include/trace/events/gk20a.h" file.
(which were used for linux userspace driver.)
- For QNX driver, "nvgpu_rmos/trace/events/gk20a.h" was used.
This patch moves that file to "include/nvgpu/posix/trace_gk20a.h" and
does relevant license change. This same file will be used for linux
userspace driver.
- This patch also creates a new file "include/nvgpu/trace.h" which
selects proper trace file depending on the config.
Bug 2802414
Change-Id: Icdfb251e5698073f986753a969e804161af3ecc5
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286388
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Xavier Chip Product POR was updated to 20G only. No more qual work
happening for 16G. So we do not plan to support 16G. Now that we have
a single speed left, remove the code added to support nvlink speed from
VBIOS as it is redundant.
JIRA NVGPU-2964
Change-Id: Icd71ebb8271240818e36d40bf73c60f0c5beb6bf
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2284175
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-Created perf.h file and moved all private functions
and structures into it
-Created single sw_setup/pmu_setup for whole perf
unit
-Changed public function and structure names as per
standard format
-Deleted lpwr unit specific file from make file as
it is no longer used
-Removed support_vfe and support_changeseq flags as
it is no longer used
-Removed clk_set_boot_fll_clks_per_clk_domain function
as it is no longer used for tu10a
-Removed perf unit headers from pmuif folder
NVGPU-4448
Change-Id: Ia29e5b5a1a960b5474a929d8797542bf6c0eccf1
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283587
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As a part of refactoring, we need to move the volt functions from
pmu_pstate.c to volt.c as it belongs there and also move the
arbitor specific functions under CLK_ARB as they will be removed
from safety build.
This patch does the following
*Move volt setup from pmu_pstate to volt
*Move clk freq related functions into CLK_ARB
*Replace pmu.h with nvgpu_mem.h in boardobj.h
*Rename obj_volt to nvgpu_pmu_volt
NVGPU-4491
NVGPU-4492
Change-Id: I9abc96f695fce41893311982a80dc3656aaa64d6
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2282361
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
MISRA Advisory Rule 8.13 states that a pointer should point to a
const-qualified type wherever possible.
This change eliminates such violations from the use of
nvgpu_timeout_expired_msg_cpu() by marking the temporary
struct nvgpu_timeout pointer const.
Jira NVGPU-3178
Change-Id: Id0c77f2a18db29dcc1125540fdc02ab246c68092
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283774
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Coverity 2019.06 has a bug due to which it scans and reports violations
for uncompiled code. This change whitelists violations which are only
visible for the Linux build. Linux is not part of the safety build.
Therefore, these violations can be whitelisted.
Bug 2799838
Change-Id: Ief24b121741d36d1c34a117122f1d6fd3e31f35f
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2283210
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Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
The atomic counter in interrupt handler can overflow and result in
calling of BUG() which will crash the process. The equivalent
functionality can be implemented with just setting an atomic variable at
start of handler and resetting at end of handler. The wait can be longer
in case there is constant interrupts coming but ultimately it will end.
Generally the wait path is not time critical so it should not be an
issue. Also, fix the unit tests for mc.
Change-Id: I9b8a236f72e057e89a969d2e98d4d3f9be81b379
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2247819
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Update SW quiesce as follows:
- After waking up sw_quiesce_thread, nvgpu_sw_quiesce
masks interrupts, then disables and preempts runlists
without lock. There could be still a concurrent thread
that would re-enable the runlist by accident. This is
very unlikely and would mean we are not in mission mode
anyway.
- In sw_quiesce_thread, wait NVGPU_SW_QUIESCE_TIMEOUT_MS,
to leave some time for interrupt handler to set error
notifier (in case of HW error interrupt). Then disable
and preempt runlists, and set error notifier for remaining
channels before exiting the process.
Also modified nvgpu_can_busy to return false in case
SW quiesce is pending. This will make subsequent
devctl to fail.
Jira NVGPU-4512
Change-Id: I36dd554485f3b9b08f740f352f737ac4baa28746
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2266389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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This patch adds boundary value check for common.fifo parameters as
listed below.
1. nvgpu_channel_setup_bind() includes a condition to check that value
of num_gpfifo_entries does not exceed 2^31. Otherwise prints message and
returns error.
2. nvgpu_tsg_bind_channel() includes a condition to check if channel
subctx had ASYNC id. If true, runqueue selector is set to 1 and 0
otherwise. This check is to be moved from devctl to common.fifo.
Jira NVGPU-4817
Change-Id: Id1c9253945859c245e584b5c42b3285a6b620055
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2278613
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nvgpu_init_hal is private to the common.init unit in the driver, used
only by nvgpu_detect_chip. However, it is used extensively by the unit
tests, so it can't be static. So, hide it from doxygen, so it is not
included in SWVR traceability.
Add missing target APIs in SWUTS for init UTs.
JIRA NVGPU-4818
Change-Id: I4d8acf29e9cbafdfd26d7088f98974da3b12a8ba
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
