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2079 Commits

Author SHA1 Message Date
Deepak Nibade
a3d30adab2 gpu: nvgpu: add debugger flag for fb units 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.hal.fb unit

Jira NVGPU-3506

Change-Id: If459e623e73ce716088d9cb92c31864c26fe0d3d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132260
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:06:30 -07:00
Deepak Nibade
1112af9f8c gpu: nvgpu: add flag for global fecs trace buffer index 
Add compile time flag check CONFIG_NVGPU_FECS_TRACE for
NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER

Also add the flag check for setting NVGPU_FECS_TRACE_* characteristics
flag

Jira NVGPU-3506

Change-Id: I57f1538c852834b9be075a7b56b79fd699c04024
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132259
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:06:14 -07:00
Deepak Nibade
436549b9bf gpu: nvgpu: add cilp flag for CILP support 
Add CONFIG_NVGPU_CILP flag for CILP support across all the units

Jira NVGPU-3506

Change-Id: I0c71d38f9db6f00599a5070a8cb9d75d5b5fc351
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132258
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-13 12:05:59 -07:00
Deepak Nibade
4ac27a24bb gpu: nvgpu: add debugger flag for gr.utils unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.utils unit.

Jira NVGPU-3506

Change-Id: Iea551df287e06602949b3c2c33ebe565f0a0c921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132257
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:44 -07:00
Deepak Nibade
6ac3fc30c7 gpu: nvgpu: add debugger flag for gr.ctx unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.ctx unit.

Jira NVGPU-3506

Change-Id: I42becd6404eb12b39dca7815849425128e7e42d8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132256
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:34 -07:00
Deepak Nibade
1792e6b820 gpu: nvgpu: add debugger flag for gr.global_ctx unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.global_ctx unit.

Jira NVGPU-3506

Change-Id: I9baf468c17b9c6a2a64275ac191242fa8e01b0e1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-13 12:05:24 -07:00
Deepak Nibade
1239bf67a5 gpu: nvgpu: add debugger flag for hal.gr.ctxsw_prog unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
hal.gr.ctxsw_prog unit
Also add this flag for PM context allocation/free

Jira NVGPU-3506

Change-Id: Ib40569c7617b8b8aa3343fc89f3d8f30b1d21aa6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:14 -07:00
Sagar Kamble
556ddaf9a3 gpu: nvgpu: add support for removing comptags and cbc from safety build 
Safety build does not support compression. This patch adds support to
compile out compression related changes - comptags, cbc.

JIRA NVGPU-3532

Change-Id: I20e4ca7df46ceec175b903a6a62dff141140e787
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 10:55:27 -07:00
Kary Jin
03db4f8f33 gpu: nvgpu: add check for "vm->num_user_mapped_buffers" 
The "nvgpu_big_zalloc()" will be failed if the passed-in argument
"vm->num_user_mapped_buffers" is zero. The returned value is 16
which will bypass the NULL-check and then causes the panic.

This patch adds a check on the "vm->num_user_mapped_buffers" to
avoid the zero is passed-in the "nvgpu_big_zalloc()".

Bug 2603292

Change-Id: I399eecf72a288e13992730651a34a6cea1ef56d1
Signed-off-by: Kary Jin <karyj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123499
(cherry picked from commit fea9e05454)
Reviewed-on: https://git-master.nvidia.com/r/2130001
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-13 01:56:02 -07:00
Seshendra Gadagottu
5943f5fc9d gpu: nvgpu: fix CERT EXP34-C in common.gr.falcon 
Fixed CERT EXP34-C error in gr_falcon driver by checking for valid
nvgpu_firmware pointer, before calling nvgpu_release_firmware.

JIRA NVGPU-3622

Change-Id: Ief4973ce4b73aa5348460632693d18e6104eda47
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134674
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-12 22:19:11 -07:00
Seshendra Gadagottu
b2ed105fe5 gpu: nvgpu: fix CERT-C errors in common.gr.falcon 
Used nvgpu_safe_mult_u32 function for u32 multiplications to avoid
CERT INT 30-C errors.

JIRA NVGPU-3622

Change-Id: Id945910a586c00be0f0cdad941b17023db66b23b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134621
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-12 22:18:55 -07:00
Vinod G
6110bcf586 gpu: nvgpu: Fix MISRA 17.7 errors in gr.intr unit 
Fix MISRA 17.7 errors in gr.intr unit
misra_c_2012_rule_17_7_violation: The return value of a non-void
function is unused.

Jira NVGPU-3621

Change-Id: I7b03b8165a628decce66bf886625fe001db76a01
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134530
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-12 20:56:57 -07:00
Philip Elcan
6c1f0177ac gpu: nvgpu: mm: fix CERT-C INT30 violations in bitmap_allocator 
CERT-C INT30 requires checking for wrapping when doing arithmetic of
unsigned value. This fixes INT30 violations in bitmap_allocator.c

JIRA NVGPU-3587

Change-Id: I68dbe4ba77c668cc02e6a41a2bc1e01625eb4a8c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132541
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 16:16:23 -07:00
rmylavarapu
ebc0b3b381 gpu: nvgpu: Remove hardcoding related to Psate objs 
In P4 #25076323, we have done many hard codings in PMU
which are related to Pstate board objs. As we are sending
Pstate objs now we can remove those hardcoding in NVGPU.

NVGPU-3597

Change-Id: I8b35e6b34c71721bb84fde9ffc280cf748232dbf
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131350
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 00:46:42 -07:00
Petlozu Pravareshwar
cebf5ea159 gpu: nvgpu: release nvgpu endpt minion fw 
Release nvgpu nvlink endpt minion fw after minion
has loaded and booted successfully. This fixes
the kernel memory leak.

Bug 200448597

Change-Id: Ia15a0941275101a9713ad5c4210e0e316a080c2e
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-12 00:46:26 -07:00
rmylavarapu
b38f261981 gpu: nvgpu: Implement Pstate Board objs 
Implemented parsing and sending performance table to pmu in
form of Pstate board objs under Perf_pstate unit.

NVGPU-3472

Change-Id: If8cc6373d1a03dd8f40a93a36203fa3d7127913f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115564
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 00:45:43 -07:00
Divya Singhatwaria
5eab914e34 gpu: nvgpu: Fix MISRA violation in ACR safety code 
- Fix directive 4.7 violation
  Test the return value "err" of the function.

- Fix Rule 16.1 and 16.3 MISRA violations
  Add break-statement in "default" case.

JIRA NVGPU-3571

Change-Id: I57b098361ecefe6b69061063d1f52cda88fced18
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 22:28:24 -07:00
ajesh
a6cbfca58c gpu: nvgpu: fix MISRA violations in bitops unit 
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 22:26:41 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags 
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:46:24 -07:00
Vinod G
1daaf83dce gpu: nvgpu: Fix CERT ARR37-C errors in common.gr.ctx unit 
Cert_arr37_c_violation: Using arithmetic operator on address which
points to non-array object.
Assign all pointer operands to array's 0th index address.

Jira NVGPU-3585

Change-Id: I59c213ed6d17d2bfb6f58c649a1ec151fba2c72b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133863
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:06:06 -07:00
Thomas Fleury
0624d908cd gpu: nvgpu: unit: add channel close tests 
Add branch coverage for:
- nvgpu_channel_kill
- nvgpu_channel_close

Also, modified gk20a_free_channel as follows:
- use nvgpu_assert to check ch->g (so that it can be tested)
- make sure g is non-NULL before calling nvgpu_get_poll_timeout

Jira NVGPU-3480

Change-Id: Ie1fa231b022da47b9ef9022ae67a6b3d73c28a8b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129724
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 19:45:17 -07:00
Vinod G
0c13e9e8ad gpu: nvgpu: Fix CERT INT30-C errors in common.gr 
Fix CERT INT30-C erros in common.gr units

Unsigned integer operation may wrap. Use safe_ops macro
to fix the wrap errors.

Jira NVGPU-3585

Change-Id: I76127d8d58e1b5516370e78432754a7e7091e7be
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 07:48:58 -07:00
Thomas Fleury
6602baaf41 gpu: nvgpu: unit: add tsg setup_sw/cleanup_sw coverage 
Add unit test for:
- nvgpu_setup_sw
- nvgpu_cleanup_sw

Made nvgpu_tsg_init_support return void, since it cannot fail.

Jira NVGPU-3476

Change-Id: Ifff115e98c097375d7920b79ae9e13657d54a357
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124512
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-09 22:55:18 -07:00
Vinod G
4201f58e1e gpu: nvgpu: Add utils header for posix 
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle
the CERT-C wrap issues.

Jira NVGPU-3411

Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130453
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-07 17:05:23 -07:00
Philip Elcan
60c3be3ca9 gpu: nvgpu: mm: fix CERT-C INT32 violations in page_allocator 
CERT-C Rule INT32 requires checking that signed values do not wrap when
doing arithmetic operations. The INT32 violations in page_allocator were
actually unsigned values, so change them to u32 and use safe ops.

JIRA NVGPU-3586

Change-Id: I7c7fbf52c2f55a9d47d86c2b01be0ab222d3d65e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131160
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-07 09:06:04 -07:00
Philip Elcan
fbbfc9717f gpu: nvgpu: mm: fix CERT-C INT31 violations in page_allocator 
CERT-C Rule INT31 requires checking that no data is lost when doing
casts, so use the safe cast operations in page_allocator.c

JIRA NVGPU-3586

Change-Id: I0cf0de7eda0c117a65a08930dbc70f9c699a0219
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131159
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2019-06-07 09:05:55 -07:00
Philip Elcan
0a645e66ee gpu: nvgpu: mm: fix CERT-C violations in page_allocator 
CERT-C Rule INT30 requires checking for values wrapping when doing
arithmetic operations on unsigned values. Use the safe ops or asserts to
ensure unsigned arithmetic operations will no wrap.

JIRA NVGPU-3586

Change-Id: Ia1fc05711520135e788023e0614c70778c076f6a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131158
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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 2019-06-07 09:05:46 -07:00
Lakshmanan M
57170db65a gpu: nvgpu: fifo: Call os specific channel open only for kernel mode submit 
Restricted the os specific channel open only for kernel mode submit.
For linux, g->os_channel.open is just noop.
For QNX, nvgpu creates the sync point notifier thread for
job tracking. This job completion tracking is only required
for kernel mode submit. This sync point notifier thread
is not required for user mode submit.

JIRA NVGPU-2944

Change-Id: Ie37824aac3609090ef9da378202dbc211a2eb0b3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131386
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:29:50 -07:00
Deepak Nibade
649a2b57a8 gpu: nvgpu: add debugger flag for hal.gr.gr unit 
Add NVGPU_DEBUGGER flag for common.hal.gr.gr unit and corresponding
hals.

Also add this flag for deferred reset functionality

Jira NVGPU-3506

Change-Id: Iee4fbc1305346bb4d779cd69e8fd5539cb07206b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130149
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:44 -07:00
Deepak Nibade
d315f2a7e2 gpu: nvgpu: add debugger flag for perf units 
Add NVGPU_DEBUGGER flag for common.gr.perfbuf and common.hal.gr.perf
units

Jira NVGPU-3505

Change-Id: Ic01324304114e3fbaf018fd3bd892ccaa655b9ae
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:29 -07:00
Deepak Nibade
c5f5eb896c gpu: nvgpu: add debugger flag for hwpm_map units 
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:14 -07:00
Deepak Nibade
455b0da253 gpu: nvgpu: add debugger flag for regops support 
Add NVGPU_DEBUGGER flag for regops API and hals

Jira NVGPU-3505

Change-Id: I9f2b850c881bf05f8ba5b6ef1f59f0d73a948cde
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130146
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:27:58 -07:00
Alex Waterman
3d318e1d1d gpu: nvgpu: Move PTE size computation to VM 
Move the PTE size computation from MM to VM where it belongs. This
function is only ever used in vm.c so move it there and make it
static.

This is part of the broader effort to cleanup the top level unit
header files and only expose functions needed by other units in the
top level unit header files.

JIRA NVGPU-3544

Change-Id: Ifd8ed36723eb62e19a7e6563ef52dc9c3adb3f52
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128075
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:27:43 -07:00
Nitin Kumbhar
e0061b8daa gpu: nvgpu: fix sim STR30 CERT C violations 
Make path a pointer to const char to avoid attempt to
modify string literal.

Error: CERT STR30-C:
drivers/gpu/nvgpu/common/sim/sim_netlist.c:363:
cert_violation: Assigning or casting string literal
 ""GRCTX_GEN_CTX_REGS_BASE_INDEX"" to a pointer to non-const.

Jira NVGPU-3560

Change-Id: I22dacbbd210a43c41aef2532c5ddb1429d5c9153
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122101
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:26:48 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety 
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 06:55:58 -07:00
Vinod G
20b974e724 gpu: nvgpu: Add flag to rop_mapping hal function 
Add NVGPU_GRAPHICS flag to support the rop_mapping hal function and
files which refer this function.
Use only when this flag is defined.

Jira NVGPU-3584

Change-Id: I49b10bb772306ba20004b3836596ea43cf0e1775
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130649
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 22:56:21 -07:00
Vinod G
1ad54446da gpu: nvgpu: Add flag to map_tiles functions 
Add NVGPU_GRAPHICS flag to support the nvgpu_gr_config_init_map_tiles
and map_tiles related functions and variables.
Use only when this flag is defined.

Jira NVGPU-3583

Change-Id: Ib31a7445bcc573a127d1902bc19fc2aae9548d0f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130616
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 22:56:12 -07:00
Philip Elcan
b127d668ab gpu: nvgpu: mm: fix CERT-C INT30 violations in buddy_allocator 
Rule INT30 requires checking for unsigned value overflow. Use the safe
arithemetic ops or check with nvgpu_assert() before doing arithmetic
operation.

JIRA NVGPU-3563

Change-Id: I495dae8f9d471db93c0526cd44b7b5a7845aec1e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128588
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 15:54:53 -07:00
Philip Elcan
dcab84e6d7 gpu: nvgpu: mm: check for valid base in buddy_allocator 
Add a validity check for the base value passed to
nvgpu_balloc_fixed_buddy_locked(). Without this check, overflow
arithmetic can occur when balloc_base_shift() is called.

JIRA NVGPU-3563

Change-Id: I0194486d4c6d68dc338b8ad59f031007380b49d0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128586
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 15:54:35 -07:00
Thomas Fleury
97762279b7 gpu: nvgpu: make nvgpu_init_mutex return void 
Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.

This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.

Jira NVGPU-3476

Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 10:25:52 -07:00
Philip Elcan
591990212a gpu: nvgpu: mm: fix CERT-C ARR38 violation in vm.c 
Rule ARR38 requires checking or array ranges passed to library
functions. Fix case where strncpy was potentially called with an
insufficient length.

JIRA NVGPU-3517

Change-Id: I719260e70f53e9e53d4702e146f5a87e68738d06
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127428
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 15:15:42 -07:00
Philip Elcan
f83447d134 gpu: nvgpu: mm: make num_user_mapped_buffers a u32 
The vm object num_user_mapped_buffers was declared as an int. However,
it is an unsigned value. Being a signed value required a cast to
unsigned when calling nvgpu_big_zalloc() which causes a CERT-C INT31
violation. So, avoid the cast and use an unsigned type. And fix related
INT30 violations related to num_user_mapped_buffers as well.

To avoid introducing new MISRA/CERT-C violations, update the upstream
user of these changes, fifo/channel.c and make the equivalent uses of
this value, num_mapped_buffers a u32 as well.

JIRA NVGPU-3517

Change-Id: I6f6d9dfe4a0ee16789b8cd17b908a3f3f9c4a40c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127427
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 15:15:33 -07:00
Philip Elcan
e1094c4800 gpu: nvgpu: mm: fix CERT-C INT32 violations in vm.c 
Rule INT32 is to prevent overflowing signed integers. In vm.c, change
objects to unsigned as they should never be negative, and make sure they
do not overflow.

JIRA NVGPU-3517

Change-Id: I0dc236d167efb3eaea2c167282017b66583e4cc5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127426
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 15:15:24 -07:00
Philip Elcan
c2bf4a4e8f gpu: nvgpu: mm: fix CERT-C INT31 violations in vm.c 
Rule INT31 requires integer conversions do not result in losing or
misinterpreting data. For most cases, use the safe cast operations.

For one case, the conditional operator was being used for s16 values
which were being promoted to ints. So, replace the conditional operator
with an if statement.

JIRA NVGPU-3517

Change-Id: Iac466911b0dd3893e7e7a188e372272b14591b60
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127425
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 15:15:15 -07:00
Philip Elcan
23eaac0f33 gpu: nvgpu: mm: fix CERT-C INT30 violations in vm.c 
Rule INT30 requires checking that arithmetic operations on unsigned
numbers do no wrap. Use the "safe" ops to comply.

JIRA NVGPU-3517

Change-Id: I21c73d4327289e9b087c44c96b6aa7a3231f1066
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127424
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 15:15:05 -07:00
Divya Singhatwaria
8618135d6e gpu: nvgpu: Protect elpg_stat access 
- Protect the access of pmu->pg->elpg_stat using
  g->can_elpg protection
- Also, in pg public functions keep a check for 
  if lspmu and pg features are enabled.

JIRA NVGPU-3573

Change-Id: If4f25d4ab9df5e3e7257aaa9ed1e6d1fb9e431cf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128351
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 14:15:08 -07:00
Seema Khowala
a72bfa63b2 gpu: nvgpu: Add NVGPU_FEATURE_POWER_PG compiler flag 
This flag is added to compile out below features from
safety build
-elpg

JIRA NVGPU-3425

Change-Id: I439edb444a4ebe1732a379aecbb0ffc8b48eb97c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127449
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 12:05:49 -07:00
Abdul Salam
84a6d4e656 gpu: nvgpu: Add support for Vmax from get_status 
This patch does the following
1. Get the Vmax from get_status.
2. Compare the Vmax with voltage requested to pmu.
3. Make sure requested voltage is always less that Vmax.
4. Add maximum_voltage to expose this value via sysfs.

Bug 200454682

Change-Id: I1135f387d852a13ae435b4a665a7394ed5ed762f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129500
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 01:15:55 -07:00
Divya Singhatwaria
42f8b51411 gpu: nvgpu: Fix MISRA violations in BIOS unit 
- Fix Rule 16.1 and 16.6 violations:
  Every switch statement shall have at least two
  switch-clauses
- Fix Rule 15.6 violations:
  The body of an iteration statement shall be a
  compound statement.
- Fix Rule 17.7 violations:
  The return value of a non-void function shall
  be used.

JIRA NVGPU-3546

Change-Id: I475d185945f0998d4d359f4b9ded6e983474f01f
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127923
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-04 01:13:32 -07:00
Sagar Kamble
13a7ef2cc7 gpu: nvgpu: handle falcon copy pointer alignment for misra 11.3 deviation 
Function for copying to/form IMEM/DMEM cast pointer to char to
pointer to u32 since falcon data registers are read/written in
4-bytes. Firmware data is generally byte stream and hence we
won't be able to deal in pointer to u32. Hence we need deviate
from misra rule 11.3.
Firmware data is also not aligned at word boundary sometimes
hence we need to copy it byte by byte to conform to the dev-
iation recommendation.

Error: MISRA C-2012 Rule 11.3: ./hal/falcon/falcon_gk20a.c:296:
misra_violation: The object pointer expression "src" of type
"u8 *" is cast to type "u32 *".

JIRA NVGPU-3271

Change-Id: Ic081f97226dbbcf08402970829624933402066eb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 21:25:32 -07:00