Commit Graph

29 Commits

Author SHA1 Message Date
Rajesh Devaraj
befd4f7ac3 nvgpu: gpu: implements error reporting hooks for HOST
Implements hooks for reporting errors related to the following
sub-modules of HOST: PFIFO, PBUS and PBDMA.

JIRA NVGPU-1333
JIRA NVGPU-1368

Change-Id: I8e2388222d7fcd3ffe09e6c8f0c4c99efa0b2d21
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959183
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-11 11:44:51 -08:00
Sai Nikhil
303fc7496c gpu: nvgpu: common: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals or casting operands
to have same type of operands when an arithmetic operation is
performed.

This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: I27e3e59c3559c377b4bd3cbcfced90fdf90350f2
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921459
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-12-11 10:26:16 -08:00
Alex Waterman
c49e9e4bcd gpu: nvgpu: split the nvgpu_sgt unit from nvgpu_mem
Split the nvgpu_sgt code out from the nvgpu_mem code. Although the
two chunks of code are related the SGT code is distinct and as
such should be its own unit. To do this a new source file has been
added - nvgpu_sgt.c - which contains all the nvgpu_sgt common APIs.
These are the facade APIs to abstract the actual details of how any
given nvgpu_sgt is actually implemented.

An abstract unit - nvgpu_sgt_os - was also defined. This unit
exists solely for the nvgpu_sgt unit to call so that the OS
specific nvgpu_sgt_os_create_from_mem() API can be moved from the
common nvgpu_sgt unit. Note this also updates the name of what the
OS specific units are expected to call. Common code may still use
the generic nvgpu_sgt_create_from_mem() API.

JIRA NVGPU-1391

Change-Id: I37f5b2bbf9f84c0fb6bc296c3e04ea13518bd4d0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946012
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-11-29 03:15:17 -08:00
smadhavan
503b897b45 gpu: nvgpu: Fix MISRA rule 8.3 violations
MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.

JIRA NVGPU-847

Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-11-15 15:35:47 -08:00
Amulya
999eabbcd7 gpu: nvgpu: MISRA 10.1 boolean fixes
MISRA rule 10.1 doesn't allow the usage of non-boolean variables as
booleans.

Fix violations where a variable of type non-boolean is used as a
boolean and changed few instances of BIT() to BIT32() or BIT64().

JIRA NVGPU-646

Change-Id: I100606a69717c12839aa9c35e7bf6c18749db56e
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809836
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-11-09 13:27:04 -08:00
Amurthyreddy
1023c6af14 gpu: nvgpu: MISRA 14.4 boolean fixes
MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.

Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.

JIRA NVGPU-1022

Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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2018-11-07 10:35:22 -08:00
Amulya
3e6a445310 nvgpu: common: MISRA 10.1 boolean fixes
Fix violations where a variable of type non-boolean is used as a
boolean in gpu/nvgpu/common.

JIRA NVGPU-646

Change-Id: I64e96e02e9a3d5d5604c4fa52460e0415f484d75
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807128
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Amulya Murthyreddy <amurthyreddy@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-10-29 14:44:38 -07:00
smadhavan
757f028320 gpu: nvgpu: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations by renaming them
to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there
is no keyword repetition between file name and directory or
'NVGPU_HEADER-NAME' when there is repetition.

Deviate from the convention mentioned earlier in the case of clk.h.
There are two files with name clk.h. One under include/nvgpu directory
and other on in clk/ directory. Both of them will have header guards
with name NVGPU_CLK_H under the convention. Thus clk/clk.h will have
header guard with name NVGPU_CLK_CLK_H and include/nvgpu/clk will have
header guard with name NVGPU_INCLUDE_CLK_H

JIRA NVGPU-1028

Change-Id: I386d39649f39a98019a9e06bc65c8b623a43629b
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923539
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-10-29 03:57:01 -07:00
Amurthyreddy
89660dbd62 gpu: nvgpu: MISRA 14.4 bitwise operation as boolean
MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.

Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.

JIRA NVGPU-1020

Change-Id: If910150072c3dd67c31fe9819c3a9e738fd3c1c6
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2018-10-26 10:06:55 -07:00
Debarshi Dutta
6c8be7cfe2 gpu: nvgpu: move header location of gk20a.h
Change path corresponding to gk20a.h to <nvgpu/gk20a.h> corresponding
to files in the following directories.

gk20a/
vgpu/
gv100/
tu104/
common/bus/
common/fb/
common/ltc/
common/mc/
common/perf/

Jira NVGPU-597

Change-Id: I7b4f5e5ea3d13a4d1810c5db35fbc26fe5da443e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1846826
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2018-10-24 23:16:10 -07:00
Terje Bergstrom
3bda3a0678 Revert "Revert "gpu: nvgpu: add turing support""
This reverts commit 278842d6ff4e15467e0b8761c6e1b2a05f926f91.

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I37f47c137c048ddc3a728e143b6f30be525de120
Reviewed-on: https://git-master.nvidia.com/r/1918622
2018-10-12 17:35:09 +05:30
David Gilhooley
b74a4dbd26 Revert "gpu: nvgpu: add turing support"
This reverts commit 27686d8b56316c7ad772dd91548e91516d59f3b1.

Change-Id: Iebda705858edbd58c10ca3024a4ad060401485b6
Signed-off-by: David Gilhooley <dgilhooley@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918612
2018-10-12 17:35:09 +05:30
Deepak Nibade
51244d6112 gpu: nvgpu: add turing support
Add Turing specific common, unit, hardware header files

Make all the Makefile and Makefile.sources changes to compile
all Turing specific code

Bug 200454999

Change-Id: I62ebff5c078b4b8817fc83ea0e4ee3cfffe668dc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917983
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2018-10-12 17:35:09 +05:30
Debarshi Dutta
421e64aad7 gpu: nvgpu: move header location of gk20a.h
Update header path of gk20a.h in files present in common/
to <nvgpu/gk20a.h>

Jira NVGPU-597

Change-Id: I3431dae93ada9bd561454c89a0b99c5292ab4a8d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1832024
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2018-09-25 00:20:25 -07:00
Nicolas Benech
0e58ebaae1 gpu: nvgpu: Fix nvgpu_readl MISRA 17.7 violations
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_readl.

JIRA NVGPU-677

Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807528
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-09-06 21:33:41 -07:00
Srirangan
9e69e0cf97 gpu: nvgpu: common: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I599cce2af1d6cdc24efefba4ec42abfe998aec47
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795845
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2018-08-20 05:46:25 -07:00
Debarshi Dutta
db7bb6548b gpu: nvgpu: remove clk_arb.h to gk20a.h circular dependency
clk_arb.h and gk20a.h has circular dependencies to each other. This is
removed by forward declaring struct gk20a in clk_arb.h and removing the
header gk20a.h from clk_arb.h and similarly forward declaring struct
nvgpu_clk_arb in gk20a.h and removing the header clk_arb.h from gk20a.h
alongwith putting headers in every execution unit which calls clk_arb.h
related methods.

JIRA NVGPU-597

Change-Id: I7cedca17206c148b21d93e5d7f0d88c2f98b979a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790915
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2018-08-08 20:14:16 -07:00
Debarshi Dutta
82a90170d3 gk20a: nvgpu: Remove io.h dependency from gk20a.h
In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h

JIRA NVGPU-597

Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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2018-07-30 11:24:06 -07:00
Terje Bergstrom
16f131eb50 gpu: nvgpu: Cosmetic changes to bus
A few review comments got lost in the review of moving bus code to
common/bus. This takes care of renaming the header file protection
define, deletes the unnecessary description of the file in header,
and updates copyright years.

Change-Id: Ib7dfe3d8fdf31ff3ea1fbf96fc41f9e454486dd1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1741824
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2018-06-14 06:44:08 -07:00
Terje Bergstrom
dec8625b88 gpu: nvgpu: Move SW scratch register read to bus
SW scratch register is in bus register range. Move query of that
register to bus HAL from bios.

JIRA NVGPU-588

Change-Id: I69f35af3d5f8da3550eb68fe7d060a3ec48ce275
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730898
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
27694ca572 gpu: nvgpu: Implement bus HAL for bar2 bind
Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.

JIRA NVGPU-588

Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
5c8f1619ce gpu: nvgpu: Use gm20b version of BAR1 bind
All chips should use the waiting version of BAR1 bind since gm20b.
Change gp10b and gp106 to do that. BAR1 is not used in Volta.

JIRa NVGPU-588

Change-Id: Ib6957ebea4effa7c64f4d71522447fa6245728ed
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730895
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
d71d38087d gpu: nvgpu: Separate timer from bus
Code touching timer registers was combined with bus code. They're two
logically separate register spaces, so separate the code accordingly.

JIRA NVGPU-588

Change-Id: I40e2925ff156669f41ddc1f2e7714f92a2da367b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730893
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
5215d65c25 gpu: nvgpu: Remove setting of PRI timeout
PRI timeout should always use the HW initialization value. Do not set it
explicitly.

JIRA NVGPU-588

Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730892
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
f9a2f449a5 gpu: nvgpu: Remove direct MC and GR deps from bus
bus_gk20a.c had some debug dump references to MC and GR registers.
The dumps have not been very useful, so instead of refactoring the
code just remove the dumps.

JIRA NVGPU-588

Change-Id: Id974731716d058ef4a3fe77240c11b1c53db169c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
dbb8792baf gpu: nvgpu: Move setting of BAR0_WINDOW to bus
Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to
common code so that pramin_gk20a.[ch] can be deleted.

JIRA NVGPU-588

Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730890
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
ed65f1f26e gpu: nvgpu: Move setting priv interrupt to priv_ring
Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.

JIRA NVGPU-588

Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
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2018-06-14 06:44:07 -07:00
Terje Bergstrom
4eae06299b gpu: nvgpu: bus: Remove use of extra includes
bus_gk20a.c had a few unnecessary includes. Remove them to speed up
compilation.

JIRA NVGPU-588

Change-Id: I0e94e788104ba6acb259c315734e6b42f69a8074
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730888
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
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2018-06-14 06:44:06 -07:00
Terje Bergstrom
2dbf961365 gpu: nvgpu: Move bus HAL to common
Move implementation of bus HAL to common/bus.

Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1726337
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2018-05-25 10:15:40 -07:00