Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.
The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.
Jira NVGPU-1307
Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
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Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.
Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.
JIRA NVGPU-1008
Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
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gr_gk20a_update_hwpm_ctxsw_mode() right now validates the incoming
hwpm mode, checks if it is already set, and if not, it will go ahead
and set the new hwpm mode by calling g->ops.gr.ctxsw_prog HALs
Instead of programming hwpm mode in gr_gk20a.c, move the programming
to gr/ctx and gr/subctx units by adding below APIs
nvgpu_gr_ctx_prepare_hwpm_mode() - validate the incoming mode and
check if it is already set
nvgpu_gr_ctx_set_hwpm_mode() - set pm mode in graphics context
nvgpu_gr_subctx_set_hwpm_mode() - set pm mode in subcontext
Add gpu_va field to struct pm_ctx_desc to store the gpu_va to be
programmed into context
Rename NVGPU_DBG_HWPM_CTXSW_MODE_* to NVGPU_GR_CTX_HWPM_CTXSW_MODE_*
and move them to gr/ctx.h
Remove below HALs since they are no longer used
g->ops.gr.ctxsw_prog.set_pm_mode_no_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_stream_out_ctxsw()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: Id2a4d498182ec0e3586dc7265f73a25870ca2ef7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011093
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Add new unit gr/config to initialize GR configuration like GPC/TPC
count, MAX count and mask
Create new structure nvgpu_gr_config that stores all the configuration
and that is owned by the new unit
Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h
Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;
u32 pe_count_per_gpc;
u32 *gpc_tpc_count;
u32 *gpc_ppc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
Remove gr->sys_count since it was already no longer used
common/gr/config/gr_config.c unit now exposes the APIs to initialize
the configuration and also to query the configuration values
nvgpu_gr_config_init() is called to initialize GR configuration from
gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply
renamed as nvgpu_gr_config_init_map_tiles()
Expose new API nvgpu_gr_config_deinit() to deinit the configuration
Expose nvgpu_gr_config_get_*() APIs to query above configuration
fields stored in nvgpu_gr_config structure
Update vgpu_gr_init_gr_config() to initialize the configuration
from gr->config structure
Chip specific HALs that access GR register for initialization
are implemented in common/gr/config/gr_config_gm20b.c
Set these HALs for all GPUs
Jira NVGPU-1879
Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012167
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.
JIRA NVGPU-677
Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
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It is possible to have an invalid combination of the ioctl calls that
could result in a null pointer access in the function
gk20a_event_id_release(). The null pointer access can be prevented by
having a null check for a valid struct gk20a_event_id_data before
accessing its internal variables.
Bug 200462170
Change-Id: I9233479081b7a7659deeaa3b84141381ed302e63
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006314
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The function parameter of nvgpu_vm_map function is fixed for MISRA
where implicit assignment of objects to a narrower or different
essential type not allowed.This fixes few enum violations.
JIRA NVGPU-1584
Change-Id: I2353f7501c3326f792f5942b2e247badf03349cf
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1986509
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Add error prints for DMA alloc failures. This way when there is a
DMA alloc failure the failure is clear. Without this it's hard to
know what exactly is causing any given -ENOMEM issue or what the
specifics of said ENOMEM case are.
Change-Id: Ia535895ae07bc1704edaed564edbb6f6dfbf6518
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1976441
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Instead of using kmalloc() to get a buffer for storing the
computed flags string during DMA debugging use a stack
buffer. This removes the need for a kmalloc() call. The
problem with kmalloc() is that if a dma_alloc() fails due
to being out of memory the kmalloc may likely fail, too!
Also simplify the logic now that there's no need to do
any error checking for a kmalloc() call.
Change-Id: I45c1fd16658212188a1206a2edf17b28f3c06c9e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1976440
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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gv11b_mm_l2_flush was not checking error codes from the various
functions it was calling. MISRA Rule-17.7 requires the return value
of all functions to be used. This patch now checks return values and
propagates the error upstream.
JIRA NVGPU-677
Change-Id: I9005c6d3a406f9665d318014d21a1da34f87ca30
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998809
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Make a physical nvgpu_mem implementation in the common code. This
implementation assumes a single, contiguous, physical range. GMMU
mappability is provided by building a one entry SGT.
Since this is now "common" code the original Linux code has been
moved to commom/mm/nvgpu_mem.c.
Also fix the '__' prefix in the nvgpu_mem function. This is not
necessary as this function, although somewhat tricky, is expected
to be used by arbitrary users within the nvgpu driver.
JIRA NVGPU-1029
Bug 2441531
Change-Id: I42313e5c664df3cd94933cc63ff0528326628683
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995866
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Move the code involved in nvlink register initialization into a
separate unit called "nvlink_device_reginit".
Nvlink device_reginit will be an unit under component nvlink_init.
TLC buffer credit initialization is done by this unit.
JIRA NVGPU-1784
Change-Id: I9dd4238d0288b33867eb8a8993e56287a67a907f
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994665
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The commit 3fdd8e38b2 ("gpu: nvgpu: Use our own vmap() for
coherent DMA buffers") added an NVGPU_DMA_NO_KERNEL_MAPPING
flag for coherent chips to work around a memory mapping bug
suspiciously from DMA API.
However, this requires dma-mapping code of ARM64 to support
a legacy DMA_NO_KERNEL_MAPPING attribute for DMA allocation,
which will not likely get upstreamed -- it is not long-term
sustainable. So the plan is to remove this flag from ARM64
part.
The results of 3D benchmarks and GVS sanity tests show that
the system has no regressions in stability, and no mapping
issue being observed after removing this WAR. In case that
GPU code encounters mapping issue in the future, we should
fix from the general DMA API side instead.
Bug 2424160
Change-Id: Ice91f2b2c924beb2f83762cb02efbd53fe7df1c0
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001294
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move the code involved in nvlink probe sequence into a separate
unit called "nvlink_probe"
nvlink probe code is spread over both the common and OS specific
nvlink files.
Nvlink Probe unit would encompass code needed to initialize the
nvlink software state. Nvlink software initialization involves:
1. Allocate memory for nvlink_device and nvlink_link structs
2. Read the device tree pci node to know about nvlink topology
3. Initialize nvlink function pointers needed by Tegra nvlink
core-driver
4. Register nvlink_device and nvlink_link with the core-driver.
nvlink probe returns -ENODEV when nvlink is not supported.
Nvlink is not supported in two cases:
1. There is no nvlink IP on the Tegra SoC which is denoted by
CONFIG_TEGRA_NVLINK or
2. The pci device tree node does not have "nvidia,nvlink" child
node needed to describe nvlink topology.
Any negative return value other than -ENODEV denotes failure in
execution of nvlink probe.
JIRA NVGPU-1783
Change-Id: I50011b25d88d8cc01569caac7895abe32ee38215
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994619
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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sync cmbbuf specific ops pointers are moved into a new struct sync_ops
under the parent struct gpu_ops. The HAL assignments to the gk20a and
gv11b versions are updated to match the new struct type.
Jira NVGPU-1308
Change-Id: I1d9832ed5e938cb65747f0f6d34088552f75e2bc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975919
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Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS to debugger node, to
install/uninstall a buffer for cycle stats.
Add NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT to debugger
node, to attach/flush/detach a buffer for Mode-E streamout.
Those ioctls will apply to the first channel in the debug session.
Bug 200464613
Jira NVGPU-1442
Change-Id: I0b96d9a07c016690140292fa5886fda545697ee6
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2002060
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Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c
Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h
Move rest of the platform HAL files to common/regops/ as well
Fix all the header includes to include new public header
Remove *_apply_smpc_war() declarations from headers. Corresponding
functions were cleaned up already, and declarations were left somehow
Jira NVGPU-620
Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998723
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Replace nvgpu locks to vanilla Linux locks. For the custom kernel
driver when they include nv-p2p.h, nvgpu/linux/lock.h will not be
available because nvgpu/linux/lock.h is not copied to
/usr/src/kernel_header_file.
Bug 200438879
Change-Id: I55b52c6f791970650388b7d51c4d30b5fe75bbb8
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997950
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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gk20a_remove_gr_support() is freeing the local_golden_image and
local_golden_image->context. But there are instances where
local_golden_image is not allocated since freeing an
unallocated golden context image accesses the contents of
local_golden_image causes a fault.
Check golden_image_initialized flag before freeing
local_golden_image->context.
Jira NVGPU-1648
Bug 2461665
Change-Id: I19235d2ec9d77ba4ef00257f43436448f5f70b25
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997665
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The Tegra SOC nvlink driver and dGPU nvlink driver depend on
struct definitions, macros and functions exposed by nvlink-core
driver. The nvlink-core driver is not part of the nvgpu driver,
hence we should not be directly accessing any core driver
APIs/macros/structs from the /common/nvlink code. Common code can
only use nvgpu internal APIs. We wrap all calls from common/nvlink.c
to other drivers in nvgpu wrappers, and define the implementation of
wrappers in os/linux and os/nvgpu_rmos, and stub them in os/posix.
Also, we remove the implicit inclusion of OS specific nvlink header
file via common nvgpu/nvlink.h. So the OS specific code needs to
explicitly add OS specific header file.
JIRA NVGPU-966
Change-Id: I65c67e247ee74088bb1253f6ae4c8d0c49420a98
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990071
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
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While not necessary for MISRA compliance purposes, this change
modifies the linux platform clk code use of container_of() to follow
similar changes applied to address the following rule violations:
* Rule 11.3 : A cast shall not be performed between a pointer to
object type and a pointer to a different object type.
* Rule 11.8 : A cast shall not remove any const or volatile
qualification from the type pointed to be a pointer.
* Rule 20.7 : Expressions resulting from the expansion of macro
parameters shall be enclosed in parentheses.
This patch replaces the to_clk_gk20a() macro with a new (static)
clk_gk20a_from_hw() function that eliminates the Rule 11.8 and
Rule 20.7 violations and exchanges the Rule 11.3 violation with
an advisory Rule 11.4 violation.
It should be noted that the replacement function still contains
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations where appropriate.
JIRA NVGPU-782
Change-Id: Ia702cca1e3fc1a57771d0d6db2fd3b4788ac49b8
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995893
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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Regops does not depend on debug session logically
We right now include debugger.h in regops_gk20a.c to extract
channel pointer from debug session and to check if session is for
profiling or not
Update exec_regops_gk20a() to receive channel pointer and profiler
flag directly as parameters, and remove dbg_session_gk20a from
parameter list
Remove ((!dbg_s->is_profiler) && (ch != NULL)) checks from
check_whitelists(). Caller of exec_regops_gk20a() already ensures
that we have context bound for debug session
Use only is_profiler boolean flag in this case which should be
sufficient
Remove (ch == NULL) check in check_whitelists() if regops is of
type gr_ctx. Instead move this check to earlier function call
in validate_reg_ops(). If we have non-zero context operation on
a profiler session, return error from validate_reg_ops()
Update all subsequent calls with appropriate parameter list
Remove debugger.h include from regops_gk20a.c
Jira NVGPU-620
Change-Id: If857c21da1a43a2230c1f7ef2cc2ad6640ff48d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997868
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Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).
To not lose this documentation a comment was added to convey that this
function must be used with care.
JIRA NVGPU-1029
Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
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Add new unit common/gr/ctx.c to manage GR context
This unit provides interfaces to allocate/free/map/unmap GR context,
patch context, pm context, ctxsw {preempt/spill/betacb/pagepool/rtvcb}
buffers.
It also provides APIs to set size of above buffers
Add new header file include/nvgpu/gr/ctx.h to declare all the interfaces.
Move nvgpu_gr_ctx, patch_desc, pm_ctx_desc, zcull_ctx_desc structures
to this unit
Add new structure nvgpu_gr_ctx_desc to hold context description
parameters. For now we add sizes of all the buffers here.
Add this structure to gr_gk20a for global reference
Remove gr_gp10b_alloc_buffer() since it is no longer used
Rename g->ops.gr.alloc_gfxp_rtv_cb() to g->ops.gr.init_gfxp_rtv_cb()
since this HAL now only sets the size of rtvcb ctxsw buffer
Remove gr->ctx_vars.buffer_size and gr->ctx_vars.buffer_total_size
since they were redundant. We already have gr->ctx_vars.golden_image_size
to denote golden image size
Jira NVGPU-1527
Change-Id: I8847b347f80235209dd5e28d979e79984ab85408
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987702
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