Commit Graph

5570 Commits

Author SHA1 Message Date
Deepak Nibade
58bc18b794 gpu: nvgpu: load context image from gr/ctx unit
We currently load and create new graphics context image in
gr_gk20a_load_golden_ctx_image()
This API will first load local golden image in new context
image and then initialize context appropriately by calling
g->ops.gr.ctxsw_prog() HALs

Move this sequence to gr/ctx unit and rename the API as
nvgpu_gr_ctx_load_golden_ctx_image()

Note that call to g->ops.gr.update_ctxsw_preemption_mode()
is moved out of this API and called directly from
gk20a_alloc_obj_ctx()

Jira NVGPU-1527

Change-Id: Id5a5b2cd2c0704fbefe536d581a37a60ec185ea9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989157
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-17 10:26:50 -08:00
rmylavarapu
f048bb5a71 gpu: nvgpu: Reading Vmin and Volt_rail get status
Changes:
1) volt_rail_boardobj_grp_get_status function implemented.
2) nvgpu_volt_get_vmin_tu10x function implemented.
3) Only Vmin is updated into boardobjs.

Bug 200454682
Bug 2481917

Change-Id: Ie070b28a78503eeb3003493b5f130a4dcd9b1275
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1996137
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-17 09:15:22 -08:00
Abdul Salam
c57cf00aa0 gpu: nvgpu: Add quantization to slave VF Points
All slave clock should be quantized as per step size.
TU104 has 15Mhz as step size.
Enable clk_arb without enabling clk_freq_controller.
clk_freq_controller is not needed for Auto use case.
Increase the maxclk only when master is less that slave clock.
This is needed when gpcclk is less than slave P0 min.
Use get_status to get Vim and use it for change sequencer.
Add support for Device Events

Bug 200454682
Bug 2481917

Change-Id: Ie0c404f4b77e41f6a1719b52d6e29a5ac757b41b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-01-17 09:15:19 -08:00
Mahantesh Kumbar
33e9d08610 gpu: nvgpu: Modify dgpu WPR/NON-WPR address space
Currently, there is free space of 3MB with current implementation due to
gap between WPR & NON-WPR offset, with this PMU buffers are allocated
between this space & some are after WPR.

So, modified WPR to allocate at 0th offset of bootstrap-region of VIDMEM
& NON-WPR to be at WPR+WPR_SIZE offset of bootstrap-region to make
contiguous free space available till end of bootstrap-region of VIDMEM.

Increased WPR/NON-WPR size from 1MB to 2MB as LS falcon managed
count increased to 4 for Turing & remains 2MB for previous chips too.

Bug 200476497

Change-Id: I92ca5bc9a571330d75a66ce820a1c82442c1f200
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994653
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-01-16 23:24:47 -08:00
Alex Waterman
dd4c60aeb5 gpu: nvgpu: rfr: Add address book
Add an address book that lets devs use short hand for specifying
--to and --cc targets. For example, if a dev wants to CC the MISRA
list this can be used:

  $ ./scripts/rfr -e --cc misra ...

The address book also lets devs add their own names/email addresses
since this makes it convenient to CC individual people. For example:

  $ ./scripts/rfr -e --cc alex ...

Several new arguments were added to support the address book. There
are arguments to list/search the address book, ignore the address
book, and to prevent nvgpu-core from being added to the to address
by default. For more details see the help page.

To use an address book there's several options: place one at

  ~/.rfr-addrbook

Export an RFR_ADDRBOOK environment variable pointing to the address
book, or specify one with the `-a' option. The address book contents
is simple. All empty lines and lines beginning with '#' are ignored.
The remaining lines are split by '|' and the first half of the line
is considered a nickname and the latter half the address. An example:

  alex | alex waterman <alexw@nvidia.com>

This will let you specify `--to alex' instead of the full email
address. This is especially useful for mailing lists.

Lastly there is more documentation located at:

  https://confluence.nvidia.com/display/TGS/NVGPU+Request+For+Review

[Bump version to 1.1.0]

Change-Id: Iac7ec05ae28d7e888d2bf36bd23574ec49eb04dc
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983695
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
2019-01-16 15:38:18 -08:00
Deepak Nibade
164e387940 gpu: nvgpu: fix dereference after NULL check
Fix dereference of pointer after NULL check in
gr_gv11b_handle_warp_esr_error_mmu_nack() by adding appropriate
NULL check

Coverity defect ID : 6270399

Change-Id: Ic111f9a89207133530d775463d605810f248c6b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1996271
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2019-01-16 15:38:17 -08:00
Alex Waterman
67138e0376 gpu: nvgpu: rfr: Add support for CCs
Add support for CCs instead of only direct To addresses. This
lets us have more fine grained control over the to/cc addresses.

[Bump minor revision to 1.0.3]

Change-Id: Ie2864ddde02a71a4502bf2b3d0d80064810da0ef
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983663
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
2019-01-16 15:38:14 -08:00
Alex Waterman
e2aa359774 gpu: nvgpu: rfr: Notify user of email destination
When sending emails it can be nice to see who you are sending an
email to if you specify multiple '--to' options.

Also update the get_user_message() function to remove comment lines
starting with '#'. This lets the script place information useful
to a developer in the message that won't ultimately make it to the
final email.

[Bump minor revision to 1.0.2]

Change-Id: I3657a787d8e9a8c19de727e050a0b9a18a6d43e0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983642
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
2019-01-16 15:38:11 -08:00
Scott Long
dce49c9b2b gpu: nvgpu: container_of() changes to sema code
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object type.
 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.
 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace the references to
container_of() in common semaphore code:

 * nvgpu_semaphore_pool_from_ref
 * nvgpu_semaphore_from_ref

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: I79c0b6fc4fa819c92985f2e2239e9d1d7137618d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995937
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-16 15:37:57 -08:00
Philip Elcan
96d3f396d0 gpu: nvgpu: gv11b: fix misc MISRA 10.3 violations
MISRA Rule 10.3 prohibits implicit assignment of an object of different
essential type or narrower type. This change addresses a number of
miscellaneous violations in gr_gv11b.c.

JIRA NVGPU-1008

Change-Id: I92f5fb38be6c09a7b363646028460a24763f2810
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994967
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2019-01-16 15:37:53 -08:00
Philip Elcan
dc20c0733a gpu: nvgpu: gv11b: fix MISRA 10.3 bool violations
MISRA Rule 10.3 prohibits implicit assignment of an object of different
essential type or narrower type.

This change fixes a number of MISRA 10.3 violations with booleans in
gr_gv11b.c.

JIRA NVGPU-1008

Change-Id: Ia4821930d14b06ae6bc10d0b02f57d0aef22f358
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994966
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2019-01-16 15:37:44 -08:00
Konsta Holtta
bca54edb08 gpu: nvgpu: unit: use array for a lone tsg
test_tsg_format_gen() uses a single tsg and passes its address on to be
used as an array (of a single element). Reduce confusion by using a
single-element tsg array already instead of a plain tsg.

Coverity ID 8335811

Change-Id: I0135bcabeed12474beb9c52c9d186de1676b5423
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1996287
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2019-01-16 09:55:07 -08:00
Vinod G
fe765fc464 gpu: nvgpu: fix unintentional integer overflow issue
Reported issue, potentially overflowing expression with type u32
is evaluated using 32bit arithmetic and then used in a context that
expects an expression of type 64.

Type cast the 32 bit to 64bit variable before applying the
arithmetic left shift.

Fix Coverity ID 8387800

Change-Id: I7a988eedf91f82b21b8bc6c35606d80cfb2d083b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995835
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2019-01-16 09:55:04 -08:00
Vinod G
c0a2f356c4 gpu: nvgpu: pmu code fix for VDK
dgpu vdk does not have pmu support. pmu variables do not get
initialized in fmodel.

Add is_pmu_supported check before nvgpu_pmu_mutex_acquire call.

JIRA NVGPU-1564

Change-Id: Ieb683d3092b5289a9959c8811c25782074d19804
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992193
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-01-15 23:04:42 -08:00
Terje Bergstrom
fc503da086 gpu: nvgpu: Add rest of common files to POSIX build
Add common files to POSIX build, and enable most of the common feature
flags nvgpu has enabled in other builds.

As consequence common code now uses more APIs that need to be stubbed
in POSIX build, so add stubs posix-dt.c, posix-nvhost.c, posix-vgpu.c,
and posix-vidmem.c.

JIRA NVGPU-1734

Change-Id: I936c5886229cb4d47cab4f42b013ff77f9e45482
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993127
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-15 17:15:24 -08:00
Terje Bergstrom
59cada205d gpu: nvgpu: Add real clk_arb.c to POSIX build
Add common clk_arb.c to the POSIX build. Remove the stub POSIX clk_arb.c
and instead implement only the OS specific interfaces needed by common
clk_arb.c.

JIRA NVGPU-1734

Change-Id: I846cbffecb519f182af7261c1699cbd03bc922f5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993126
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2019-01-15 17:15:20 -08:00
Terje Bergstrom
13125a57ca gpu: nvgpu: Add POSIX __nvgpu_mem_create_from_phys
Add a stub POSIX version of __nvgpu_mem_create_from_phys. That allows
building nvgpu code that is behind NVHOST compilation option.

JIRA NVGPU-1734

Change-Id: I12d80e69e78d975141d690bc3f37220ecb5bcc89
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993125
Reviewed-by: Automatic_Commit_Validation_User
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2019-01-15 17:15:17 -08:00
Terje Bergstrom
e6f790c7a8 gpu: nvgpu: Make hw_sim.h definitions unsigned
Add U postfixes to all integers in hw_sim.h to make them unsigned.

JIRA NVGPU-1734

Change-Id: Ia162db271f23ddafe444576e1bd6a33dddb794e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993124
GVS: Gerrit_Virtual_Submit
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2019-01-15 17:15:13 -08:00
Terje Bergstrom
b8358c06d6 gpu: nvgpu: Add missing log.h include
Add missing include <nvgpu/log.h> to vgpu_gr_gp10b.c. It has relied
on that file getting included implicitly.

JIRA NVGPU-1734

Change-Id: Ie07ed43aeeef8ff20e9e4aaf2b1712e17fc8d4f7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992460
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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2019-01-15 17:15:09 -08:00
Terje Bergstrom
3f39ac89b7 gpu: nvgpu: Remove unused vgpu_fifo_gp10b.c file
vgpu_fifo_gp10b.c file is not used anywhere. Delete it.

JIRA NVGPU-1734

Change-Id: Id5c3dc03a226eca7ae44f655e1255d7f0f9753f6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992459
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2019-01-15 17:15:06 -08:00
Terje Bergstrom
adb562f58e gpu: nvgpu: Add ERESTARTSYS and SZ_512 to POSIX
Vidmem common implementation requires ERESTARTSYS and SZ_512. Define
them for POSIX.

JIRA NVGPU-1734

Change-Id: If8d656b56f27516c5f988bc1d4b4251b0e0eab57
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992458
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2019-01-15 17:15:02 -08:00
Terje Bergstrom
8c76c98063 gpu: nvgpu: Def sim_readl() and sim_writel() for POSIX
Allow POSIX build by defining stubs for sim_readl() and sim_writel().
Add their declarations in include/nvgpu/sim.h to replace the build
specific ones.

JIRA NVGPU-1734

Change-Id: Ie51393e7e3bc54f3eadb01e8df15dd96343aa14a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992457
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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2019-01-15 17:14:59 -08:00
Terje Bergstrom
2683ce089a gpu: nvgpu: Use Hw vals instead of CPU page size in sim
Simulation used PAGE_SHIFT for values that are actually dependent on the
fmodel implementation and not CPU page size. Fix that by introducing new
HW constants.

JIRA NVGPU-1734

Change-Id: Icaab8293ac9f6eeaae5d5424d55851cb53b365dd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992456
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-01-15 17:14:55 -08:00
Terje Bergstrom
503fe52304 gpu: nvgpu: Add stub for channel reset trace
Add a stub function for channel reset trace event. Missing the stub
prevents build without Linux ftrace.

JIRA NVGPU-1734

Change-Id: Iaa04c9f4715918658d68257056f1969440ff9ca9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1992455
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2019-01-15 17:14:51 -08:00
Seema Khowala
c2524323eb gpu: nvgpu: fix error_type_index decoding
Priv errors are in the form of 0xBADF-TYPE[3:0]-TYPEINDEX[3:0]-YY
To get error TYPEINDEX, shift by 8 instead of 16 as shifting by
16 will result 0.

Fix Coverity ID 9748860

Change-Id: I2eee5c0cdd87d318a2ef670b6329de984158ed1e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995783
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-01-15 16:04:15 -08:00
Scott Long
6b4a762528 gpu: nvgpu: container_of() changes to nvgpu init
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object type.
 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.
 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace the reference to
container_of() in nvgpu init code:

 * gk20a_from_refcount

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: I70698c01906872e6bba368b00f5926c4419671d0
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995743
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2019-01-15 14:04:03 -08:00
Scott Long
6b66428a34 gpu: nvgpu: container_of() changes to ch sync code
The container_of() macro used in nvgpu produces the following set
of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object to type.

 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.

 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() in common channel sync code:

 * nvgpu_channel_sync_semaphore_from_ops
 * nvgpu_channel_sync_syncpt_from_ops

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: Ib4279c7d28824ce5888838580a54b573323f7152
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993787
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-15 14:03:50 -08:00
Alex Waterman
11e9e8fa49 gpu: nvgpu: Fix white space in enabled.h
Clean up the tabbing to make all enabled flags have similar tab
offsets.

JIRA NVGPU-1737
JIRA NVGPU-1029

Change-Id: Ib647b0d1a0f2d9d8e0096de7dcbc6db1e2d45c10
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989499
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-15 12:54:27 -08:00
Alex Waterman
489236d181 gpu: nvgpu: MISRA 21.2 fixes: __nvgpu_set_enabled()
Rename __nvgpu_set_enabled() to nvgpu_set_enabled(). The original
double underscore was present to indicate that this function is a
function with potentially unintended side effects (enabling a feature
has wide ranging impact).

To not lose this documentation a comment was added to convey that this
function must be used with care.

JIRA NVGPU-1029

Change-Id: I8bfc6fa4c17743f9f8056cb6a7a0f66229ca2583
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989434
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-15 12:54:19 -08:00
Alex Waterman
4ce9c114d5 gpu: nvgpu: Fix secure buffer size for 64K PAGES
Increment secure buffer size by 64K when page size is 64K.
This fixes the secure buffer allocation issue as otherwise the buffer
runs out of space.

Bug 2441531

Change-Id: I16741341bcaca2fee093adef4c461a42124cd928
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943609
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
Tested-by: Rohit Khanna <rokhanna@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-15 10:43:29 -08:00
Deepak Nibade
720402ba74 gpu: nvgpu: remove unused gr_gv11b_alloc_buffer() API
gr_gv11b_alloc_buffer() is not being called from anywhere, hence
remove it

Jira NVGPU-1527

Change-Id: Ib52ac9cd2f8d37c775f8d34453893308bebf1181
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995566
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-15 08:34:31 -08:00
Alex Waterman
5b5608f221 gpu: nvgpu: Delete unused source file mclk_gp106.c
Also delete the corresponding header file and all references to
said header file (mclk_gp106.h).

JIRA NVGPU-1737

Change-Id: I2376f03f7393784af72b20a789bf9cfda4871725
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995064
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-15 00:04:18 -08:00
Sagar Kamble
9b114d628c gpu: nvgpu: check bl_size with imem size in bl_bootstrap
Currently nvgpu gets the destination offset in imem by directly subtra-
cting bl_size from imem size however there can be underflow if bl_size
is larger than imem size. Add check for that.

JIRA NVGPU-1732

Change-Id: I88477beee273201fc6075c7ab8d77eb9b2a17ca5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989989
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 21:44:17 -08:00
Sagar Kamble
32280be158 gpu: nvgpu: update timed falcon state checks
falcon wait_idle, mem_scrub_wait, wait_for_halt, clear_halt_intr_status
routines have similar structure of returning -EINVAL on invalid falcon
parameter, invoking flcn_ops and returning -ETIMEDOUT on failure to
satisfy the condition. Fix the deviations.

JIRA NVGPU-1732

Change-Id: I95c907aacf02431604fa1502c688b376fa27ebbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989988
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-14 21:44:14 -08:00
Sagar Kamble
20b6744384 gpu: nvgpu: fix null falcon access
Unit tests helped identify invalid accesses of falcon before validating
in nvgpu_falcon_wait_idle and nvgpu_falcon_clear_halt_intr_status. Fix
them.

JIRA NVGPU-1732

Change-Id: I14874fb91556ad47d032bd96a81c73d5bc5771cb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989987
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 21:44:10 -08:00
Sagar Kamble
ed8d3b5d8c gpu: nvgpu: fix ops access for dmem & emem accessors
Similar to imem, update dmem & emem copy_from and copy_to functions to
warn and handle cases where ops are not available.

JIRA NVGPU-1732

Change-Id: If5cebffe68d16933c2abe1cb7e5421877149d823
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989986
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 21:44:06 -08:00
Scott Long
0837b6988c gpu: nvgpu: container_of() changes to clk arb code
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object type.
 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.
 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses.

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() references in clk arb code:

 * nvgpu_clk_dev_from_refcount
 * nvgpu_clk_session_from_refcount

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: I612990e9c27f10d0ce3ac76729529aa1eb15d42a
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993796
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 20:34:26 -08:00
asah
35ea60fe80 gpu: nvgpu: unit: extend unit test build system
Added NV_COMPONENT_INCLUDES and
NV_COMPONENT_NEEDED_INTERFACE_DIRS support as we need
them for building QNX nvgpu_rmos/ files with the test
library

JIRA NVGPU-1352

Change-Id: If1944396dac2ac84fadd5cbb487fa700c829523a
Signed-off-by: asah <asah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1994355
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 19:23:52 -08:00
Nicolas Benech
7e503d619d gpu: nvgpu: unit: add req testing for page_table
Add requirement-based testing for the page_table unit.

JIRA NVGPU-907

Change-Id: Ia81a2c92025e6a3c05536f26690338a3873ba5de
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990503
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 15:56:00 -08:00
Philip Elcan
3d62c3256f gpu: nvgpu: gk20a: fix misc MISRA 10.3 issues
MISRA Rule 10.3 prohibits assigning to an object of different essential
or narrower type. This fixes some miscellaneous violations in
gr_gk20a.c.

JIRA NVGPU-1008

Change-Id: I46aa3bcdee23f53ab79615d37c1a797de1b74137
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990390
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 13:45:08 -08:00
Philip Elcan
a6f9d1c40e gpu: nvgpu: gk20a: add casts for MISRA 10.3
MISRA Rule 10.3 prohibits assignment to an object from an object of
different essential type or a narrower type. This adds casts in
gr_gk20a.c to address these violations. BUG_ON() is added for cases
where there is potential for losing data in the cast.

JIRA NVGPU-1008

Change-Id: Ic4e2449c536abe8127272d4ca46f76336fae46c8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990389
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 13:45:05 -08:00
Philip Elcan
60ef4d2e3b gpu: nvgpu: gk20a: fix MISRA 10.3 violations
MISRA 10.3 prohibits assignment from an object of different essential or
narrower type. This fixes a number of MISRA 10.3 violations in
gr_gk20a.c in constant values.

JIRA NVGPU-1008

Change-Id: I93eeabe4ab0217a8043a2a025a42d5b95e177bc3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990388
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 13:45:01 -08:00
Philip Elcan
edd5a73bbf gpu: nvgpu: gk20a: fix function returns
This fixes MISRA 10.3 violation for assignment of narrower or different
type. The fixes are cases where functions were mixing u32s and ints
for function return values.

JIRA NVGPU-1008

Change-Id: I58c7e499c918ece0abb4012da9fe6b7a604b0419
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990386
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 13:44:57 -08:00
Philip Elcan
1b2dd4904a gpu: nvgpu: gk20a: cleanup function return
gk20a_init_gr_prepare does not return any meaningful status, so just
make it a void.

JIRA NVGPU-1008

Change-Id: I25f528407e123e84e6bc5450dbd8ee38e75ad3fd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990385
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-14 13:44:54 -08:00
Philip Elcan
f910525e14 gpu: nvgpu: cleanup idle_wait and wait_empty APIs
All cases where the wait_empty HAL API and the wait_idle, wait_fe_idle
APIs were being called used the same parameters, so move those
parameters inside the APIs.

JIRA NVGPU-1008

Change-Id: Ib864260f5a4c6458d81b7d2326076c0bd9c4b5af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 13:44:50 -08:00
Scott Long
4ba92354c0 gpu: nvgpu: container_of() changes to tsg/fence code
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

* Rule 11.3 : A cast shall not be performed between a pointer to
              object type and a pointer to a different object type.

* Rule 11.8 : A cast shall not remove any const or volatile
              qualification from the type pointed to be a pointer.

* Rule 20.7 : Expressions resulting from the expansion of macro
              parameters shall be enclosed in parentheses

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() references in tsg and fence code:

 * tsg_gk20a_from_ref
 * gk20a_fence_from_ref

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: Ib5f3b8c7b18b92af8237e82ef5ee42d39c0381e5
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993503
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-14 12:42:54 -08:00
Scott Long
69e5b2a38c gpu: nvgpu: container_of() changes to mm code
The container_of() macro used in nvgpu produces the following
set of MISRA required rule violations:

 * Rule 11.3 : A cast shall not be performed between a pointer to
               object type and a pointer to a different object type.

 * Rule 11.8 : A cast shall not remove any const or volatile
               qualification from the type pointed to be a pointer.

 * Rule 20.7 : Expressions resulting from the expansion of macro
               parameters shall be enclosed in parentheses

Using the same modified implementation of container_of() as that
used in the nvgpu_list_node/nvgpu_rbtree_node routines eliminates
the Rule 11.8 and Rule 20.7 violations and exchanges the Rule 11.3
violation with an advisory Rule 11.4 violation.

This patch uses that same equivalent implementation in two new
(static) functions that are used to replace references to
container_of() references in vm.c:

 * nvgpu_mapped_buf_from_ref
 * vm_gk20a_from_ref

The implementation of the following routine has also been updated
using the same approach to eliminate the direct reference to
container_of():

* gk20a_from_as

It should be noted that replacement functions still contain
potentially dangerous (and non-MISRA compliant code) and that it is
expected that deviation requests will be filed for the new advisory
rule violations accordingly.

JIRA NVGPU-782

Change-Id: I530f8d0cbe37445535b82578953eb5193ccf682c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989570
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-11 16:15:03 -08:00
Vinod G
e492834a07 gpu: nvgpu: dGpu VDK support
Skip the simulation register check in real silicon.

Check sim_config_simulation register for fmodel identification.

JIRA NVGPU-1564

Change-Id: Ic65d816f35e93855db31555e7e943361fca4e9d0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970733
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-11 16:15:00 -08:00
Rajesh Devaraj
befd4f7ac3 nvgpu: gpu: implements error reporting hooks for HOST
Implements hooks for reporting errors related to the following
sub-modules of HOST: PFIFO, PBUS and PBDMA.

JIRA NVGPU-1333
JIRA NVGPU-1368

Change-Id: I8e2388222d7fcd3ffe09e6c8f0c4c99efa0b2d21
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959183
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-11 11:44:51 -08:00
Peter Daifuku
31540f6620 gpu: nvgpu: allocate ctxsw buffers once only
In nvgpu_gr_ctx_alloc_ctxsw_buffers, just return if
ctxsw buffers have already been allocated.

Bug 200418468

Change-Id: I0fe0b0d851c2b304243f9fca2c19832806ba40f4
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1991656
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-11 09:25:22 -08:00