Add common/falcon/falcon_priv.h file that will contain declarations
private to Falcon unit. Clean up the falcon header files inclusion.
Rules followed:
1. Remove unneeded header file includes.
2. Falcon unit source files will only include falcon_priv.h.
3. Base architecture Falcon source (falcon_gk20a.c) will only
include hw_falcon_*.h file.
4. Derived architecture source will include hw headers if needed.
5. Other units should not include hw headers for Falcon.
6. HAL source will include the Falcon unit header if needed.
JIRA NVGPU-1459
Change-Id: Ia9f03f7b577fe10b8c0f417e6302fa7ebd4131cc
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961634
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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pmu.g & sec2.g were set in nvgpu_falcon_sw_init. They are now set
in nvgpu_early_init_pmu_sw & nvgpu_init_sec2_setup_sw. Pass gk20a
& pmu struct to nvgpu_init_pmu_fw_support like sec2.
pmu_fw_support & sec2_setup_sw are separated from respective init
sequence and now are called earlier since we need ->g member earlier
and most of the setup is sw only.
nvgpu_init_pmu_fw_ver_ops is now being exported.
JIRA NVGPU-1594
Change-Id: I6c71c6730ce06dad190159269e2cc60301f0237b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968241
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Add new unit common/gr/global_ctx.c to manage GR global context buffers
This unit provides interfaces to allocate/free/map/unmap all the global
context buffers. It also provides APIs to get/set size of the buffers,
and to get memory handle of the buffers
Use interfaces exposed by this unit instead of directly accessing global
context buffers in common code
Add new header file include/nvgpu/gr/global_ctx.h to declare all the
interfaces.
Rename "struct gr_ctx_buffer_desc" to "struct nvgpu_gr_global_ctx_buffer_desc"
which holds all data for each global context
Remove void *priv since it is no longer used
Add size to the desc structure to store the requested size
Remove global_ctx_buffer_size from struct nvgpu_gr_ctx since it is no longer
used for any real purpose
Jira NVGPU-1625
Change-Id: I3feaf47bc2fdf192f36b136f2ef80a49d1782c5d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1977884
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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In gr_gp10b_set_cilp_preempt_pending() we already extract TSG pointer
by calling tsg_gk20a_from_ch() which safely returns correct TSG or
NULL in error case
But before calling g->ops.fifo.post_event_id() we again extract TSG
by directly accessing g->fifo.tsg array, and this could result in
getting invalid TSG pointer
Fix this by removing direct TSG extraction through g->fifo.tsg
Bug 2444819
Jira NVGPU-1601
Change-Id: I9d49b5309c74e162828e7cb7d97556aae939a07c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1984954
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In gk20a_gr_handle_fecs_error(), we right now check the error code in
mailbox to identify if we hit timestamp buffer full error interrupt
This error code right now is hard coded to 0x26
But on Turing ucode this error code is set to 0x32
Add new HAL g->ops.fecs_trace.get_buffer_full_mailbox_val() to get
correct error code per platform and use this in
gk20a_gr_handle_fecs_error()
Bug 200471541
Bug 2469604
Change-Id: I7325354b39d35b1c8b218e554814316d22950469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978144
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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For K4.14, the pci driver is enabled with CONFIG_PCIE_TEGRA=y. The
check of dummy APIs doesn't capture this config. Fix this to use
tegra_pcie_detach/attach_controller() APIs from the pci driver.
Bug 200480179
JIRA NVGPU-1100
Change-Id: I3a2b4f243dce6ead1174b12bc8ce2ffb6700c86b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1982549
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When called with timeout=0, NVGPU_COND_WAIT_INTERRUPTIBLE macro
ignores the return code from wait_event_interruptible. As a result
we do not detect when the call is interrupted, and the calling
process hangs.
Use wait_event_interruptible return code in case of infinite timeout.
Bug 200384829
Change-Id: I930f0d08c73a3b91ab20a6c8faaf633a3d7aee4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1982242
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This reverts commit 98dca979d6.
The original commit was reverted because there was an issue
where commit "include: uapi: move nvhost user-interface headers" in
linux-nvidia repo caused DLA UMD driver to be exposed of including
kernel headers directly.
Since then, DLA UMD driver has been fixed to use headers from
user-space code. And hence restore this change and commit
"include: uapi: move nvhost user-interface headers" in linux-nvidia
repo.
Bug 200471393
Change-Id: Ic8627aca37422aad9b2549c9b7e6de1474d80af9
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1980596
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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The GC-OFF feature shall be available only for selective
dGPUs like Volta, etc. To enable this, add a platform flag
to control GC-OFF feature for a given dGPU.
If GC-OFF is not enabled for a dGPU, EPERM error will be
returned by kernel interfaces.
JIRA NVGPU-1100
Change-Id: Ic9e4492b2bb8916d520e78ecb6a500ccd349b70c
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1923249
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. Most of the time, callers of pmu_wait_message_cond ignore the
return value. This patch changes the signature to return void, and adds
a new pmu_wait_message_cond_status for callers that need the return
information.
JIRA NVGPU-677
Change-Id: Ibaa15b04c4d40a7de73f39a7d6eb68f9e3da71f3
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978211
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The else path in the nvgpu_assert() call definition handles the
non-Linux kernel platforms. These platforms are generally safety
conscious and as a result care about MISRA scans and unit testing.
The static inline hides the BUG_ON() call from the unit test
branch analyzer and the MISRA analyzer. Note: the MISRA issue
still exists; however, it's just not seen when analyzing patches
that only use the nvgpu_assert() call.
This patch combines the __POSIX__ path with the general else path
to ensure that all non-Linux platforms use the aforementioned
static inline.
JIRA NVGPU-1246
Change-Id: I3f267224acd0b27429302118872c40ca6d7b9137
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1977276
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move the nvlink HAL code to unit specific directory as part
of nvgpu restructing.
This move is done after removing usage of other unit's hardware
headers from nvlink. Also confirmed that no other unit files are
including nvlink hardware headers.
JIRA NVGPU-966
Change-Id: I301e3f8de37c5792a3e1e799b97e5fdfc131f058
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975259
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MISRA Rule 10.1 states that operands shall not be of an
inappropriate essential type.
For example, the use of bitwise OR on signed values is not
permitted.
Both the pmu_read_message() and sec2_read_message() routines
do this in some cases when an error (or unexpected number of
bytes) is returned from the falcon queue pop/rewind routines.
This patch eliminates the MISRA violations by modifying these
cases to return the falcon queue operation error unmodified in the
corresponding status argument (or use -EINVAL in the event the
requested number of bytes isn't returned).
To reduce code duplication new pmu_falcon_queue_read() and
sec2_falcon_queue_read() routines are added here to wrap the
code that handles the error for the respective units.
Note that higher up in the call sequence (tu104_sec2_isr() in the
sec2_read_message() case and gk20a_pmu_isr() in the pmu_read_message()
case) the actual status value is only checked for non-zero or ignored
altogether. So it appears no existing code would depend on the
bitwise OR result anyway.
JIRA NVGPU-650
Change-Id: Id303523ac096f1989e612044082e0a62ae8179c2
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972624
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This change adds RDMA supports for tegra iGPU.
1. Cuda Process allocates the memory and passes
the VA and size to the custom kernel driver.
2. The custom kernel driver maps the user allocated
buf and does the DMA to/from it.
3. Only supports iGPU + cudaHostAlloc sysmem
4. Works only for a given process.
5. Address should be sysmem page aligned and size should
be multiple of sysmem page size.
6. The custom kernel driver must register a free_callback when get_page()
function is called.
Bug 200438879
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Change-Id: I43ec45734eb46d30341d0701550206c16e051106
Reviewed-on: https://git-master.nvidia.com/r/1953780
(cherry picked from commit d6278955f6)
Reviewed-on: https://git-master.nvidia.com/r/1821407
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Changes between GV100 and Turing VFE pstate tables-
1. PS3.5 ucode packs two sets of vfe boardobjgrp - primary and
rppm in new struct whose name is appended with suffix pack. The
rppm (runtime power and performance model) set is needed to
achieve Max Q. The rppm set is not relevant to Automotive SKUs and
entries are set to 'disabled'. But the turing ucode in R400 uses
the 'pack' struct to calculate supersurface offset and size of
vfe_var/equ boardobjgrp.
2. Header size has been increased to add RPPM related VFE variable
and equation count.
VFE Variables boardobjgrp specific changes-
1. New var type 'single caller specified' had been added to represent
generic type of variable which is not associated with voltage or
frequency but identified by a Unique ID.
2. The frequency variable type can be associated with a clock domain,
if the clock domain index availability flag is set.
VFE Equations boardobjgrp specific changes-
1. New entry type 'scalar' had been added to allow scaling equation
pointed by 'equ_idx_to_scale'.
2. More ouput types are added to represent the equation evaluation
results.
We modify the nvgpu Turing driver and GV100 ucode to adapt to these
changes.
This patch also fixes some MISRA defects in touched files.
JIRA NVGPU-1178
Change-Id: I90910ac8dccf0b98a588cbc442dc11ac4fbd2e61
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928999
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaikundanathan S <vaikuns@nvidia.com>
Tested-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Update the fifo code to use the HALs exposed by "Top" unit to
read data from device_info table.
The information for GRAPHICS engine in device_info table is
now parsed using the get_device_info HAL from "Top" unit.
Copy engine(CE) has multiple entries in the device_info table
corresponding to each instance of the engine. Prior to Pascal, each
instance of an engine was denoted by different engine type.
For example in GM20B, there are engine types like COPY_ENGINE0,
COPY_ENGINE1 and so on. In Pascal and chips beyond, a new field
called "inst_id" is added and the engine_type is kept the same for
different instances of an engine. For example in GP10B, all copy
engine entries have same engine type i.e ENGINE_LCE, but different
inst_ids. So for Pascal and chips beyond, we use a different HAL to
get CE information from device_info table.
JIRA NVGPU-1053
Change-Id: Ib40a616d903a5dbef5730678c2ebc3454b8e900d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969400
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GVS: Gerrit_Virtual_Submit
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