Commit Graph

963 Commits

Author SHA1 Message Date
Tejal Kudav
3b1bbc7259 gpu: nvgpu: Remove GP10b support
Starting 6.0.2.0, deprecate support for GP10b. Delete GP10b specific
things such as platform data, ucodes, regops allowlist, cg/pg register
list. Per unit specific gp10b code cleanup will be done later.

Bug 3431142

Change-Id: I4d5fd9ad8c6ee53845df3b6b2298af64d76e86c3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2630946
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-03 08:43:52 -08:00
Ninad Malwade
69ffeeaa26 gpu: nvgpu: fix the tpc_pg_mask read and store return values
tpc_pg_mask_read: function returns the value stored in the
tpc_pg_mask node. Since, it does not have the terminator it
returns garbage value after the mask value and gets troublesome
to parse in the userspace. Fix is to add '\n' at the end of the
mask value to be consistent with the earlier releases.

tpc_pg_mask_store: In this function there is a call to check if
gpu is powered on or not. In case when gpu is powered on, the return
value is just assigned to the 'err' variable which is never
returned to notify the application to follow the next steps. Thus,
need to return this value and inform the same to the userspace.

Bug 3445617

Change-Id: Ibb6fed88c83c751a5fb73181089274aa27c3f18b
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2630925
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-11-30 11:30:16 -08:00
Sagar Kamble
b6d349dcf6 gpu: nvgpu: init all buffer compbits state members
User fence syncpt_id in the buffer compbits state was set to 0
on allocation through PREPARE_COMPRESSIBLE_READ ioctl or
MARK_COMPRESSIBLE_WRITE ioctl.

In case NVGPU_GPU_COMPBITS_GPU is requested through the ioctl
PREPARE_COMPRESSIBLE_READ, CDE conversion command is not
submitted and the output fence is cloned from the initial
state fence (with syncpt_id=0).

NvRmSyncWait on this fence from userspace lead to below error:
  13e40000.host1x: nvhost_syncpt_wait_timeout: invalid syncpoint id 0

Initialize the buffer compbits state user fence syncpt_id to
NVGPU_INVALID_SYNCPT_ID with nvgpu_user_sync_init() so that
the userspace skips the NvRmSyncWait on that fence.

While at it, initialize other uninitialized members, valid_compbits
and zbc_color.

Bug 3360675

Change-Id: Ie2a584546e1ed37841cbdc3472b598794f911e6f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2631235
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-27 10:08:14 -08:00
Sagar Kamble
41df3e17a7 gpu: nvgpu: fix nvgpu remove sequence
While removing the nvgpu module, all gpu unmaps should happen before
removing the PMU support as ELPG_MS accesses pmu pg structure and
ELPG_MS is disabled/enabled while accessing TLB or cache flush.

nvgpu_fb_vab_teardown_hal and mmu_fault.info_mem_destroy do gpu
unmaps. They were executed post removal of PMU support. Fix the
sequence.

Bug 3448630

Change-Id: I44925c313c625a2d0f297d1367d69069b3deacef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632490
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-26 08:47:52 -08:00
Rajkumar Kasirajan
71cd434f4f gpu: nvgpu: add thermal cooling support
Add devfeq thermal cooling device for GPU software thermal throttling.

Bug 3287074

Change-Id: Ib0b53a58177964dfda3c8993da9c4835e2cb8a6e
Signed-off-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2625659
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-26 08:46:00 -08:00
Seshendra Gadagottu
616a885079 gpu: nvgpu: ga10b: enable frequency scaling
Enable GPU frequency scaling for t234 silicon.

Bug 3315239

Change-Id: I0b581283d4c9558fb9f7c3b553ea8bee71ba22af
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2617544
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2021-11-25 08:16:42 -08:00
Seshendra Gadagottu
fc27aab523 gpu: nvgpu: ga10b: update clock operations
ga10b can have 2 GPCs and each GPC is clocked with separate
gpc clk. Added ga10b specific set_rate/get_rate operations
for gpcclks considering GPC floor-sweeping info.

Bug 3315239

Change-Id: I4e2156b4e06a1580a60d832e0d3296ed3dc17887
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2617441
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Tejal Kudav <tkudav@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-11-25 08:16:31 -08:00
Jon Hunter
02ab4c3880 gpu: nvgpu: Correct permissions for cbc_ctrl debug node
The cbc_ctrl debugfs node is created with both read and write
permissions, however, this node only supports being written and
not read. Fix this by removing read permissions for this debugfs
node.

Bug 3402817

Change-Id: I16ffba8285144389758be283121c3096745aae73
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2630027
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-24 17:55:57 -08:00
Divya Singhatwaria
09c0813c94 gpu: nvgpu: ga10b: disable ELPG
Disable ELPG to avoid pmu halt

Bug 3430273
Bug 3439350

Change-Id: I1a7ac388e334010a4a7cf848fa99bb078c5026ca
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628191
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-24 10:53:20 -08:00
Konsta Hölttä
fe7ae02f5f gpu: nvgpu: add sched domain bind ioctl
Support binding TSGs to some other scheduling domain than the default
one. Binding happens by name until a more robust interface appears in
the future, as the name is a natural identifier for users.

No other domains are actually created anywhere yet; that will happen in
next patches.

Jira NVGPU-6788

Change-Id: I5abcdea869b525b0a0e9937302f106f7eee94ec2
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628047
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-24 04:47:30 -08:00
Tejal Kudav
6648cfea09 gpu: nvgpu: Disable low power features on AV+L
NVGPU does not support low power features on hypervisor
based embedded environments.Disable low power features like ELPG,
AELPG and railgating on AV+L using the nvgpu_is_hypervisor_mode().

JIRA NVGPU-7283

Change-Id: I930e06ae711ee1485109b7f519a2dacc95b7d74b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2610056
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2021-11-19 13:16:36 -08:00
Debarshi Dutta
5d42343cbf gpu: nvgpu: use appropriate permissions for debugfs entries
SW Profiler's debugfs entry "enable" has both RW permissions set
however the corresponding read operation is set to NULL.

Similarly, the other entries i.e. "percentiles", "raw_entries" and
"basic_stats" only have a read operation defined and write is set to
NULL.

To enable correct permissions, set permission for "enable" to "W"
and set permissions for others as "R" only.

Bug 200747304

Change-Id: I296a0ff08a871f752988c9b0a671c080695d5eab
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2566322
(cherry picked from commit 8542dd388da536ee693610acd0bb3a679ff52881)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628035
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-19 08:08:11 -08:00
Tejal Kudav
79ee724b04 gpu: nvgpu: Add knob to control dbg/prof support
On production boards, there is requirement to disable GPU
profiler and debugger support. Add DT property 'support-gpu-tools'
which can be modified to enable/disable debugger/profiler support.
The default behavior is to enable the debugging features and set
'support-gpu-tools' to 1. This property is chosen to be u32 value
to be in sync with GPU vserser property by same name.
The debugger/profiler support is disabled by skipping the creation
of below nodes under /dev/nvgpu/:
1. ctxsw
2. dbg
3. prof
4. prof-dev
5. prof-ctx

Bug 200773450
JIRA NVGPU-7109

Change-Id: I86d72d17fa7f5492e117a4c1cd1144623e9b6132
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2592012
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-18 03:57:18 -08:00
Martin Radev
64d2e25382 gpu: nvgpu: Expose cbc status and ctrl debug nodes
This patch adds two new debug nodes:
- cbc_status to retrieve cbc state information
- cbc_ctrl to flush and mmap cbc

These two nodes are to be used for purpose of testing
and debugging. One immediate goal is to use them for
verifying if CBC is programmed correctly via a user
space test.

Bug 3402817

Change-Id: I4046fb45ebfb48cb4644f88621429e1e323972c0
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2620184
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-14 01:29:53 -08:00
Antony Clince Alex
1bcc22ab19 gpu: nvgpu: make mssnvlink programming OS agnositc
Make ga10b_init_nvlink_soc_credits OS agnostic by replacing OS
specific functions with corresponding nvgpu wrappers. This function is now
assigned to gops.mssnvlink.init_soc_credits HAL.

Introduce nvgpu wrapper, nvgpu_io_map/unmap to map/unmap specified
physical address range.

Jira NVGPU-6641

Change-Id: I337bc75b8ec36552fe471bf5e42f62c19f67ed4a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618237
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2021-11-12 07:31:15 -08:00
Sagar Kamble
83dbb711bb gpu: nvgpu: make buffer metadata support independent of compression
Earlier, buffer metadata support was made dependent on compression.
However that is not required.

Update the enabled flag NVGPU_SUPPORT_BUFFER_METADATA setup for
various hals. Enable it for all from linux characteristics init.

Update REGISTER_BUFFER and GET_BUFFER_INFO ioctls to seggregate
the compile/runtime compression functionality.

If compression is disabled, return error in case comptags are
required else don't fail the REGISTER_BUFFER ioctl.

Bug 200767700

Change-Id: I3850ccc879f180c97b830fb3d652c094b9d28a5b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2614378
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2021-11-12 07:30:33 -08:00
Jon Hunter
aa44d0e041 gpu: nvgpu: Fix build for Linux v5.16-rc1
Building NVGPU against the current upstream mainline kernel is failing
and errors such as the following are seen.

ERROR: modpost: module nvgpu uses symbol dma_buf_map_attachment from
	namespace DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_detach from namespace
	DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_vmap from namespace
	DMA_BUF, but does not import it.

Following upstream commit 16b0314aa746 ("dma-buf: move dma-buf symbols
into the DMA_BUF module namespace"), it is now necessary to import the
DMA_BUF module namespace into the NVGPU driver to fix this.

Change-Id: I901b74cea692a5e0d66a190d01fe74a55aaf4431
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621641
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-12 02:51:30 -08:00
Sagar Kamble
688a6aa17d gpu: nvgpu: change set_err_notifier error message to info type for forced channel reset
Below error notifier message is not really warning/error as that
is user triggered reset and the notifier value set is already
consumed by userspace hence limit this message to INFO type.

nvgpu: 17000000.gp10b     nvgpu_set_err_notifier_locked:142  [ERR]  error notifier set to 43 for ch 460

Bug 3344409

Change-Id: Ia41cc85f30111ef72994f3ce8e5113e881c06b1b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2620974
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-08 15:08:32 -08:00
Konsta Hölttä
3cf796b787 gpu: nvgpu: move active bitmaps to domain
Move the active_channels and active_tsgs bitmaps from struct
nvgpu_runlist to struct nvgpu_runlist_domain. A TSG and its channels are
currently active as part of a runlist; in the future, a runlist may be
switched from multiple domains that each are a collection of TSGs.

The changes are still internal to the runlist code. Users of runlists
need no modifications.

Jira NVGPU-6425

Change-Id: I2d0e98e97f04b9716bc3f4890cf881735d0ab664
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618387
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2021-11-03 20:55:08 -07:00
Debarshi Dutta
e616b2ba4d gpu: nvgpu: fix access-out-of-bounds issue
As part of the function gp10b_clk_get_freqs, the code walksthrough
the H/W frequency table and populates the gp10b_freq_table by picking
only GP10B_NUM_SUPPORTED_FREQS =
 GP10B_MAX_SUPPORTED_FREQS/GP10B_FREQ_SELECT_STEP frequencies at max.

The access-out-of-bounds happen when sel_freq_count reaches
GP10B_NUM_SUPPORTED_FREQS and new_rate equals max_rate, resulting
in one additional update that is beyond the size of gp10b_freq_table
table.

Also, removed the warning as it will never be true.

Bug 3407276

Change-Id: Ic496ccdda1784130e7139bd93d068be58eb60a35
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2617850
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-11-02 14:04:47 -07:00
Seshendra Gadagottu
a70df981e6 gpu: nvgpu: ga10b: handling gpcclk requests with GPC floor-swept
ga10b supports floor-sweeping of GPCs. Check for tegra soc
fuse info, before making gpcclk requests to BPMP for available
GPCs.

Bug 3362403

Change-Id: I3f5e2d85b785098ce3a8c8d7d8a5621446e94c15
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2616898
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2021-10-27 21:18:19 -07:00
Konsta Hölttä
f4ec400d5f gpu: nvgpu: simplify nvgpu_timeout_init
nvgpu_timeout_init() returns an error code only when the flags parameter
is invalid. There are very few possible values for flags, so extract the
two most common cases - cpu clock based and a retry based timeout - to
functions that cannot fail and thus return nothing. Adjust all callers
to use those, simplfying error handling quite a bit.

Change-Id: I985fe7fa988ebbae25601d15cf57fd48eda0c677
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613833
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2021-10-26 13:47:32 -07:00
Pyarelal Knowles
99a664bda0 gpu: nvgpu: enable stencil zbc
The implementation already exists. This change
adds NVGPU_GR_ZBC_TYPE_STENCIL and plumbs through
the stencil value from NvRmGpuDeviceZbcAddStencil
through NVGPU_GPU_IOCTL_ZBC_SET_TABLE.

Adds cases for querying the stencil values,
enabling NvRmGpuDeviceZbcGetStencilTableEntry.

Bug 3403523
Bug 3395601

Change-Id: I42c9a2967d0433e0bb08343aabeff0fe465f231e
Signed-off-by: Pyarelal Knowles <pknowles@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2554963
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2021-10-26 09:47:17 -07:00
Divya
d538737ba1 gpu: nvgpu: Add ELPG_MS protected call for L2 flush
- if L2 flush is done when ELPG_MS feature is engaged
  then it can cause some of the signals to go non-idle.
  This can cause idle snap in ELPG_MS.
- To avoid the idle snap, add elpg_ms protected call before
  L2 flush operation

Bug 200763448

Change-Id: I651875bc051c3b7d26d2bb0b593083512a5765b2
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2599459
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-10-22 06:20:13 -07:00
Divya
727a2573dc gpu: nvgpu: add wrapper for MS_LTC disallow/allow
- add separate wrapper function for sending ALLOW
  and DISALLOW RPCs for MS_LTC engine
- add separate SW blocker function for MS_LTC

Bug 200763448

Change-Id: I80b6c59f6acaec03ab9fcd2e1ce82817f55124b2
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603122
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-22 06:20:00 -07:00
Tejal Kudav
d61a84c8d1 gpu: nvgpu: ga10b: Set GPU clocks to max rate
Max GPU clk supported by BPMP is 1.275GHz. Remove the hard-coded
default value of 1GHz and pass an arbitrary high value to BPMP
API to set the clocks to max rate. Use UINT_MAX instead of a
hardcoded clk max_rate value (like 1.275GHz) to ensure that the max
clock rate supported by BPMP is chosen during clk_set_rate().

Bug 200779751

Change-Id: I08719c3348e7e5c86aa45b423bac3a099cead005
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2612146
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-19 07:59:43 -07:00
Divya Singhatwaria
c482effaf9 gpu: nvgpu: ga10b: Enable ELPG
Enable ELPG for ga10b.

Bug 200774890

Change-Id: Iec6e74954fe83dd823b927d44a225eec1bb42d9a
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2589915
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-14 17:02:44 -07:00
Tejal Kudav
243e52a771 gpu: nvgpu: ga10b: Disable compression on Av+L/Q
GPU HW expects physically contiguous addresses when clearing
the compression bit store in memory. Currently on hypervisor setup,
the DMA_ATTR_FORCE_CONTIGUOUS flag ensures contiguous IPA, but it
is not possible to ensure contiguous physical memory.Disable
compression on virtualized environments until physically contiguous
memory is feasible.

Buffer Metadata support is dependent on compression support.
Move the initialization of NVGPU_SUPPORT_BUFFER_METADATA flag to
common code where NVGPU_SUPPORT_COMPRESSION is initialized.

Bug 200780546

Change-Id: Id94bffc878e275a80948880f0475162d0bb4ddae
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2607830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-11 17:01:06 -07:00
Konsta Hölttä
a28612220a gpu: nvgpu: return -ENOSYS if no host1x
The callers of nvgpu_get_nvhost_dev() expect that if all goes well,
nvhost and syncpoint support exists. Thus if the device tree entry is
not found, return -ENOSYS instead of 0.

Bug 3394386

Change-Id: I4617aa2cfc240ade53294c26b3e8c2ce50b66913
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2608549
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-11 12:29:09 -07:00
Divya Singhatwaria
5e5f1baa10 gpu: nvgpu: Add debugfs node for ELPG_MS transitions
- To capture ELPG_MS transitions, add debugfs node
  "elpg_ms_transitions".
- After successful entry and exit in ELPG_MS sequence
  the transition increments by 1 and this is captured
  in "elpg_ms_transitions" debugfs node.

JIRA NVGPU-6551

Change-Id: I961693b90f869935240a4be17d932306f15c3e2d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2599461
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-11 08:16:48 -07:00
Sagar Kamble
396c77d7f8 gpu: nvgpu: fix the return type for power node read/write fops
When error (negative value) with int type is returned from read/write
fops (gk20a_power_node_ops) is read as ssize_t value as expected in
userspace it will be seen as large non-negative number and will
suppress the error.

Make return type for these fops ssize_t.

Also include power_ops.h in power_ops.c. This would have caught the
type mismatch issue.

Bug 3388725

Change-Id: Ie66b0178b31a1b7d147b4f441884bbba3bd2e4d8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604342
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-07 17:53:30 -07:00
Seshendra Gadagottu
963022ed41 gpu: nvgpu: ga10b: separate gpc and fbp static pg requests
gpc and fbp can be static powergated independently, so separate
these requests.

Bug 200768322
JIRA NVGPU-6433

Change-Id: I61d09cff964ac8a0bacdcf460f88d6abc6656bb8
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2600879
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-06 18:15:28 -07:00
Sagar Kamble
18239c3a25 gpu: nvgpu: fix user input string preparation in gk20a_power_write
String parameter to kstrtouint has to be null terminated.
If the input string to gk20a_power_write doesn't have the
terminating null character then gk20a_power_write passed
string without appending null character to kstrtouint.

Fix this by preparing string to occupy null character in
the end after user supplied string characters.

Bug 3388725

Change-Id: I521f879326908e296dd9a32b5781db490d40bdd2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603985
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-04 10:29:58 -07:00
Seshendra Gadagottu
f80670915e gpu: nvgpu: ga10b: enable all cg power features.
Enable ELCG/BLCG and SLCG for ga10b.

Bug 200766930

Change-Id: Ifeb094b91489d8c97245d261bce794acf458bde0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2604379
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-02 17:55:47 -07:00
Konsta Hölttä
1b1d183b9c gpu: nvgpu: simplify gmmu map calls
Introduce nvgpu_gmmu_map_partial() to map a specific size of a buffer
represented by nvgpu_mem, or what nvgpu_gmmu_map() used to do. Delete
the size parameter from nvgpu_gmmu_map() such that it now maps the
entire buffer. The separate size parameter is a historical artifact from
when nvgpu_mem did not exist yet; the typical use is to map the entire
buffer.

Mapping at a certain address with nvgpu_gmmu_map_fixed() still takes the
size parameter.

The returned address still has to be stored somewhere, typically to
mem.gpu_va by the caller so that the matching unmap variant finds the
right address.

Change-Id: I7d67a0b15d741c6bcee1aecff1678e3216cc28d2
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2601788
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-01 21:38:43 -07:00
Vedashree Vidwans
6d38ae76ce gpu: nvgpu: ga10b: secure alloc after GPU enable
Secure alloc uses VPR memory and this might trigger VPR resize. Move
platform secure alloc after resuming GPU.

Bug 200760980

Change-Id: Id67a5e6caa6a9f9d9ded39e0a0340b69852d5c04
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603755
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Ashish Mhetre <amhetre@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-01 14:11:14 -07:00
Konsta Hölttä
44422db851 gpu: nvgpu: simplify gmmu unmap calls
Introduce nvgpu_gmmu_unmap_addr() to unmap a nvgpu_mem that was mapped
at some other address than mem.gpu_va, which can be the case for buffers
that are shared across different address spaces. Delete the address
parameter from nvgpu_gmmu_unmap(), as the common case is to store the
address to mem.gpu_va when mapping the buffer.

Modify some instances of consecutive unmap + free calls to call just
nvgpu_dma_unmap_free().

Change-Id: Iecd7c9aa41d04e9f48e055f6bc0c9227cd759c69
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2601787
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-30 16:29:41 -07:00
Seshendra Gadagottu
79f83f4993 gpu: nvgpu: ga10b: set bpmp mrq on static pg request
Set BPMP MRQ strap on static PG request for gpc, tpc or fbp.

Bug 200768322
JIRA NVGPU-6433

Change-Id: Ic7e99748b035423d7ad279a1344331ed3396c215
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2600665
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-26 17:55:12 -07:00
Divya
5625a383ff gpu: nvgpu: Add sysfs node for taking static PG config
- Add sysfs node for GPC, TPC and FBP mask values
- Add the following nodes:
  gpc_pg_mask
  tpc_pg_mask
  fbp_pg_mask
  to allow userspace to pass static pg config values

Bug 200768322
JIRA NVGPU-6433

Change-Id: I072cd2cad65bfb389c2164f1450ac1ab5bcad064
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2594803
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-26 00:35:24 -07:00
Divya
1a4737546f gpu: nvgpu: ga10b: Add MRQ interface support
Add MRQ_STRAP BPMP interface support to send GPC, FBP
and TPC static powergating mask

Bug 200768322
JIRA NVGPU-6433

Change-Id: Iff5019ac283eda73865c6efe672b1c6c3e3f118b
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2595231
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-25 15:47:30 -07:00
Divya
ae2d561c48 gpu: nvgpu: add platform support for Static PG
- Add support for taking static PG config values
  from DT nodes
- Check those values against valid set of values
  for GPC, TPC and FBP
- Store valid values in g->gpc_pg_mask, g->fbp_pg_mask
  and g->tpc_pg_mask[] array.

Bug 200768322
JIRA NVGPU-6433

Change-Id: Ifc87e7d369034b1daa13866bc16a970602514bf6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2594802
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-25 15:47:25 -07:00
Divya Singhatwaria
af24bff07d gpu: nvgpu: ga10b: Disable ELPG_MS
ELPG_MS issue is under debug.
Disabling the feature till it gets resolved.

Bug 200763448

Change-Id: Idd66146c9387f98c64e95fa99f9423dfebbe6b77
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2598456
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-22 20:39:24 -07:00
Divya
9266da636b gpu: nvgpu: update static pg support for pre-si
- On pre-silicon platform, static pg will be
  done by nvgpu driver. For this, retain structs
  and HALs of static pg.
- Add the static pg support under pre-silicon code.
- On silicon, the static pg will be done by BPMP.
- Rename variables used in static pg for better
  readability and consistency

Bug 200768322
JIRA NVGPU-6433

Change-Id: Ib31c0f83b751c2b1563a36bd51af78a0bd12a117
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2594801
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-21 13:40:11 -07:00
Mayur Poojary
fe7368f8f4 gpu: nvgpu: ga10b: Support emulate mode
Add sysfs node to enable gpu emulate_mode and
pass the value to acr through acr descriptor struct.

Bug 3279344

Change-Id: I936b1dda84d7f4f3688237308223c019798bdce3
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2591377
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-20 16:40:34 -07:00
Divya Singhatwaria
95c954cf9f gpu: nvgpu: ga10b: enable can_elpg_init flag
Set can_elpg_init flag to true. This will allow enabling
ELPG via sysfs node.

Bug 200766930

Change-Id: I7e16d3d233a212ec01728eae119d6a60fcf6390e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590733
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-17 04:03:20 -07:00
Debarshi Dutta
9328f057a7 gpu: nvgpu: fix use-after-free use case of CE APP.
The following issue is reported when running sudo modprobe -r nvgpu

[  134.066392] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000058
[  134.066428] Mem abort info:
[  134.066431]   ESR = 0x96000004
[  134.066434]   EC = 0x25: DABT (current EL), IL = 32 bit
[  134.066450] [0000000000000058] pgd=0000000000000000, p4d=0000000000000000
[  134.066459] Internal error: Oops: 96000004 [#1] PREEMPT_RT SMP

[  134.066639] pc : nvgpu_cic_rm_wait_for_stall_interrupts+0x78/0xd0 [nvgpu]
[  134.066847] lr : nvgpu_cic_rm_wait_for_stall_interrupts+0x74/0xd0 [nvgpu]
[  134.067043] sp : ffff80001971ba80
[  134.067046] x29: ffff80001971ba80 x28: ffff000093b0da00
[  134.067054] x27: 0000000000000000 x26: ffff80001c28b990
[  134.067061] x25: ffff00008cd01000 x24: 0000000000000bb8
[  134.067067] x23: 0000000000000000 x22: ffff0000915b0000
[  134.067073] x21: ffff000093b0da00 x20: ffff0000915b0000
[  134.067079] x19: ffff0000915b0000 x18: 0000000000000036
[  134.067085] x17: 0000000000000000 x16: 0000000000000000
[  134.067091] x15: ffff8000126b5fd8 x14: 7373616c633d4d45
[  134.067097] x13: ffff8000098abef0 x12: 0000000000000000
[  134.067102] x11: ffff8000098ab5a0 x10: ffff8000098abef8
[  134.067108] x9 : ffff80001010e844 x8 : ffff80001971ba48
[  134.067115] x7 : 2222222222222222 x6 : ffff000093b0da00
[  134.067122] x5 : ffff8000098b1fd8 x4 : 0000000000000000
[  134.067127] x3 : 0000000000000000 x2 : 0000000000000000
[  134.067133] x1 : 0000000000000000 x0 : 0000000000000000
[  134.067138] Call trace:
[  134.067140]  nvgpu_cic_rm_wait_for_stall_interrupts+0x78/0xd0 [nvgpu]
[  134.067328]  nvgpu_cic_rm_wait_for_deferred_interrupts+0x20/0xb0 [nvgpu]
[  134.067517]  nvgpu_channel_deferred_reset_engines+0x29c/0x920 [nvgpu]
[  134.067714]  nvgpu_channel_close+0x18/0x20 [nvgpu]
[  134.067904]  nvgpu_init_pramin+0x2ac/0x350 [nvgpu]
[  134.068092]  nvgpu_ce_app_destroy+0x94/0xe0 [nvgpu]
[  134.068279]  nvgpu_put+0x90/0x120 [nvgpu]
[  134.068465]  nvgpu_pci_shutdown+0x29c/0x18a0 [nvgpu]
[  134.068655]  pci_device_remove+0x44/0xe0
[  134.068665]  device_release_driver_internal+0x114/0x1f0
[  134.068701]  driver_detach+0x54/0xe0
[  134.068709]  bus_remove_driver+0x70/0x120
[  134.068733]  driver_unregister+0x34/0x60

The above issue occurs due to freeing of CIC resources earlier than
dependent users of interrupts e.g. CDE, CE etc.

As a solution, move CIC deinit sequence to end of nvgpu_put.
This handles deinit properly for VGPU/IGPU/DGPU.

Bug 200763510

Change-Id: I696e31d5e03a9468cccfe710048000dbf7cf0269
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2592063
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-16 21:45:43 -07:00
Sahil Mukund Patki
794d1edbe4 gpu: nvgpu: Fix debugfs compilation errors
The function "nvgpu_ce_debugfs_init" is declared in "debug_ce.h".
This file is only compiled when CONFIG_DEBUG_FS is enabled. So
any accesses to this function result in compilation errors when
CONFIG_DEBUG_FS is disabled.

This patch fixes the errors by guarding all accesses to the above
mentioned function by CONFIG_DEBUG_FS.

Bug 200755555

Change-Id: Ie566413913c4a72b10b87c3285d1263d1c811074
Signed-off-by: Sahil Mukund Patki <spatki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2591304
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-15 09:16:22 -07:00
prsethi
dd94573e55 gpu: nvgpu: Update KMDI mapping interface
Finding gpu va mapping inside a given range is a two step process where
in first step number of mapping are queried and at second step it
queries for all the continues mapping range for that given gpu va
range. Mapping interface should count and return number of mappings if
input count is 0 in place of failing it.
Patch make the change for this two step process and only returns count
at first step and in second step returns the continues memory ranges.

Patch also replaces nvgpu_zalloc with nvgpu_big_zalloc to handle bigger
size allocation.

Bug 200722275

Change-Id: I56428deafa560ac8471c78f102bb1f9dbe20cabc
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2591043
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-15 09:16:06 -07:00
Debarshi Dutta
79ab0ba6c4 gpu: nvgpu: remove sudo restrictions on gpu nodes.
When SMC modes are enabled, devices are created with sudo-only
access permissions. Those permissions are relaxed to allow non-sudo
processes to allow job submission.

Also, allow only root users to poweroff explicitely via the device
power node.

Bug 3374078

Change-Id: Ieb869399c3ada3588708cf2bc99a580414023cb7
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2590584
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-15 09:15:49 -07:00
Antony Clince Alex
f3164a4672 gpu: nvgpu: fix tpc_fs_mask syfs output
The tpc_fs_mask sysfs entry outputs the TPC masks in logical order,
however, contradicts the gpc_fs_mask which is in physical order.
So for consistency, update tpc_fs_mask to provided output in physical
order.

Bug 3364907

Change-Id: I2cc7b66dac2bea215024ef95944cde4b46d51c9a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2593803
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-14 16:14:33 -07:00