Since we plan to separate engine DMEM/EMEM and FB queues into separate
implementations, let's make the engine queue_head and queue_tail APIs
independent of nvgpu_falcon_queue parameter.
JIRA NVGPU-1994
Change-Id: I389cc48d4045d9df8f768166f6a1d7074a69a309
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
We get gpc_mask by calling GR HAL g->ops.gr.get_gpc_mask()
But gpc_mask should be logically owned by gr/config unit
Hence add new gpc_mask field to nvgpu_gr_config
Initialize it in nvgpu_gr_config_init() by calling a new HAL
g->ops.gr.config.get_gpc_mask() if available
If HAL is not defined we just initialize it based on gpc_count
Expose new API nvgpu_gr_config_get_gpc_mask() to get gpc_mask
and use this API now
Remove gr_gm20b_get_gpc_mask() and HAL g->ops.gr.get_gpc_mask()
Update GV100 and TU104 chip HALs to remove old and add new HAL
Add gpc_mask to struct tegra_vgpu_constants_params to support this
on vGPU. Also get gpc_mask from vGPU private data in
vgpu_gr_init_gr_config()
Jira NVGPU-1879
Change-Id: Ibdc89ea51df944dc7085920509e3536a5721efc0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016084
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Unit gr/config right now queries gpc_count from priv_ring by directly
reading the value from register
priv_ring unit now exposes below HAL to get gpc_count
g->ops.priv_ring.get_gpc_count()
Use this HAL in gr/config unit
Jira NVGPU-1879
Change-Id: Ibd3557b7f906690a7ad18f11d02a0a6990b98337
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016083
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
In gr/config unit we right now query max gpc_count and tpc_per_gpc_count
by directly accessing registers using hw_top_gm20b.h h/w header
Update TOP unit to provide below HALs
g->ops.top.get_gpc_count()
g->ops.top.get_tpc_per_gpc_count()
And call these HALs from gr/config
Jira NVGPU-1879
Change-Id: I39f5d3bb80960d68a1f493b372745e964ad82803
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2016082
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
A new unit nvgpu_engine_status_info is added. The unit provides a HAL
ops function pointer read_engine_status_info() to read and produce
a struct of type nvgpu_engine_status_info. Additionally, the unit
provides public APIs to retrieve data from the struct
nvgpu_engine_status_info.
Jira NVGPU-1315
Change-Id: I6c167c36081bee5c9a8db51d3467c8f5f02c2685
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003886
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add a HAL op for resetting the eng_faulted and pbdma_faulted states on a
channel. This used to be a local feature in fifo_gv11b.c; the HAL is
defined for all chips from gv11b onwards.
Jira NVGPU-1307
Change-Id: I120a59c429851cc69e712ddd5b06a4b3d16c06c9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017269
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Refactor read accesses to the ccsr_channel register for channel state to
be done via a channel HAL op for all chips. A new op called read_state
is added for this; information needed by other units is collected in a
new struct nvgpu_channel_hw_state.
Jira NVGPU-1307
Change-Id: Iff9385c08e17ac086d97f5771a54b56b2727e3c4
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Split out ops that belong to channel unit to a new section called
channel. Channel is a broad concept; this includes just the code that
accesses channel registers (ccsr_*). This is effectively just renaming;
the implementation still stays put.
The word "channel" is also dropped from certain HAL entries to avoid
redundancy (e.g., channel.disable_channel -> channel.disable).
fifo.get_num_fifos gets an entirely new name: channel.count.
Jira NVGPU-1307
Change-Id: I9a08103e461bf3ddb743aa37ababee3e0c73c861
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017261
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.
Jira NVGPU-1948
Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.
Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.
JIRA NVGPU-1008
Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
gr_gk20a_update_hwpm_ctxsw_mode() right now validates the incoming
hwpm mode, checks if it is already set, and if not, it will go ahead
and set the new hwpm mode by calling g->ops.gr.ctxsw_prog HALs
Instead of programming hwpm mode in gr_gk20a.c, move the programming
to gr/ctx and gr/subctx units by adding below APIs
nvgpu_gr_ctx_prepare_hwpm_mode() - validate the incoming mode and
check if it is already set
nvgpu_gr_ctx_set_hwpm_mode() - set pm mode in graphics context
nvgpu_gr_subctx_set_hwpm_mode() - set pm mode in subcontext
Add gpu_va field to struct pm_ctx_desc to store the gpu_va to be
programmed into context
Rename NVGPU_DBG_HWPM_CTXSW_MODE_* to NVGPU_GR_CTX_HWPM_CTXSW_MODE_*
and move them to gr/ctx.h
Remove below HALs since they are no longer used
g->ops.gr.ctxsw_prog.set_pm_mode_no_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_ctxsw()
g->ops.gr.ctxsw_prog.set_pm_mode_stream_out_ctxsw()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: Id2a4d498182ec0e3586dc7265f73a25870ca2ef7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011093
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
In gr_gk20a_ctx_zcull_setup(), we configure context/subcontext with
zcull details
This API now does it directly by calling g->ops.gr.ctxsw_prog HAL
Move all context/subcontext setup to gr/ctx and gr/subctx units
respectively
Define and use below new APIs for same
gr/ctx : nvgpu_gr_ctx_zcull_setup()
gr/subctx : nvgpu_gr_subctx_zcull_setup()
Jira NVGPU-1527
Jira NVGPU-1613
Change-Id: I1b7b16baea60ea45535c623b5b41351610ca433e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011090
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
LSF loader cleanup, on gm20b/gp10b PMU falcon & other GR falcons
uses different struct to store loader config which needs different
functions to fill LSF loader config data, but on gv11b/gv10x/tu10a
uses common falcon struct to store loader config, so made single
function to fill LSF loader config data using ACR LSF struct &
removed duplicate code.
Removed ACR LSF loader ops which were part of PMU ops
to cleanup dependency
JIRA NVGPU-1148
Change-Id: I681829e05463d2517a4049433d8b0de3adeb06d9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012853
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Added data struct under ACR struct to manage LS falcons ucode
as LS falcon ucode holds multiple properties & can be set at acr
init stage to bootstrap LS falcons as required, at present LS falcons
code is part ACR & partially part of PMU code to setup LSF bootstrap,
so, needed to clean up the dependency.
JIRA NVGPU-1148
Change-Id: Ie206e129e3db838041db44d5227ab76a1de991c8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012763
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
A comment for gk20a_fifo_update_runlist() says:
/* add/remove a channel from runlist
special cases below: runlist->active_channels will NOT be changed.
(ch == NULL && !add) means remove all active channels from runlist.
(ch == NULL && add) means restore all active channels on runlist. */
Those special cases call for a new function, so add that. Delete the
update_runlist HAL op and add update_for_channel (like update_runlist
without the special cases) and reload (no channel to add or remove, just
the special cases).
While at it, rename gk20a_fifo_update_runlist_ids to
nvgpu_runlist_reload_ids. It's common across chips and does what the
reload HAL does but for a list of several IDs.
Jira NVGPU-1922
Change-Id: I9a99ab03a636a1214c021faad359d2b304a9472f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2013058
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new unit gr/config to initialize GR configuration like GPC/TPC
count, MAX count and mask
Create new structure nvgpu_gr_config that stores all the configuration
and that is owned by the new unit
Move below fields from struct gr_gk20a to nvgpu_gr_config in gr/config.h
Struct gr_gk20a now only holds the pointer to struct nvgpu_gr_config
u32 max_gpc_count;
u32 max_tpc_per_gpc_count;
u32 max_zcull_per_gpc_count;
u32 max_tpc_count;
u32 gpc_count;
u32 tpc_count;
u32 ppc_count;
u32 zcb_count;
u32 pe_count_per_gpc;
u32 *gpc_tpc_count;
u32 *gpc_ppc_count;
u32 *gpc_zcb_count;
u32 *pes_tpc_count[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_tpc_mask;
u32 *pes_tpc_mask[GK20A_GR_MAX_PES_PER_GPC];
u32 *gpc_skip_mask;
u8 *map_tiles;
u32 map_tile_count;
u32 map_row_offset;
Remove gr->sys_count since it was already no longer used
common/gr/config/gr_config.c unit now exposes the APIs to initialize
the configuration and also to query the configuration values
nvgpu_gr_config_init() is called to initialize GR configuration from
gr_gk20a_init_gr_config() and gr_gk20a_init_map_tiles() is simply
renamed as nvgpu_gr_config_init_map_tiles()
Expose new API nvgpu_gr_config_deinit() to deinit the configuration
Expose nvgpu_gr_config_get_*() APIs to query above configuration
fields stored in nvgpu_gr_config structure
Update vgpu_gr_init_gr_config() to initialize the configuration
from gr->config structure
Chip specific HALs that access GR register for initialization
are implemented in common/gr/config/gr_config_gm20b.c
Set these HALs for all GPUs
Jira NVGPU-1879
Change-Id: Ided658b43124ea61b9f273b82b73fdde4ed3c8f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012167
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes pmu_elpg_statistics to return a status based
on the result of nvgpu_falcon_copy_from_dmem and propagate it upstream.
JIRA NVGPU-677
Change-Id: I7c85bf2b1b9f5a8eb09040229a1112c84713eb70
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008825
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch changes calls to nvgpu_falcon_bootstrap to handle
error codes.
JIRA NVGPU-677
Change-Id: I1d9df6053c727e7eb3d99682ff7bb06267608a54
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008797
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
The support sparse HAL severs only one purpose: return true or false
depending on whether the given chip supports sparse mappings. This
HAL is used to, in turn, program (or not) the
NVGPU_SUPPORT_SPARSE_ALLOCS enabled flag. So instead of having all
this rigmarole to program this flag just program it for all native
GPUs. Then, in the vGPU specific characteristics function disable it
explicitly. This seems to have precedent already.
JIRA NVGPU-1737
JIRA NVGPU-1934
Change-Id: I630928ad656aaffc09fdc6b7fec9fc423aa94c38
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006796
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
common/pmu/pmu.c uses IS_ENABLED() to check if perfmon sampling
should be enabled. The flag it is checking was already removed, so
the condition always evaluates to false. Remove the reference to the
removed build flag. Perfmon sampling can now be enabled only via
debugfs.
Remove the definition of IS_ENABLED() in include/nvgpu/posix/types.h.
Change-Id: I26ddd9d24c39513db68c7ae2b1cd1ebdd980e96e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011631
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Currently there are multiple BOARDOBJGRP SET/GET_STATUS construct
added to support for 3.5 pstate, _pack boardobjs & to fetch respective
offset/size of boardobjs from PMU super surface.
With super surface member descriptor(SSMD) support, boardobj offset
will be part of SSMD lookup table which is part of PMU super surface
buffer & updated by PMU RTOS during init stage,
So, making changes to use common BOARDOBJGRP SET/GET_STATUS
construct define which fetchs offset/size from SSMD,
& deleting other BOARDOBJGRP construct defines.
JIRA NVGPU-1874
Change-Id: I4e3d9ad31da33a836c5e9219321c68d867c2a172
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000860
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-SSMD - super surface member descriptor
-created new file pmu_super_sruface.c for super surface
related functions.
-Modified macros BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT and
BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT to fetch
offset/size using super surface related functions
-Moved functions nvgpu_pmu_super_surface_alloc() &
nvgpu_pmu_surface_free from pmu.c to pmu_super_sruface.c
-Created ops create_ssmd_lookup_table under pmu
to support function for chip specific
Currently, NVGPU must modify RM/PMU defined common super surface
data struct to match offset as per NVGPU super surface data struct
as NVGPU cannot include directly RM/PMU defined struct due to number
boardobjs supported by NVGPU, this adds extra work when there is
changes in boardobj or when need add support for new boardobj.
SO, to fix this issue SSMD feature is introduced.
With SSMD support, NVGPU required boardobjs offset will be part of
SSMD lookup table which is part of PMU super surface buffer & is
always first member of PMU super surface data struct for easy access,
SSMD lookup table will be copied to PMU super surface SSMD offset by
PMU RTOS ucode at init stage as per predefined SSMD lookup table.
JIRA NVGPU-1874
Change-Id: Ida1edae707ddded300f9a629710b53a6606ac0ee
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761338
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Changes:
1. Added a new type: CTRL_PERF_VFE_EQU_OUTPUT_TYPE_THRESHOLD
This parameter was added in VFE table(under index 36) of 4F VBIOS to
convert VFE floating point output into threshold percentage value for
Fmon threshold programming.
Bug 2500899
Change-Id: Ife72e9a7b644c289702b0bcc89a1c9dce9d60386
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011177
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
The function parameter of nvgpu_vm_map function is fixed for MISRA
where implicit assignment of objects to a narrower or different
essential type not allowed.This fixes few enum violations.
JIRA NVGPU-1584
Change-Id: I2353f7501c3326f792f5942b2e247badf03349cf
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1986509
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Currently, PMU f/w ucode read is part of ACR prepare ucode blob
which makes PMU to depend on ACR to init PMU f/w version related
ops & to include PMU related members to be part of ACR data struct
to free the allocated space for PMU ucodes.
Moved PMU f/w ucode read to PMU early init function & initializing
version ops once PMU ucode descriptor is available.
JIRA NVGPU-1146
Change-Id: I465814a4d7a997d06a77d8123a00f3423bf3da1e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006339
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. This is because identifier names which start with an
underscore are reserved for the C library. This patch fixes rule 21.2
issues in POSIX header guard names.
JIRA NVGPU-1028
Change-Id: I12d01c9d18b64c2a12fbd7840455d38fb024c2e8
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011873
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. This is because identifier names which start with an
underscore are reserved for the C library. This patch fixes rule 21.2
issues in vgpu header guard names.
JIRA NVGPU-1028
Change-Id: I89b450f0c1960ad93392971dcd6ef3c15d2460db
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011872
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new unit common/gr/subctx.c to manage GR subcontext
This unit provides interfaces to allocate/free/load GR subcontext
Add new header file include/nvgpu/gr/subctx.h to declare all the
interfaces.
Right now channel_gk20a structure directly includes a nvgpu_mem
for context header.
Declare a new structure nvgpu_gr_subctx for subcontext and include
this from channel_gk20a
Make all necessary changes to refer ctx_header from subctx instead
of directly referencing it from channel
Jira NVGPU-1613
Change-Id: I9eb1ee8f26fa88d2881f9b294935b65e9cbcc9b4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1990129
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
When an engine faults due to unbound instance block, all
active TSGs are currently aborted. This includes the TSG
used by vidmem-clear task to clear vidmem buffers. From
this point nvgpu_vidmem_clear cannot submit jobs anymore.
Define TSG in MM CE context as non-abortable, and skip it
when aborting active TSGs.
Bug 2486146
Change-Id: I221259aec468e8ee3a24e80fab8d8fb7ee8607b0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008954
(cherry picked from commit 6f2444dc5e128aa2b870796bd1e9dee7853f90af)
Reviewed-on: https://git-master.nvidia.com/r/2008942
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
