Commit Graph

138 Commits

Author SHA1 Message Date
Philip Elcan
acc65f6e84 gpu: nvgpu: bug: move nvgpu_do_assert_print() into assert.c
There was a header file circular dependency that was preventing
including some files. For example, for utils.h to include safe_ops.h
would include bug.h which included log.h which included bitops.h which
included utils.h. To break this loop, the macro nvgpu_do_assert_print()
into a function in a new file assert.c. With this change, log.h is no
longer required in bug.h.

This change also required adding a few includes in C files that were
picking up definitions through the chain above.

JIRA NVGPU-3868

Change-Id: Icf95677bb36e4aa034cba25594cf71f2d028c289
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168528
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2019-08-06 13:36:30 -07:00
Vedashree Vidwans
19c80f89be gpu: nvgpu; fix MISRA errors in nvgpu.common.mm
Rule 2.2 doesn't allow unused variable assignments. The reason is
presence of unused variable assignments may indicate error in program's
logic.
Rule 21.x doesn't allow reserved identifier or macro names starting with
'_' to be reused or defined.

Jira NVGPU-3864

Change-Id: I8ee31c0ee522cd4de00b317b0b4463868ac958ef
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163723
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2019-08-01 21:57:18 -07:00
Scott Long
3c7cf8b75a gpu: nvgpu: fix MISRA 10.5 issue in timeout code
This change switches nvgpu_timeout_peek_expired() to return a bool
instead of an int to remove advisory rule MISRA 10.5 violations.

MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.

JIRA NVGPU-3798

Change-Id: I5cf9badaf07493e11a639e47ae4cf221700134ff
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155617
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2019-07-24 17:04:38 -07:00
Adeel Raza
59ac65d8d7 gpu: nvgpu: rename error notifier APIs
There was a name clash between the nvgpu_set_error_notifier*() APIs and
the SET_ERROR_NOTIFIER IOCTL. Therefore, the APIs were renamed from
nvgpu_set_error_notifier*() to nvgpu_set_err_notifier*(). This rename
was done to fix MISRA 5.x errors.

JIRA NVGPU-1633

Change-Id: I06af551a664b0706f106e853f1ea8733894f11bd
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159813
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2019-07-24 15:57:07 -07:00
Scott Long
93a74d6700 gpu: nvgpu: fix MISRA 10.5 issue in syncpt code
This change switches nvgpu_nvhost_syncpt_is_expired_ext()
to return a bool instead of an int to remove advisory rule
MISRA 10.5 violations.

MISRA 10.5 states that the value of an expression should not be
cast to an inappropriate essential type.

JIRA NVGPU-3798

Change-Id: Ie0772ac7167a3c999129de0dc7f22cd96faa28fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159801
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2019-07-24 15:56:43 -07:00
Vaibhav Kachore
e8c53b4e81 Revert "Revert "gpu: nvgpu: Improve accuracy of dGPU clk measurement""
This reverts commit ffda24df36.

Bug 2637525
Bug 200530176

Change-Id: I542e51ea340f344768f9a3a090164964372fb5d2
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2148174
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2019-07-24 10:16:30 -07:00
Philip Elcan
91187b6db2 gpu: nvgpu: init: rename init functions
Rename init functions that still carry the gk20a moniker to use the more
appropriate nvgpu name instead.

JIRA NVGPU-2385

Change-Id: I5d40cd72943272c8b5f16b97d9a786d9c41496d4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156220
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2019-07-23 13:27:18 -07:00
Rajesh Devaraj
2d8791e866 gpu: nvgpu: SWUD for SDL unit
This patch adds SWUD (SW Unit Design) document for SDL unit. In addition,
it re-names err_type to err_id in error reporting APIs related to ECC, GR,
PRI and MMU, to keep the name consistent with other APIs.

JIRA NVGPU-3758

Change-Id: I968218574aa78144497fc12bd6dab20d1be7aa1c
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2151092
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2019-07-19 00:05:40 -07:00
ajesh
4249359aa9 gpu: nvgpu: fix CERTC violation in timers unit
INT31-C requires that integer conversions do not result in lost or
misinterpreted data.
Fix violation of INT31-C in timers unit.

Jira NVGPU-3605

Change-Id: Ia145e3bf814bd16d48a0f1fbbf8e62d73d08c98c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152240
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2019-07-12 11:26:12 -07:00
ajesh
b095d73022 gpu: nvgpu: modify the ffs and fls interface
Modify the ffs/fls interface function names to nvgpu_ffs and
nvgpu_fls.  The return bit values are numbered from 1 to 64.
A return value of 0 indicates an input of 0 value.

Jira NVGPU-3601

Change-Id: I1c151eeac1f94fe3b5b85bd5daf0488f75c5efa0
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146119
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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2019-07-11 05:43:55 -07:00
Nicolas Benech
2f324d5fb2 gpu: nvgpu: posix: improve SGT handling in posix-dma
This patch fixes posix-dma to properly set operations during creation
and during free it ensures that it is not freeing a NULL pointer.

JIRA NVGPU-2225

Change-Id: I0838d2faa9a05ab98d3ebd0d6af676ad1088c73d
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2145434
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-07-09 14:54:57 -07:00
Rajesh Devaraj
cd4fa084c1 gpu: nvgpu: report MMU page fault errors to 3LSS
This patch adds support to report MMU page fault errors to 3LSS.

JIRA NVGPU-3459

Change-Id: I3f06e594a75ae79bf4deef9acdc1829a002ea869
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2142742
GVS: Gerrit_Virtual_Submit
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
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2019-07-05 08:09:12 -07:00
Abdul Salam
ffda24df36 Revert "gpu: nvgpu: Improve accuracy of dGPU clk measurement"
The newly added nvgpu_current_time_ms API results in inaccurate time 
measurements sometime which causes nvgpu_dgpu_freq_test.sh to fail.

Bug 2637525
Bug 200530176

This reverts commit 318d6451e9.

Change-Id: I96279c556b3c044f590882b3bff358cfcb545ab1
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2147571
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-07-04 03:48:27 -07:00
ajesh
15afca04ba gpu: nvgpu: fix CERT C violations in bitops unit
INT30-C Requires that unsigned integer operations do not wrap.
INT31-C Requires that integer conversions do not result in lost or
misinterpreted data.
Fix the violations of above rules in bitops unit.

Jira NVGPU-3601

Change-Id: I77bc56d2dda80aa05a4665c0b5762f6ecf99ea3f
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139306
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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2019-07-03 21:45:18 -07:00
ajesh
92f42b293b gpu: nvgpu: fix MISRA violation in kmem unit
MISRA Rule 21.6 requires that the standard library input/output
functions shall not be used.
Remove the usage of snprintf function to fix the violation.
Cache name is not required in QNX build as it is not used in cache
allocation.

Jira NVGPU-3293

Change-Id: I2bd92a3ed2510a3ef8f2bdee8ad446b353baf613
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2144442
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2019-07-01 03:55:40 -07:00
Nitin Kumbhar
c69c5a7a60 gpu: nvgpu: use safe ops in ALIGN and ALIGN_MASK
Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
  throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
  used.

Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.

Also, change users of ALIGN to pass unsigned types only.

JIRA NVGPU-3515
Jira NVGPU-3411

Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-06-28 08:56:27 -07:00
ajesh
a1bbbd4cad gpu: nvgpu: fix CERT C violations in cond unit
INT31-C requires that integer conversions do not result in lost or
misinterpreted data.
INT32-C requires that operations on signed integers do not result in
overflow.
Fix the above CERT C violations in cond unit.

Jira NVGPU-3607

Change-Id: I31da5b214ee3c39799066a785b0c19f45e48c3cd
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139212
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2019-06-25 05:46:35 -07:00
Sagar Kamble
a16cc2dde3 gpu: nvgpu: compile out vidmem from safety build
Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.

JIRA NVGPU-3524

Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-06-25 04:37:08 -07:00
ajesh
fa8e1904e2 gpu: nvgpu: fix CERTC violations in timers unit
INT32-C requires that operations on signed integers do not result in
overflow.
Fix violations of INT32-C in timers unit.

Jira NVGPU-3605

Change-Id: I2d5ba6d1c2e3a84a5b3df1ecaf16cce13c1b2c97
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139971
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2019-06-21 10:26:50 -07:00
Vaibhav Kachore
318d6451e9 gpu: nvgpu: Improve accuracy of dGPU clk measurement
- This patch replaces "nvgpu_current_time_ms" with "nvgpu_hr_timestamp_us".
- "nvgpu_hr_timestamp_us" gives timestamp in microseconds and has better
accuracy than "nvgpu_current_time_ms" (which gives timestamp in millisecond)

Bug 200503143

Change-Id: I6a10e8e1b3e8ff842aa23f58bf2ba9344af232a6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125959
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2019-06-21 10:25:48 -07:00
ajesh
70d8a4555a gpu: nvgpu: fix CERTC violations in kmem unit
INT30-C Requires that unsigned integer operations do not wrap.
INT31-C Requires that integer conversions do not result in lost or
misinterpreted data.
ERR33-C Requires to detect and handle standard library errors.
Fix the above CERT C violations in kmem unit.

Jira NVGPU-3603

Change-Id: I104551406e3cf6d2da22c5b6c6edc6694992ce62
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139529
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
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2019-06-21 04:36:51 -07:00
Deepak Nibade
67350e2c9c gpu: nvgpu: add flags to debugger specific headers
Add debugger/cyclestats/fecs_trace compile time flags to debugger
specific unit headers

Jira NVGPU-3506

Change-Id: Iedea5f274243a389dce91edecbc80c58753d4805
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137253
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2019-06-18 01:38:54 -07:00
Rajesh Devaraj
ab70c2e80f gpu: nvgpu: report class/method related errors
This patch adds support to report class/method related errors to 3LSS.
Specifically, it adds the following service ID:
NVGUARD_SERVICE_IGPU_PGRAPH_SWERR_ILLEGAL_ERROR

JIRA NVGPU-3458
JIRA NVGPU-3461

Change-Id: I9b28ed3074f664254347e059ac699470f95610b3
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2136301
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Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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2019-06-18 01:37:43 -07:00
Vedashree Vidwans
6f37ac5de2 gpu: nvgpu: Disable logging for safety build
This patch adds a conditional flag to filter out logging functions from
safety release build. Logging functions are replaced with stubs.

Jira NVGPU-869

Change-Id: If898b9ce8edb260727df28b407df83f0a92f61ad
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109509
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-06-17 00:16:03 -07:00
ajesh
a6cbfca58c gpu: nvgpu: fix MISRA violations in bitops unit
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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2019-06-11 22:26:41 -07:00
Vinod G
4201f58e1e gpu: nvgpu: Add utils header for posix
Move all definitions and functions other than type defines from types.h
to new header utils.h for posix.
Update files that use functions and defintions from utils.h

DIV_ROUND_UP macro is updated to use safe_ops.h calls to handle
the CERT-C wrap issues.

Jira NVGPU-3411

Change-Id: I9da3e9f255f39949287c615519f062fd8816aa04
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130453
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-06-07 17:05:23 -07:00
ajesh
74782201ee gpu: nvgpu: fix MISRA violation in threads unit
MISRA directive 4.7 states that if a function returns error
information, then that error information shall be tested.  Fix
violation of Dir 4.7 in threads unit

Jira NVGPU-3290

Change-Id: Ibafc6f525de2c73d972ed2e60b21f44727ca5807
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126416
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-06-06 16:27:33 -07:00
Nitin Kumbhar
0fcd58b3f6 gpu: nvgpu: posix: fix ARR30 CERT C violation
Add checks for type before indexing log_types.

Error: CERT ARR30-C:
drivers/gpu/nvgpu/os/posix/log.c:63:
cert_violation: "log_types[type]" evaluates to an
address that could be at negative offset of an array.

Jira NVGPU-3560

Change-Id: I7ffe9bb2e12be6eea465618e4860697862ee1845
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122867
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-06-06 16:27:23 -07:00
Nitin Kumbhar
69331cdfb7 gpu: nvgpu: posix: fix EXP32 CERT C violation
Do not ignore volatile attribute of addr while assigning it to p.

Error: CERT EXP32-C:
drivers/gpu/nvgpu/os/posix/bitmap.c:227:
cert_violation: Access volatile variable "addr" through
 a nonvolatile reference.

Jira NVGPU-3560

Change-Id: I202b143e1818641b12f6552810953ac447348271
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-06 16:27:13 -07:00
Nitin Kumbhar
97a4a76936 gpu: nvgpu: posix: fix MEM31 CERT C violation
Fix memory leak which happens if a subsequent memory allocation fails
in the loop.

Error: CERT MEM31-C:
drivers/gpu/nvgpu/os/posix/posix-nvgpu_mem.c:146:
cert_violation: Variable "head" going out of scope leaks
 the storage it points to.

Jira NVGPU-3560

Change-Id: I82084d5402dc22c924f3864b7ddf50f03ff8a41e
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122690
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-06 16:26:58 -07:00
Thomas Fleury
97762279b7 gpu: nvgpu: make nvgpu_init_mutex return void
Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.

This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.

Jira NVGPU-3476

Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-05 10:25:52 -07:00
ajesh
a417da9094 gpu: nvgpu: move UT specific code under a define
Move all unit test specific code in bug unit under the define
__NVGPU_UNIT_TEST__.  With this change the following MISRA violations
in bug unit will be only for UT specific code,
MISRA rule 11.3
MISRA rule 21.4
MISRA rule 21.5

Jira NVGPU-3294

Change-Id: I54d3fc2bb6f1f8bc319443c522cb7036d37368e6
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129285
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-03 12:26:18 -07:00
Rajesh Devaraj
05ed37ae3a gpu: nvgpu: remove usage of hw headers from SDL
This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
    the initialization required for errors that can be injected using hw
    support, error injection function. Further, it passes the required
    information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
    nvgpu_report_ecc_err.

Jira NVGPU-3235

Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-31 04:06:51 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-30 02:18:05 -07:00
ajesh
8901faae57 gpu: nvgpu: fix MISRA violations in bitops unit
MISRA rule 21.1 states that #define and #undef shall not be used on
a reserved identifier or reserved macro name.  Fix violations of
rule 21.1 in bitops unit.
MISRA rule 21.2 states that a reserved identifier or macro name
shall not be declared.  Fix violations of rule 21.2 in bitops unit.

Jira NVGPU-3545

Change-Id: Ie551d7ce5e19287107403f2c991bcc55bd11a4e8
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125842
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-29 14:51:37 -07:00
Thomas Fleury
0a2bac5974 gpu: nvgpu: unit: add io callbacks for tegra fuses
Remove WAR to set FMODEL during gv11b_init_hal.
Instead, add io callbacks for tegra fuses, and return
GCPLEX_CONFIG_WPR_ENABLED_MASK for FUSE_GCPLEX_CONFIG_FUSE_0.

Jira NVGPU-3476

Change-Id: I0739d66668b0f5c6658346b67bc368682edda4da
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120680
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-24 19:05:47 -07:00
ajesh
779cb11b5d gpu: nvgpu: fix MISRA violations in os_sched unit
MISRA rule 21.1 forbids the use of #define and #undef on a reserved
identifier or reserved macro name.  Fix violations of rule 21.1 in
os_sched unit.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix violation of MISRA rule 21.2 in os_sched unit.

Jira NVGPU-3299

Change-Id: Ib772f60adf5e81935f9cd2044ff8f6a402e15d82
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121955
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-21 11:47:19 -07:00
Deepak Nibade
dfdd05a3d6 gpu: nvgpu: disable fecs trace support for safety builds
Compile all files with fecs trace support only if flag
NVGPU_FECS_TRACE_SUPPORT is set

remove CONFIG_GK20A_CTXSW_TRACE checks from within the files

add POSIX file for fecs trace support for compilation with
make command

Jira NVGPU-3414

Change-Id: I205e3494ce94138ab6c6fccf7fbcefc41f953c77
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-21 10:36:04 -07:00
Thomas Fleury
b528bb5ae4 gpu: nvgpu: posix: add register/unregister reg space
For some units, we want to use register spaces with
data already initialized with power-on register values.

Added the following routines:
- nvgpu_posix_io_register_reg_space
- nvgpu_posix_io_unregister_reg_space

Jira NVGPU-3476

Change-Id: Id4f5beb5e5d6b4af795e2eb58ccee13d2cfa6da5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120563
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-17 10:46:00 -07:00
Seeta Rama Raju
671cc9d785 gpu: nvgpu: MISRA 10.x fix
-- This will MISRA 10.x violations in semaphore_pool.c,
   nvgpu_mem.h, nvgpu_mem.c and posix-nvgpu_mem.c.

JIRA NVGPU-3177

Change-Id: I1db234a47c7097da28fdfd3236d9b7c5fe385d79
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119524
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 04:29:50 -07:00
Philip Elcan
1e95144194 gpu: nvgpu: Fix MISRA 21.2 violations in log.h
MISRA 21.2 prohibits naming functions with double underscore. So, rename
__nvgpu_log_dbg() and __nvgpu_log_msg() to nvgpu_log_dbg_impl() and
nvgpu_log_msg_impl(), respectively.

JIRA NVGPU-3368

Change-Id: I4548820f6772875088d095539b6da92051e08653
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118043
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 22:29:40 -07:00
Philip Elcan
5a0a711464 gpu: nvgpu: fix MISRA 21.2 violation in io.h
MISRA Rule 21.2 prohibits naming functions beginning with double
underscore. So, rename __nvgpu_readl() to nvgpu_readl_impl().

JIRA NVGPU-3361

Change-Id: Ia09a0f57e250fa3934f843671a529ee1b2ac2493
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 22:29:21 -07:00
Vinod G
7b0620501e gpu: nvgpu: Fix CERT INT31-C error on common.gr
cert_violation: Casting "-1" from "int" to "unsigned int" without checking
its value may result in lost or misinterpreted data.
Error: CERT INT31-C:

Change "(unsigned int)-1" to "~0U" in posix code.

Jira NVGPU-3411

Change-Id: I3f1fed7d0788f9ee5c4f2b3c297d7311a0bf2419
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119008
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:48:02 -07:00
Philip Elcan
e0fa45135a gpu: nvgpu: timers: fix MISRA 5.5 violation
MISRA Rule 5.5 requires identifiers be unique from macro names. The
struct timeout member max is renamed to max_attempts to fix the
violation.

JIRA NVGPU-3374

Change-Id: I701899e38a25b654d5f78feabbb273e21601f313
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118815
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 12:15:16 -07:00
Vedashree Vidwans
b4590adae4 gpu: nvgpu: fix MISRA 11.2 and 16.x in nvgpu_mem
MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.

MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.

This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.

Jira NVGPU-3339

Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-07 21:38:53 -07:00
ajesh
1639db51b2 gpu: nvgpu: fix MISRA violation in os_sched unit
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix violation of MISRA rule 21.2 in os_sched unit.

Jira NVGPU-3139

Change-Id: Ic64a2590bb180b7ae9481daca5f7720dc2dc8719
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112747
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-07 14:37:20 -07:00
ajesh
fe9f1e9e5c gpu: nvgpu: fix MISRA violations in timers unit
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix the violations of MISRA rule 21.2 in timers unit.

Jira NVGPU-3139

Change-Id: I507d0f2a51e83ce24d642dcc81975aa513fa41eb
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112599
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 12:07:16 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 02:56:53 -07:00
ajesh
e154c1c007 gpu: nvgpu: fix MISRA violations in bug unit
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix the violations of MISRA rule 21.2 in bug unit.

Jira NVGPU-3139

Change-Id: I2670f3745d09069a4d36beec4291c795a08f1c49
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111058
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-03 13:08:30 -07:00
ajesh
cfb17a1f9a gpu: nvgpu: fix MISRA violations in kmem unit
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.  Fix the violations of MISRA rule 21.2 in kmem unit.

Jira NVGPU-3139

Change-Id: I20f80e8bcdc8f802bd9aea34bbf050cafdfbd72e
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110524
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-03 13:08:00 -07:00