Commit Graph

8961 Commits

Author SHA1 Message Date
Debarshi Dutta
1b3ae7eb92 gpu: nvgpu: fix ecc issues
Fixed memory leaks within the ltc ecc code.
Memory leak occurs as some of the stats are not free'd
during Rmmod. Add a common API to handle the same.

Bug 3364181

Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Change-Id: I1ec5a7d7e57580bc75b7679c922d1e3af8418f6b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2652684
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-27 07:50:52 -08:00
Rajesh Devaraj
878235e914 gpu: nvgpu: remove report error callback
In DRIVE 6.0, NvGPU needs to support error reporting in QNX-Safety,
QNX-Standard, and Linux. To support error reporting in all these
platform variants, SDL unit will be moved from QNX to common code.
As part of this refactoring activity, this patch removes ops assignment
for report error. Also, it removes API calls that are used to take
time-stamp for stall interrupt thread. This time-stamp APIs will be
brought back later, if required to support periodic diagnostics.

JIRA NVGPU-7353

Change-Id: I38536019dc7165e6a97674863b37d009854af948
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2655958
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-24 02:06:24 -08:00
Tejal Kudav
4f41ce7696 gpu: nvgpu: Disable frequency scaling for AV+L
NVGPU does not support frequency scaling on hypervisor
based embedded environments.Disable frequency scaling on AV+L
using the nvgpu_is_hypervisor_mode().

JIRA NVGPU-7283

Change-Id: If8fbcc0c5e2f11b9e8895825bb3b3022e7bd3005
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2654969
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kasinadha Dendukuri <kdendukuri@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-17 05:37:23 -08:00
Antony Clince Alex
6bfa11c327 gpu: nvgpu: ga10b: update regops allowlist
Update regops allowlist using the latest hw headers.

Bug 3455929
Jira NVGPU-7365

Change-Id: I4f866b81de2a7d689f1b633a498a8c0c9a26a226
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2651169
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-17 05:35:57 -08:00
Chris Johnson
c78998f99b gpu: nvgpu: leave LTC evicted_cb intr disabled
The evicted_cb interrupt is occurring more frequently than
expected and has no SW action that can be taken to avoid it.

This interrupt is being disabled which is consistent with
the HW POR value and the setting used on previous chips.

Bug 3464717

Signed-off-by: Chris Johnson <cwj@nvidia.com>
Change-Id: Ibc87f4bf287eeef158e46126a5e7f8a3cc575390
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2654678
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-16 23:13:31 -08:00
Sagar Kamble
8834d598e4 gpu: nvgpu: fix CONFIG_NVGPU_NVMAP_NEXT definition
CONFIG_NVGPU_NVMAP_NEXT was defined for all kernels except 4.9. However,
Android builds nvgpu without NV_BUILD_KERNEL_OPTIONS set and it fails
while looking for definitions of the functions nvmap_dma_alloc_attrs
and nvmap_dma_free_attrs.

Define it for kstable if CONFIG_TEGRA_NVMAP_NEXT is set and define it
for kernel 5.10 (downstream) explicitly.

Bug 3445216

Change-Id: If73ca56cfc5668d6e318f470b31d999d663a4483
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2654677
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Kevin Kuo (SW-GPU) <kevkuo@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-16 12:46:19 -08:00
Seshendra Gadagottu
6935867a5e Revert "gpu: nvgpu: t234: update gating registers to avoid priv errors"
This reverts commit 319f4f6fe1.

Reason for revert: <priv errors are fixed by lowering PLM mask for
ltc registers NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK and
NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK in acr-firmware>

Bug 3469873
Bug 3423549
Bug 3452217

Change-Id: I1237f65bfeab07d2287465b40798043d9edb209a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-15 06:08:26 -08:00
Seshendra Gadagottu
a7c1052024 gpu: nvgpu: program ltc cg prod values after acr boot
Separate nvgpu_cg_blcg/slcg_fb_ltc_load_enable function
into nvgpu_cg_blcg/slcg_fb_load_enable and
nvgpu_cg_blcg/slcg_ltc_load_enable.

Program fb slcg/blcg prod values during fb init and
program ltc slcg/blcg prod values after acr boot to
have correct privilege for ltc cg programming.

Update unit tests to have sperate blcg/slcg hal for
fb and ltc programming.

Bug 3423549

Change-Id: Icdb45528abe1a3ab68a47f689310dee9a4fe9366
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2646039
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-15 06:08:21 -08:00
mpoojary
4e98b53944 gpu: nvgpu: ga10b: Update ga10b_is_pmu_supported
Update ga10b_is_pmu_supported function to add support
for pre-si platforms along with silicon.

JIRA NVGPU-4701

Change-Id: If7eec7753c01135c9c9c20d49278b3f1fe9332ae
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2652871
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-13 19:30:46 -08:00
Richard Zhao
09cf3642ef gpu: nvgpu: add more compile flags to posix iGPU
Added bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Also fixed all of compile errors for posix.

It's preparing for porting gpu server.

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I30b09a62a57396abd642922e22f2e550a96f42c2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555059
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:36:31 -08:00
Richard Zhao
9e5c88c1ef gpu: nvgpu: include: fix compile error of new compile flags
It's preparing to add bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I7a7afff85231aed52a20f77854c30fe5c755cae5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555058
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:36:26 -08:00
Richard Zhao
e81a36e56a gpu: nvgpu: hal: fix compile error of new compile flags
It's preparing to add bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia16ef186da1e97badff9dd0bf8cbd6700dd77b15
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555057
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:36:19 -08:00
Richard Zhao
9ab1271269 gpu: nvgpu: common: fix compile error of new compile flags
It's preparing to add bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia8f508c65071aa4775d71b8ee5dbf88a33b5cbd5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555056
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-13 12:36:14 -08:00
Richard Zhao
851666b632 gpu: nvgpu: common/pmu: fix compile error of new compile flags
It's preparing to add bellow CFLAGS:
    -Werror -Wall -Wextra \
    -Wmissing-braces -Wpointer-arith -Wundef \
    -Wconversion -Wsign-conversion \
    -Wformat-security \
    -Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough

Jira GVSCI-11640

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ide3ab484924bd5be976a9f335b55b136575ce428
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2555055
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:36:02 -08:00
Sagar Kadamati
a3ed73a57c gpu: nvgpu: add tegra_raw support
* This change adds NVGPU_AS_MAP_BUFFER_FLAGS_TEGRA_RAW flag
   to control buffer format
 * Add NVGPU_SUPPORT_TEGRA_RAW enabled flag to indicate if feature
   is enabled for a given chip.
 * Update gv11b_gpu_phys_addr function to set TEGRA_RAW bit

Jira NVGPU-6640
Bug 3489827

Change-Id: I959c22bef906bb9c6dcdc8d5f5e9951ad9937a60
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2545128
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 12:35:36 -08:00
Seshendra Gadagottu
03b1a81ab1 gpu: nvgpu: gr: ignore second zcull request to ctx
All channels in TSG will share same zcull context. Any
attempt to add a second zcull buffer will be ignored.

Bug 3364302

Change-Id: I04e18dfe8e5fac4ca131c3b625755aa90a23180d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2616677
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-13 10:30:23 -08:00
Debarshi Dutta
1c053a75af gpu: nvgpu: remove unnecessary warning.
Here, the freq_counter is set to track the count of number of
frequencies enumerated and capped by GP10B_MAX_SUPPORTED_FREQS.
There is an early terminating condition when new_rate equals max_rate.

The line following this is set to
WARN_ON(freq_counter == GP10B_MAX_SUPPORTED_FREQS);

This line is probably incorrect and contradicts the above loop as in
there is definite probability of freq_counter equaling
GP10B_MAX_SUPPORTED_FREQS. Probably the original intention might have
been to catch an off-by-1 error where freq_counter equals
GP10B_MAX_SUPPORTED_FREQS + 1.

Even then instead of printing a warning message, a better idea is to
handle the possible bug in the code itself.

Bug 3407276

Change-Id: I7f2a9d5c41be62227d08045e959e16c4228fbff4
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2623380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-12 07:40:37 -08:00
Ashish Mhetre
38901413f9 gpu: nvgpu: use nvmap exported APIs from K5.10 onwards
All the VPR related code has been removed from core kernel from K5.10
onwards. So make use of NvMap exported APIs for handling of VPR carveout
from K5.10 onwards.

Use those exported APIs in nvgpu when CONFIG_NVGPU_NVMAP_NEXT is
defined. This config will be defined on K5.10 onwards.

Bug 3415117

Change-Id: I7be68a3a60a8b7811a7233681421f85395a81e2b
Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2650509
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-07 15:57:49 -08:00
Deepak Nibade
7f839d6098 gpu: nvgpu: take power refcount for pma stream update get/put IOCTL
Add gk20a_busy()/idle() protection for pma stream update get/put IOCTL
NVGPU_PROFILER_IOCTL_PMA_STREAM_UPDATE_GET_PUT

Bug 2510974

Change-Id: Iade198f68e72f6fbc49be8ee55e4b44a4c332451
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2650588
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-07 06:30:24 -08:00
Sagar Kamble
535a27411a gpu: nvgpu: fix allocator debugfs deinit
Allocator (bitmap, buddy, page) debugfs files are not cleaned up when
the allocators are destroyed. This leads to warning logs from nvgpu
like below:

[21073.493000] debugfs: File 'gk20a_as_17' in directory 'allocators' already present!
[21073.493026] debugfs: File 'gk20a_as_17-sys' in directory 'allocators' already present!

Remove the per-allocator debugfs node when destroying an allocator in
runtime.

While at this, add missing nvgpu_allocator locking to the function
nvgpu_bitmap_alloc_destroy. And create nop functions for the
functions nvgpu_init_alloc_debug and nvgpu_fini_alloc_debug
when CONFIG_DEBUG_FS is not defined to avoid adding the
CONFIG checks at multiple places.

Move gk20a_debug_deinit to the end of gk20a_free_cb called in nvgpu_put
as that tears down all debugfs entries. Allocator destroy happens as
part of nvgpu_put call and it can lead to invalid debugfs dentry
access if gk20a_debug_deinit is called before it.

Bug 3481097

Change-Id: I8a66bcf6ade7e5707f9207c78a54d12d7bd94c02
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2648012
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-07 06:28:53 -08:00
mkumbar
2431b832e7 gpu: nvgpu: CONFIG_NVGPU_NON_FUSA cleanup for ga10b acr
some part of ga10b acr blob creation code under CONFIG_NVGPU_NON_FUSA
check which fails to create blob correctly for ga10b safety build.

Bug 3456240

Change-Id: If246e2142daa8dac28ac9ce35f4562119a3b30aa
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645647
(cherry picked from commit 4c52b59820804ed630836fbef9cf3e7e1a18a013)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2642679
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Shashank Singh <shashsingh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-06 17:19:54 -08:00
mkumbar
61c6aeec41 gpu: nvgpu: disable LSPMU for ga10b safety
Bug 3456240

Change-Id: I0bb9581d2df46e5cb2dea57794ee0c918394eb66
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645646
(cherry picked from commit aab86a06485c94546e11809cdeeefe9906e9b680)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2629878
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Shashank Singh <shashsingh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-06 17:19:46 -08:00
Shashank Singh
a372ec9a38 gpu: nvgpu: disable golden context image verification
- Disable golden context image verification until ctxsw fw for orin
safety is ready for this feature.
- Make NULL check for hal set_default_compute_regs else it causes crash
for orin safety.

Bug 3456240

Change-Id: I1f6ca9d78f22cc6776bb0b3a9e05f22171095c7f
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645666
(cherry picked from commit 3907d1b315e1247243632fefdcbce69d58090681)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2644533
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-01-06 11:40:46 -08:00
Sagar Kamble
4e227b3e80 gpu: nvgpu: use nvmap exported APIs for dma_alloc|free_attrs on kstable
To support nvmap as OOT module in kstable it implemented the APIs
nvmap_dma_alloc_attrs and nvmap_dma_free_attrs to replace usage
of kernel dma_alloc_attrs and dma_free_attrs. nvmap APIs have
special handling for VPR carveout.

Use those exported APIs in nvgpu when CONFIG_NVGPU_NVMAP_NEXT is
defined. This config will be defined only for kstable builds.

JIRA LS-458
Bug 200754700

Change-Id: I717aa579d29ee10c006b044f6b0fafbedc57dba8
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2647951
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-05 20:57:40 -08:00
Sagar Kamble
a2f4fdf190 gpu: nvgpu: enable CONFIG_NVGPU_VPR for all kernels
VPR functionality is split up as static VPR and VPR resize. Static VPR
is supported on all kernels. VPR resize is enabled only on 4.9 kernel.

Enable CONFIG_NVGPU_VPR unconditionally in Linux Makefile. Compile
VPR resize related functionality in nvgpu under the check for
Linux kernel version using new define NVGPU_VPR_RESIZE_SUPPORTED.

JIRA LS-458
Bug 200754700

Change-Id: Ib92f7f1b95afc6c69fbdf33354459c147337350c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2647619
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-05 20:57:32 -08:00
Dinesh T
a47ce8eafe gpu: nvgpu: add ipa-pa cache for qnx
This is adding ipa-pa cache for HV-qnx by making the code
as OS independant.

NVGPU-7329

Change-Id: If003ddf323124ba0899d7ead5db5c5478ddfc6e0
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2645771
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-31 05:04:50 -08:00
Sagar Kamble
d424598b7b gpu: nvgpu: stop nvs thread during unload
nvs worker thread is created on each resume and deinitialized on every
suspend. nvgpu can be resumed when process is getting killed. Thread
creation can fail when the process is getting killed. That will lead
to driver resume failure.

To avoid the issue above, don't stop the nvs worker thread in suspend
and let the first created thread handle the nvs work always.
Deinitialize the nvs worker thread during nvgpu unload.

Also, log the error returned by nvgpu_thread_create in the function
nvgpu_worker_start.

bug 3480192

Change-Id: I8d5d9e7716a950b162cc3c2d9fcfde07c4edfcf6
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2646218
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-29 09:35:03 -08:00
Deepak Nibade
4fd0f11e9c gpu: nvgpu: define gops.gr.init.set_default_compute_regs for Orin safety
gops.gr.init.set_default_compute_regs() HAL configures compute specific
settings in safety build and this eliminates need of using SW methods.

Define this HAL for Orin safety build and configure sked check related
registers from the HAL. Other settings done on gv11b are no more
applicable for ga10b safety.

Bug 3456240

Change-Id: Ic125cdf414a5402511949015e3424b8cb2dab1e0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2646284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-23 13:14:58 -08:00
Martin Radev
b67a3cd053 gpu: nvgpu: ga10b: Correct VAB implementation
This patch performs the following improvements for VAB:
1) It avoids an infinite loop when collecting VAB information.
   Previously, nvgpu incorrectly assumed that the valid bit would
   be eventually set for the checker when polling. It may not be set
   if a VAB-related fault has occurred.
2) It handles the VAB_ERROR mmu fault which may be caused for various
   reasons: invalid vab buffer address, tracking in protected mode,
   etc. The recovery sequence is to set the vab buffer size to 0 and
   then to the original size. This clears the VAB_ERROR bit. After
   reseting, the old register values are again set in the recovery
   code sequence.
3) Use correct number of VAB buffers. There's only one VAB buffer on
   ga10b, not two.
4) Simplify logic.

Bug 3374805
Bug 3465734
Bug 3473147

Change-Id: I716f460ef37cb848ddc56a64c6f83024c4bb9811
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621290
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-22 08:22:13 -08:00
Seshendra Gadagottu
b2db6a8453 gpu: nvgpu: ga10b: set-up vab buffer during gpu re-init
During gpu re-initialization(rail gate exit/sc7 exit), vab buffers
needs to programmed in hw by writing vab buffer address to
NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_LO(HI)_ADDR and
setting vab entries to NV_PFB_PRI_MMU_VIDMEM_ACCESS_BIT_BUFFER_SIZE_VAL.

For this moved nvgpu nvgpu_fb_vab_init_hal from
nvgpu_init_mm_setup_sw to nvgpu_init_mm_support.
nvgpu_init_mm_setup_sw is skipping during re-init, because
sw_ready is set during first boot.

Bug 3468562

Change-Id: Iee2bd4bc5165397ea4f9cca0ba6744eaf361a342
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2643244
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Martin Radev <mradev@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-21 17:15:23 -08:00
Divya
744782e088 gpu: nvgpu: add IDLE_SNAP RPC
Add support for IDLE_SNAP RPC sent from PMU.
This RPC event is received when ELPG is engaged and
some register, which lies in powergated region, is
accessed for read/write.
This RPC sends information like reason for idle_snap and
cached value of idle status registers.

JIRA NVGPU-7327

Change-Id: I289505c43f0d4246ee1379804b575cd8902050d3
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2642951
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-21 17:14:42 -08:00
shashank singh
c22ff25097 gpu: nvgpu: move GSPLITE outside DGPU flag
Jira NVGPU-7276

Change-Id: Ic69443f66f42ab5e981ce865c24fcca63f783a76
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632687
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-21 17:09:45 -08:00
Seshendra Gadagottu
820d2b4a2d gpu: nvgpu: keep gpu busy during vab reserve/flush ioctls
VAB IOCTL for reserve and flush can take more than railgate_delay(500msec).
To avoid gpu entering into railgate, set gpu busy hint during entry and set to
idle at the end of ioctl.

Bug 3468562

Change-Id: I9219e65004ad42028062ce09a315d9fde029a86c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2643418
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-21 12:20:48 -08:00
Ninad Malwade
54adf26042 nvgpu: set tpc_pg_mask only if it's changed
Set tpc_pg_mask only if it's different from the one which is set
earlier.

Bug 3463659

Change-Id: I8388e10ac0adcd56cf310c491c870614419bd18d
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2641763
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-21 12:18:14 -08:00
Shashank Singh
41c0df629b gpu: nvgpu: enable intr_get_unit_info hal for safety orin
Bug 3456240

Change-Id: Id2f0b8f4954669b063135666613f0ffc7891ec04
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2642611
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-18 02:51:44 -08:00
Seema Khowala
38010b612a Revert "gpu: nvgpu: ga10b: disable ELPG"
This reverts commit 09c0813c94.

Reason for revert: Enable ELPG

Bug 3430273
Bug 3439350

Change-Id: I6f1143c514e521ab0681e6659c55604161a19539
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2638370
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-18 02:50:42 -08:00
Sagar Kamble
da3c83cd5e gpu: nvgpu: update doxygen for common.ltc unit
Update the documentation as per SWUD feedback for common.ltc unit.

JIRA NVGPU-6982

Change-Id: I0a8406791bef2094bcd2804546db46378a269bb3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2608663
(cherry picked from commit dd1198870b4dbef5d4731fd5d292188c268967b6)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2633960
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-17 14:36:57 -08:00
Sagar Kamble
6a6562cd4d gpu: nvgpu: ga10x: fix LTC ecc handling
Notable differences from GV11B are below:
  1. RSTG/TSTG uncorrected errors are supported.
  2. PLTS_INTR doesn't report SEC/DED errors. Instead, PLTS_INTR3 will
     indicate the SEC/DED errors through CORRECTED_ERR_DSTG and
     UNCORRECTED_ERR_DSTG fields respectively.
  3. DSTG_ECC_ADDRESS and DSTG_ECC_REPORT are deprecated.

Bug 3446731

Change-Id: I60018d1b3825adcbb287dea05bc96a87f559c969
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2633959
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-17 14:36:51 -08:00
Sagar Kamble
c463810bcd gpu: nvgpu: fix ltc isr, unit tests
LTC isr doesn't handle ECC errors correctly. INTR3 reports only
parity ECC errors and INTR reports SEC/DED ECC errors. nvgpu
managed both these errors with same counters. Fix it as per
Volta ECC HW Functional Description.

JIRA NVGPU-6982

Change-Id: I6ddaab55f7e1354ad9b832672a9006b7e58df9f7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2605012
(cherry picked from commit 5f92651e921b17cb61bbbb8954128c787cd89238)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632548
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-17 14:36:45 -08:00
Sagar Kamble
449a4823d4 gpu: nvgpu: compile out non fusa LTC functionality
nvgpu_ltc_sync_enabled functionality is used only in the kernel mode
submit path and for debugging. en_illegal_compstat functionality is
used for debugging .

Compile them out under CONFIG_NVGPU_NON_FUSA.

JIRA NVGPU-6982

Change-Id: I404d4b74b2e60ba4c2173ba0bfb643b1ecb6ba7c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2605011
(cherry picked from commit f4bcafe73c8f7184b5e125e3ff6e55ceccaf87eb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-17 14:36:40 -08:00
Sagar Kamble
2c560dce0e gpu: nvgpu: ga10x: add missing LTC ECC related registers and fields
1. Registers NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT and
   NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS are
   deprecated. Remove them.
2. Define NV_PLTCG_LTC0_LTS0_INTR3 for ga100.
3. Add fields and constants for the register
   NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS.
4. Add new fields for the register
   NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL.

Bug 3446731

Change-Id: I3e41198b7b2e75ff69b5c6193e6fd54efae15752
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2633958
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-17 14:36:34 -08:00
mkumbar
4d1fa62dd9 gpu: nvgpu: ga10b: RPC for ELPG statistics data
Fetch the ELPG statistics data using RPC
NV_PMU_RPC_ID_PG_PG_CTRL_STATS_GET

Earlier/legacy chips, ELPG stats data is fetched
from DMEM directly using the offset got from pg init
command but for GA10B RPC is used to fetch the ELPG
stats data.

Bug 3439350

Change-Id: Ia29d423c41913cd96e44aba9dae41f73fe236dd2
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2641832
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-15 08:13:24 -08:00
Konsta Hölttä
55afe1ff4c gpu: nvgpu: improve nvs uapi
- Make the domain scheduler timeslice type nanoseconds to future proof
  the interface
- Return -ENOSYS from ioctls if the nvs code is not initialized
- Return the number of domains also when user supplied array is present
- Use domain id instead of name for TSG binding
- Improve documentation in the uapi headers
- Verify that reserved fields are zeroed
- Extend some internal logging
- Release the sched mutex on alloc error
- Add file mode checks in the nvs ioctls. The create and remove ioctls
  require writable file permissions, while the query does not; this
  allows filesystem based access control on domain management on the
  single dev node.

Jira NVGPU-6788

Change-Id: I668eb5972a0ed1073e84a4ae30e3069bf0b59e16
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2639017
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-15 06:05:25 -08:00
mkumbar
b92e8530fc gpu: nvgpu: ga10b: slcg and blcg update for PMU
Load register configuration for SLCG and BLCG for PMU.

Bug 3452217

Change-Id: Ib54077ee00d0b9247db8d792e5ed566fd4ca2efd
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2641365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-14 06:28:19 -08:00
Konsta Hölttä
d086c678fd gpu: nvgpu: add domain scheduler worker
Move away from the prototype call in channel wdt worker and create a
separate worker thread for the domain scheduler. The details of runlist
domains are still encapsulated in the runlist code; the domain scheduler
controls when to switch domains. Switching happens based on domain
timeslices or when the current domain is deleted.

The worker thread is paused on railgate and spun back on poweron. The
scheduler data was also left dangling, so fix that by deinitializing all
nvs-related when gk20a_remove_support() is called. The runlist domains
already get freed as part of fifo removal.

Jira NVGPU-6427

Change-Id: I64f42498f8789448d9becdd209b7878ef0fdb124
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632579
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-12-14 06:26:16 -08:00
Deepak Nibade
8ce1f48e2e gpu: nvgpu: update doxygen for nvgpu_gr_config_init
Update doxygen for function nvgpu_gr_config_init() and add reasons on
why GR engine configuration initialization could fail.

Bug 3465555
Jira PLCF-2832

Change-Id: Idcb54883c8d086ff8173cae651d8072b4dcd4625
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2640082
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-13 17:59:09 -08:00
Divya
9446cfa320 gpu: nvgpu: update golden image flag for RG seq
The flag pmu->pg->golden_image_initialized is set to
true during initial GPU context creation and is not
cleared while the GPU goes into pm_suspend (during railgate).
Hence, when the GPU resumes after un-railgate it retains
the previous value which can cause ELPG to kick in immediately.
Due to this, when ELPG and Railgating are enabled, IDLE_SNAP
is seen for read access of gr_gpc0_tpc0_sm_arch_r reg.

To resolve this, if golden image is ready set the
pmu->pg->golden_image_initialized to suspend state during railgate,
to delay the early enable of ELPG. Add a new
pmu_init_golden_img_state hal in the NVGPU_INIT_TABLE_ENTRY.
This will be called after all the GR access is done and GPU resumes
completely after un-railgate. This hal will then check if
golden_image_initialized flag is in suspend state, it will set it
to ready state and then re-enable ELPG.

Bug 3431798

Change-Id: I1fee83e66e09b6b78d385bbe60529d0724f79e79
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2639188
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-11 14:06:49 -08:00
Konsta Hölttä
ae166bba8a gpu: nvgpu: posix: print WARN*() location
WARN() and WARN_ON() are most useful when the log explains where they
happened. The posix implementation of these prints neither that nor the
warning message (if any). Extend the macros to include function name and
line number, and print those plus the format string.

Actually formatting the format string is problematic wrt. MISRA rules,
so the arguments are not formatted.

The implementation of BUG() already prints the function name and line
number.

Change-Id: Ie246a915f5e8420e1c606bb1555a7f9b498725fd
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2634105
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-11 14:05:16 -08:00
Divya
4c2e2bb0b9 gpu: nvgpu: Reduce allow/disallow in stall_isr
With the existing implemenatation ELPG was disabled and
enabled once for handling stall isr and then again ELPG is
disabled and aenabled for writing to gr retrigger register.
This increased number of ELPG cycles and degraded perf of various
graphics test with ELPG enabled.

This change now disables ELPG, then handles stall_isr and
write to gr retrigger register and then enables ELPG.
Thus, number of ELPG cycles are reduced.

Bug 3451615

Change-Id: Iadac0c7b01eb711878280cd1503ba0f26000937c
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2638175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-10 13:27:16 -08:00
Konsta Hölttä
ffb7e1f5ec gpu: nvgpu: fix power races in gsp test
The GSP stress test debug node only checks for gpu poweron and continues
to trigger the stress test if power is on. This results in a small
window where the GPU might get railgated, so call gk20a_busy() to hold a
power ref while loading or starting the stress test (which touches HW).

Change-Id: I2ced45472cd0602da36f1801e56b486097ece83d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2635604
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-12-10 13:25:05 -08:00