Commit Graph

20 Commits

Author SHA1 Message Date
Sagar Kamble
ba5d129cfc gpu: nvgpu: address CCM for nvgpu_cg_init_gr_load_gating_prod
Reduced TCC/MCC below 10 by splitting into BLCG and SLPC load gating
prod functions.

JIRA NVGPU-4101

Change-Id: Ic572e1fe4dd6a3a1edf13d77ddadf08ea2214f74
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205216
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:05:52 -06:00
Sagar Kamble
cd8f8beccd gpu: nvgpu: remove CAN_SLCG|BLCG|ELCG checks
NVGPU_GPU_CAN_SLCG|BLCG checks are done in cg/therm hal functions.
Remove them from common functions.

JIRA NVGPU-2175

Change-Id: Ie3a99c5c1a5eeb71ad4ae344ca42d63d6fac9ecf
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2191540
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2020-12-15 14:05:52 -06:00
Sagar Kamble
3444d729fd gpu: nvgpu: update compiling out cg changes
nvgpu_cg_pg_enable|disable functions are non-safe hence compile out
power_features.c. Corresponding functions from cg.c are also not
compiled. for e.g. nvgpu_cg_elcg_enable|disable, nvgpu_cg_blcg-
_mode_enable|disable, nvgpu_cg_slcg_gr_perf_ltc_load_enable|disable,
nvgpu_cg_elcg_set_elcg|blcg|slcg_enabled.
BLCG handling in nvgpu_cg_set_mode is non-safe hence compile it out
as well.

JIRA NVGPU-2175

Change-Id: I9940cc418d84eb30979dd50a2ed4a132473312fe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168957
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2020-12-15 14:05:52 -06:00
Deepak Nibade
e34b6f76d3 gpu: nvgpu: add clock gating support for HSHUB
Add BLCG and SLCG clock gating support for HSHUB unit on gv11b and tu104

Register list for BLCG and SLCG is auto generated with scripts.
Add HAL operations to enable/disable HSHUB clock gating

Re-generate gv11b reglist so that all the manually commented registers
are automatically deleted. Some of the unicast registers are also
deleted. We already have corresponding broadcast registers present.

Bug 2526212

Change-Id: I2654f158daa802bcf992e103ed4a44675aa5fd4d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2150199
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2019-07-12 13:35:04 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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2019-06-06 06:55:58 -07:00
Seema Khowala
a72bfa63b2 gpu: nvgpu: Add NVGPU_FEATURE_POWER_PG compiler flag
This flag is added to compile out below features from
safety build
-elpg

JIRA NVGPU-3425

Change-Id: I439edb444a4ebe1732a379aecbb0ffc8b48eb97c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127449
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2019-06-04 12:05:49 -07:00
Mahantesh Kumbar
90aee0086f gpu: nvgpu: rename NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0

JIRA NVGPU-3418

Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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2019-05-30 19:27:14 -07:00
Mahantesh Kumbar
b6dfba15fa gpu: nvgpu: Compile out PMU PG/LSFM code for safety
Compile out PMU PG & LSFM calls called from other unit when PMU RTOS
support is disabled for safety build by setting NVGPU_LS_PMU build
flag to 0

NVGPU JIRA-3418

Change-Id: I6a5089b37344697ffb0cc9ad301f4e7cf03f9f55
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117770
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-05-30 19:25:32 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-05-23 00:56:45 -07:00
Seema Khowala
defc27ac9b gpu: nvgpu: cg fix MISRA violations
Fix Rule 10.1

Rename gk20a_readl and gk20a_writel
Moved ELCG_* and BLCG_* defines from gk20a.h to cg.h
Cleaned up checkpatch errors

JIRA NVGPU-3424

Change-Id: I8d7de11dd7beb22c0fe44ff770af3b2609434385
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115908
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2019-05-10 11:42:52 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-05-03 16:25:43 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
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2019-05-02 23:40:42 -07:00
Seema Khowala
296ff58eb1 gpu: nvgpu: move engine related struct
Move from fifo_gk20a.h to engines.h
fifo_pbdma_exception_info_gk20a
fifo_engine_exception_info_gk20a
fifo_engine_info_gk20a

Rename
fifo_pbdma_exception_info_gk20a -> nvgpu_pbdma_exception_info
fifo_engine_exception_info_gk20a -> nvgpu_engine_exception_info
fifo_engine_info_gk20a -> nvgpu_engine_info
NVGPU_ENGINE_GR_GK20A -> NVGPU_ENGINE_GR
NVGPU_ENGINE_GRCE_GK20A -> NVGPU_ENGINE_GRCE
NVGPU_ENGINE_ASYNC_CE_GK20A -> NVGPU_ENGINE_ASYNC_CE
NVGPU_ENGINE_INVAL_GK20A -> NVGPU_ENGINE_INVAL

JIRA NVGPU-2012

Change-Id: I665487721608ff9eacbdebff17d9dbef653de55e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109009
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2019-05-02 23:39:59 -07:00
Vinod G
f7d7aabe8e gpu: nvgpu: gr_gk20a header cleanup
Move NVGPU_EVENT_ID enum from gr_gk20a.h to gk20a.h
as enum nvgpu_event_id_type. Update the function using the
NVGPU_EVENT_ID enum.

Move enum used only in cg.c from gr_gk20a.h

JIRA NVGPU-3132

Change-Id: Idd80e519d1e30f49528cdfbfc2085ebc81330c86
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102834
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2019-04-23 15:44:02 -07:00
Vinod G
1819c36562 gpu: nvgpu: move nvgpu_gr_wait_initialized to hal
Move nvgpu_gr_wait_initialized to a gr.init hal function.
Move to hal function to avoid circular dependencies of headers.

Update nvgpu_gr_wait_initialized call to
g->ops.gr.init.wait_initialized

JIRA NVGPU-3016

Change-Id: Ia2e5f78da8528c76a8d08512151483579f250676
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085740
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2019-04-02 04:46:55 -07:00
Vinod G
bf485dc68b gpu: nvgpu: move gk20a_gr_wait_initialized call
Move gk20a_gr_wait_initialized function to common.gr.init as
nvgpu_gr_wait_initialized function. Update all the files calling
this function.

JIRA NVGPU-1885

Change-Id: Ic75d3736d9b07a32c2bd07a5d576467352ab93cf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082946
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2019-03-27 18:36:12 -07:00
Seema Khowala
b650c773ac gpu: nvgpu: rename clock_gating ops to cg
Rename clock_gating ops to cg

JIRA NVGPU-2014

Change-Id: Iae3c5739c1dcecb1fa8364a509b646162b43d2a2
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082270
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2019-03-27 13:44:58 -07:00
Seema Khowala
7e2f124fd1 gpu: nvgpu: wait for gr.initialized before changing cg/pg
set gr.initialized to false in the beginning of gk20a_gr_reset() and
set it to true at the end of successful execution of gk20a_gr_reset.

Use gk20a_gr_wait_initialized() to enable/disable cg/pg
functions to make sure engine is out of reset and initialized.

Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287

Change-Id: Ic7b0b71382c6d852a625c603dad8609c43b7f20f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030827
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2019-03-13 06:34:17 -07:00
Seema Khowala
c905858565 gpu: nvgpu: add cg and pg function
Add new power/clock gating functions that can be called by
other units.

New clock_gating functions will reside in cg.c under
common/power_features/cg unit.

New power gating functions will reside in pg.c under
common/power_features/pg unit.

Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.

Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.

JIRA NVGPU-2014

Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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2019-03-08 16:24:35 -08:00