Unset get_phys_addr_bits as PCIe devices do not need
to care if SMMU is enabled or not.
Jira VFND-1965
Change-Id: Ice87ff06087ec6c0a123dcf054717eff80acc8f9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1183085
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
In addition to nonwpr_base address, allocate also the wpr_base that is
configured as wpr, in order to not overlap user allocations on that
area.
Jira DNVGPU-18
Change-Id: Ie2976a091e8084fcdc8ffd9fb4b6c75411450acb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1182874
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Add the read_ptimer hook for GP106. This makes NVGPU_GPU_IOCTL_GET_GPU_TIME
not crash on call.
Bug 1787348
Change-Id: I31d7c30bcf0d6ad7fdecccd25a7c9c16276632a2
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1179661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
For devices that have vidmem available, use the vidmem allocator in
gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem.
Because all of the buffers haven't been tested to work in vidmem yet,
rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at
the end to declare explicitly that vidmem is used. Enabling vidmem for
each now is a matter of removing "_sys" from the function call.
Jira DNVGPU-18
Change-Id: I4a67eae403f1d9d271118c35e3775b1129170676
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1176806
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
nvgpu/gp106/pmu_gp106.c:30:5: warning: symbol
'gp106_pmu_enable_hw' was not declared. Should it be static?
nvgpu/gp106/pmu_gp106.c:118:5: warning: symbol
'gp106_pmu_reset' was not declared. Should it be static?
nvgpu/gp106/pmu_gp106.c:146:5: warning: symbol
'gp106_sec2_reset' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:79:6: warning: symbol
'gp106_wpr_info' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:92:5: warning: symbol
'gp106_alloc_blob_space' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:120:5: warning: symbol
'pmu_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:187:5: warning: symbol
'fecs_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:265:5: warning: symbol
'gpccs_ucode_details' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:348:5: warning: symbol
'gp106_prepare_ucode_blob' was not declared. Should it be static?
nvgpu/gp106/acr_gp106.c:1011:5: warning: symbol
'gp106_bootstrap_hs_flcn' was not declared. Should it be static?
Bug 200088648
Change-Id: I13716e39f540f8674b1c0f917048bb6b63f7b763
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1173076
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Use the general video memory allocator for reserving wpr space for acr
ucode blob instead of crafting a mem_desc manually.
Jira DNVGPU-16
Change-Id: I9d34b3b964eb9ab781fcebecd15ba81643c5452d
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1165642
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Added fifo configuration support for gp104 and
gp106. These GPU chips have more number of
channel fifo and runlist than gp10b.
Added get_num_fifos and
eng_runlist_base_size function pointer
to find out the actual value from HW headers.
JIRA DNVGPU-25
Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1164653
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- setting WPR at 188MB of VIDMEM
- setting 256/512MB location at
VIDMEM for WPR cause ACR boot failure
on GP104/GP106 PROD board but works fine
for DEBUG board,
- Removed unwanted WPR info dump
JIRA DNVGPU-34
Change-Id: I44f9861774fe77dd534d316d91ed9f8dfcb298b4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1164840
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Include mm_gp106.h in mm_gp106.c to bring function declarations visible
and to fix a Sparse warning.
Bug 200088648
Change-Id: Id76f565021de585bc02a53a01e52084ff70009c2
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1161607
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Read video memory size from hardware during initialization for devices
that support it.
JIRA DNVGPU-14
Change-Id: I84e1bca0eaac8dc204e1fb82628acc6b52c3e5cc
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1157212
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
Pascal GPU series
5) Removed hard coded engine_id logic and
made generic way
6) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
