Compile out the function mc_gp10b_log_pending_intrs() with the
CONFIG_NVGPU_NON_FUSA macro since it isn't used in the FUSA build.
JIRA NVGPU-2224
Change-Id: I5b2d465142be7d1bddf114c7374ced7b297c33d0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257127
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Compile out unused code in gr.falcon for safety build.
By default NVGPU_SEC_SECUREGPCCS is enabled in Safety build. Add
CONFIG_NVGU_GR_FALCON_NON_SECURE_BOOT checking with non secure code.
In gm20b_gr_falcon_wait_ctxsw_ready function watchdog timer value is
calculated based on clock rate, not needed for safety code.
Add CONFIG_NVGPU_HAL_NON_FUSE checking for unused code in that function.
gm20b_gr_falcon_gr_code_less_equal is the last op status we check.
SKIP or any other status following this will be failed in checking
for valid op status. So code reaching this function mean it is for
only for GR_IS_UCODE_OP_LESSER_EQUAL. So removing the checking for
opc_status != GR_IS_UCODE_OP_LESSER_EQUAL in this function
Jira NVGPU-4453
Change-Id: I156cac59f52779fa7f78052c1f0115d0e8f03bf9
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258768
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Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.
JIRA NVLINK-283
Bug 2701677
Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
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MISRA Advisory Rule 4.4 states that sections of code should
not be commented out.
This change removes the following comment from gp10b_get_device_info():
} else { /* (entry == top_device_info_entry_engine_type_v()) */
JIRA NVGPU-3178
Change-Id: I0d5f0e9370a24b20c6e7487c92b956eb9e8a3048
Signed-off-by: Scott Long <scottl@nvidia.com>
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* Updated types and added error checks
* Modified GR condition for ctxsw disable count
CERT-C error check was added to detect error on integer overflow
But below logic couldn't detect first overflow, so updated condition
INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
So, we didn't detected in first overflow and lead to assert on enable
JIRA NVGPU-3400
Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
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To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute
on different hardware resources.
This feature requires a change in software to make it possible
to modify the virtual SM id to TPC mapping across mission and
redundant contexts.
This CL adds only SM diversity flags which are exposed to
its clients through ioctl/devctl interfaces.
Actual virtual SM id to TPC mapping implementation
will be part of upcoming patch sets.
Added NvGpu CFLAGS to identify the safety build
"CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY"
JIRA NVGPU-4133
Change-Id: I5a18256780e6726e399e39c1c8d155d2ef07d7bd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
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nvgpu_mc_log_pending_intrs is debugging related function hence compile
out that and related functionality under CONFIG_NVGPU_NON_FUSA.
nvgpu_mc_intr_enable is applicable for older chips hence compile out
under CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA.
Update BUS, CE, ECC, FIFO, MC, PRIV_RING, GR, LTC, FB, PMU units'
doxygen comments based on recent ECC and MC refactoring.
JIRA NVGPU-4439
Change-Id: I337318683d6311b9c2b5748f2fb07dff29a6584f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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- Remove non-safe TPC powergate feature from the safety
build by introducing a new flag:
CONFIG_NVGPU_TPC_POWERGATE
- Move nvgpu_init_power_gate_gr() under same compile time flag.
and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c
- Also, remove the negative test scenario and
usage of tpc_powergate from unit tests
JIRA NVGPU-4149
Change-Id: If489482401e94de499e472b16b1bc091b00992e6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.
gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.
Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.
Jira NVGPU-3968
Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247346
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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Remove following error paths as they would never get called:
1. In gm20b_device_info_parse_enum:
- This is a private HAL and is only called by get_device_info HAL.
- It gets called only for table entry with entry type = enum.
- So we remove the check if(entry_type != enum)...
2. In gp10b_device_info_parse_data:
- This is a private HAL and is only called by get_device_info HAL.
- It gets called only for table entry with entry type = data.
- So we remove the check if(entry_type != data)...
3. In gp10b_get_device_info
- entry corresponds to 2 bit extracted from the table_entry.
- So, entry can have only 4 possible values.
- We would never reach the else case; hence remove it.
JIRA NVGPU-2204
Change-Id: I6243f4f9ffd78829f7057aad943ecc6980f82c86
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243264
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FMON/Clock Mon detects for fault in a particular clock domain.
For this we need to poll a specified master register to know if there
is any fault. If this is set we scan all the available clock domains
to see which domain is faulted and the type of fault.
This CL will have all required common functions to monitor
different clock domains registers.
Bug 2182063
NVGPU-3846
Change-Id: I6a2bdb65335eaeef995eb163d480ee722c230311
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170887
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The devinit executes in parallel with PCIE link training
to reduce exit latency. Therefore, all PCIE settings that
normally occur during devinit after the PCIE link is up are
deferred until nvgpu has resumed control.
Bug 2661545
Change-Id: Ifdd4f645b2e1791d93567cc34d6ab0691a25d101
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210625
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Move graphics related defs and functions under CONFIG_NVGPU_GRAPHICS
switch.
Move classes not supported in GV11B under CONFIG_NVGPU_NON_FUSA
switch.
Add missing valid class numbers to gpu_class.is_valid HAL.
Also remove un-used class defs from class.h header.
Lot of qnx safety tests are still using graphics 3d class.
Until those tests got fixed, allowing 3d graphics class
as valid class for safety build.
JIRA NVGPU-4301
Change-Id: Ifd2a13bee3210821799c2bca10e7245eb3c79121
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
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This function gets the GPU chip architecture, implementation and
revision information by reading the MC boot register, hence it
is more suited to be located in HAL files.
test_check_gpu_state is now being run after test_hal_init as the
gops.mc needs to be initialized for test_check_gpu_state subtest.
JIRA NVGPU-2524
Change-Id: I85355af11d3505a9eb4f10a3fe4e6d9b56285047
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2226018
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gk20a.h will include gops_mc.h to contain the mc ops definitions. Add
doxygen comments for the HAL functions that are called directly.
Also move mc_gp10b_intr_pmu_unit_config to non-fusa HAL file.
JIRA NVGPU-2524
Change-Id: I4f326332d7842211b004b372d79fac9fe6ed40e7
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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Moved mmu replayable fault related code under CONFIG_NVGPU_REPLAYABLE_FAULT
switch, so that it will be compiled out for safety build.
Following hals and their related code also moved under
CONFIG_NVGPU_REPLAYABLE_FAULT switch:
void (*handle_replayable_fault)(struct gk20a *g);
int (*mmu_invalidate_replay)(struct gk20a *g, u32 invalidate_replay_val);
JIRA NVGPU-4302
Change-Id: I191ee0c181b276a04bc1531488862380af81a5c9
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Functions for copying to falcon memory typecast from pointer to char of
input buffer to pointer to u32 since falcon data registers are written
in 4-bytes. Firmware data is generally byte stream and hence we won't
be able to deal with input buffer as pointer to u32.
Hence, misra rule 11.3 deviation is required for these casts. Firmware
data is also not aligned at word boundary sometimes hence we need to
copy it to aligned buffer to conform to the deviation recommendation.
hal/falcon/falcon_gk20a_fusa.c:136
Checker: MISRA C-2012 Rule 11.3 (Required)
misra_c_2012_rule_11_3_violation: The object pointer expression "src"
of type "u8 *" is cast to type "u32 *".
This patch implements copy to falcon memory from unaligned source byte
by byte and casts the input buffer to u32 pointer otherwise.
JIRA NVGPU-4128
Change-Id: Iff3cc1010b8e209ec453c10c6d46953cf5a8adbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210321
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Currently nvgpu reads the temperature by reading the
NV_THERM_I2CS_SENSOR_00 register. Below are the issues
with current approach
1) NV_THERM_I2CS_SENSOR_00 doesn't support
fractional precision which is POR.
2) It doesn't support negative temperatures which
is required for Auto.
3) It doesn't take into account the right POR
sensor in VFE VBIOS tables.
From therm channel get status interface we can read the
current temperature from PMU.
NVBUG - 200549047
Change-Id: I2fb21926208876f3d3bebe3f2dee08edafedbc7d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
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