Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.
Change-Id: If3c1e25dcb07ce6857a4798f2c5308e2948fe5e0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571163
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Re-generate hardware headers so that all unsigned constants are
qualified with postfix U. This removes the need for compiler to do
implicit signed->unsigned conversions.
Change-Id: Ic93ef7f7a6beae57be7759c7eb3df9148afed824
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571162
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
These changes allow GV100 to init the basic HALs to pass
nvgpu_submit_twod
(1) Allocate fault buffer from vidmem instead of sysmem to prevent coherency
issues
(2) Properly enable FB
(3) Fan control requires the execution of the pre-os FW, without it the SKU201
is extremely noisy
JIRA: NVGPUGV100-9
Change-Id: I9b2072737e45432f957e7faae6d33bc0ab43b817
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539926
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- Falcon HW header re-generate for gv11b.
- Re-generate hardware headers so that all unsigned
constants are qualified with postfix U. This removes
the need for compiler to do implicit signed->unsigned
conversions
Change-Id: I313945edac1112a32c965d9565b30dc95a002752
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1571352
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
- Constants are qualified with postfix U.
This removes the need for compiler to do
implicit signed->unsigned conversions
Change-Id: I039e269b18ea8aea48b30d3af84b347ae5509413
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570998
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as
g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100
This API will check if channel has ENG_FAULTED status set, if yes it will clear
CE method buffer in case saved out channel is same as faulted channel
We need to write 0 to method count to invalidate CE method buffer
Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100
Bug 200327095
Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560643
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add TSG enable/disable operations for gv11b/gv100
To disable a TSG we continue to use gk20a_disable_tsg()
To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is
different for Volta than previous versions
For Volta it is sufficient to loop over all the channels in TSG and enable them
sequentially
Bug 1739362
Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560642
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields
in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is
used by the user space driver to disable enough ROP optimizations
to maintain ZBC state of target tiles.
Bug 1942454
Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1516205
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add gv11b implementation of gpu_phys_addr() that checks the t19x
GMMU attributes struct to determine if L3 allocation should be
enabled. If L3 alloc is enabled then a special physical address
bit is set.
Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct
nvgpu_as_map_buffer_ex_args so that User space can add a hint to
allocate buffer in L3 cache
Jira GPUT19X-10
Bug 200279508
Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master/r/1512602
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers
JIRA GPUT19X-75
Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Added handling for below ce interrupts
-INVALID_CONFIG interrupt will be generated if a floorswept
PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG
registers. This is a fatal error and the LCE will have to be
reset to get back to a working state.
-MTHD_BUFFER_FAULT interrupt will be triggered if any access to
a method buffer during context load or save encounters a fault.
This is a fatal interrupt and will require at least the LCE to be reset
before operations can start again, if not the entire GPU.
JIRA GPUT19X-12
JIRA GPUT19X-46
Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1510298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Pbdma which encountered the ctxnotvalid interrupt will stall and
prevent the channel which was loaded at the time the interrupt fired
from being swapped out until the interrupt is cleared.
CTXNOTVALID pbdma interrupt indicates error conditions related
to the *_CTX_VALID fields for a channel. The following
conditions trigger the interrupt:
* CTX_VALID bit for the targeted engine is FALSE
* At channel start/resume, all preemptible eng have CTX_VALID FALSE but:
- CTX_RELOAD is set in CCSR_CHANNEL_STATUS,
- PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or
- PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE
JIRA GPUT19X-47
Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1329372
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add new abstraction file common/linux/nvhost_t19x.c
for all nvhost APIs exported from linux/nvhost_t194.h
This file will be compiled only if config
CONFIG_TEGRA_GK20A_NVHOST is set
Export the new headers from file <nvgpu/nvhost_t19x.h>
Also add dummy private header file nvhost_priv_t19x.h
to store definition of private structure nvgpu_nvhost_dev
This file should be deleted when nvgpu-t19x repo
is merged into common nvhost repo
Jira NVGPU-29
Change-Id: I8c08c9242b08cc45f7c99cc400b3e1a720f9439c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1493792
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Adding support for ISR handling of GPCCS exceptions
and GCC ECC support
JIRA: GPUT19X-83
Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480997
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following parity support (uncorrected error),
1) SM's L1 DATA
2) SM's L0 && L1 icache
Volta Resiliency Id - Volta-634
JIRA GPUT19X-113
JIRA GPUT19X-99
Bug 1807553
Change-Id: Iacbf492028983529dadc5753007e43510b8cb786
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1483681
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This CL covers the following parity support (uncorrected error),
1) SM's LRF
2) SM's CBU
Volta Resiliency Id - Volta-637
JIRA GPUT19X-85
JIRA GPUT19X-110
Bug 1775457
Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1481791
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Adding support for ISR handling of ecc uncorrectable errors
for volta resiliency (Volta-686)
TODO: move interrupt init out of MC
bug 1881052
JIRA: GPUT19X-82
Change-Id: I45db01a6062445dd1f64a8297744cd15105e3344
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1476603
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Without these credits, gpu mmu binds over nvlink to soc are hanging.
Also add l2_enabled for mc_elpg_enable.
Bug 1899460
Change-Id: I0b26410d5c8ec9b4c88b319ddd9442f2fd91b321
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1463204
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
