Commit Graph

63 Commits

Author SHA1 Message Date
Konsta Hölttä
7aa852b31c gpu: nvgpu: emphasize fence syncpt/sema interfaces
Sometimes the syncpt-based fences are not used, and often the sema-based
fences are not used. Move code around to new files to make it easier to
see what happens and to allow leaving code out of the build easily.

Start using nvgpu_fence_ops::free again and move the fence release
there. The syncpt data is not refcounted, so it doesn't have this.

Jira NVGPU-5773

Change-Id: I991f91886c59cf2c2fbfd2e75305ba512b5d7371
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2395069
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
223d8522a1 gpu: nvgpu: clarify fence api assumptions
Adjust documentation and validity checks in the fence functions for
simplicity.

Now that the cde code is using user fences cleanly, the
do-nothing-on-null action can cause unintended behaviour in new code
using nvgpu_fence_get and nvgpu_fence_put. It does not make sense to
call these with a null fence, so delete the checks.

Extend the documentation in nvgpu_fence_extract_user() for the os fence
lifetime to give a reason for the dup call.

Make nvgpu_fence_from_semaphore() and nvgpu_fence_from_syncpt() return
void. These fill a previously allocated object; the only failure would
have been a null object, but that never happens and is not acceptable
behaviour for callers so delete these null checks and fix types.

Jira NVGPU-5248

Change-Id: I9f82365d50ab5600374c8f7dd513691eac14a2f1
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2359624
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
4e241d5974 gpu: nvgpu: adapt to generic syncpt api
Use the nvhost sync fence APIs that do not require knowledge about the
sync fence version. Nvhost exports an opaque nvhost_fence type with a
common interface for both legacy and stable sync fences.

Delete the syncfd-specific nvhost wrappers. They exist only on Linux, so
having them in the nvhost wrapper layer is just a hassle. The os fence
interface is already one wrapper.

Jira NVGPU-5386

Change-Id: I3849db3684c7be8f37cf53971347f26247a52d6c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2355650
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
d916e85171 gpu: nvgpu: incr sync once submit is ready to go
Split out the max value increment and syncpt interrupt registration out
of nvgpu_channel_sync_incr*(). This API is called in the submit path to
prepare buffers and tracking resources, but later on in the submit path
errors can still occur so that the increment wouldn't happen (unless
artificially forced by sw).

The increment and irq registration cannot easily be undone and it makes
more sense to do these at the moment when the prepared job is finally
ready, so add a new nvgpu_channel_sync_mark_progress() API to be called
later in the submit path to signal that progress shall eventually happen
on the sync. Without this, the max value would stay too large after an
unsuccessful submit until the channel gets closed.

The sync object (syncpt or semaphore) is always exclusively owned by the
channel that allocated it, so nonatomically reading the max value first
in sync_incr() and incrementing it later in mark_progress() is racefree;
all submits per channel are serialized.

Change the channel syncpoint to client managed from host managed so that
nvhost-exported sync fences behave correctly with the temporary state
where the fence threshold is over the max value. Ideally we'd always
track nvgpu-owned syncpts' max values internally, but this is enough for
now.

Jira NVGPU-5491

Change-Id: Idf0bda7ac93d7f2f114cdeb497fe6b5369d21c95
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340465
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
3875c0825f gpu: nvgpu: avoid sema/channel dependencies
Move the per-channel hw semaphore object to be owned by the channel sync
(just like with syncpoints, too). Store just the channel ID in the hw
sema for debug prints to get rid of sema->channel dependencies. Make
nvgpu_semaphore_alloc() take a hw sema instead of a channel.

Fix up some channel-related documentation that has been incorrect.

Jira NVGPU-5353

Change-Id: I04d49da3aac50a4cea32e7393f48e6f85a80ca0d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339931
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
e5b23f33b9 gpu: nvgpu: add internal CONFIG_SYNC wrapper
The sync file support in Linux has been stabilized and the new config is
called CONFIG_SYNC_FILE. Even if maybe not so intended, both the
stabilized version and the legacy CONFIG_SYNC can coexist; to begin with
supporting the stabilized version, add CONFIG_NVGPU_SYNCFD_ANDROID and
CONFIG_NVGPU_SYNCFD_NONE as choice configs of which one will be set. A
later patch will extend this with a choice for CONFIG_SYNC_FILE.

Jira NVGPU-5353

Change-Id: I67582b68d700b16c46e1cd090f1b938067a364e3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336118
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
05df07945a gpu: nvgpu: avoid channel dependency in priv cmdbuf
The priv cmdbuf queue needs only the vm_gk20a of the channel that owns
it. Pass the vm to the queue constructor and have the channel code store
the queue to itself instead of poking at the channel from the queue
code. Adjust the cmdbuf queue api to take the queue, not the channel.

Move the inflight job fallback calculation to the channel code. The size
of the channel gpfifo isn't needed in the queue; just the job count is.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I4277dc67bb50380cb157f3aa3c5d57b162a8f0ba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329659
(cherry picked from commit 83b2276f7bea563602eee20ce24b70ce70c8475a)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
991002c88b gpu: nvgpu: hide struct priv_cmd_entry
The type for entries allocated from the priv cmd queue is no longer
necessary to be visible for its users other than as an opaque handle,
except for a few minor debug prints. Make those prints output the entry
pointer value instead and move the struct definition to priv_cmdbuf.c.

Jira NVGPU-4548

Change-Id: Ia75ff41d840ac928561525a46d5973640e4b5f7e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329658
(cherry picked from commit 3292cdadbc78ca129d1e0878c3947b0839487fc2)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
9bee2fe660 gpu: nvgpu: prealloc priv cmdbuf metadata
Move preallocation of priv cmdbuf metadata structs to the priv cmdbuf
level and do it always, not only on deterministic channels. This makes
job tracking simpler and loosens dependencies from jobs to cmdbuf
internals. The underlying dma memory for the cmdbuf data has always been
preallocated.

Rename the priv cmdbuf functions to have a consistent prefix.

Refactor the channel sync wait and incr ops to free any priv cmdbufs
they allocate. They have been depending on the caller to free their
resources even on error conditions, requiring the caller to know how
they work.

The error paths that could occur after a priv cmdbuf has been allocated
have likely been wrong for a long time. Usually the cmdbuf queue allows
allocating only from one end and freeing from only the other end, as
that's natural with the hardware job queue. However, in error conditions
the just recently allocated entries need to be put back. Improve the
interface for this.

[not part of the cherry-pick:] Delete the error prints about not enough
priv cmd buffer space. That is not an error. When obeying the
user-provided job sizes more strictly, momentarily running out of job
tracking resources is possible when the job cleanup thread does not
catch up quickly enough. In such a case the number of inflight jobs on
the hardware could be less than the maximum, but the inflight job count
that nvgpu sees via the consumed resources could reach the maximum.
Also remove the wrong translation to -EINVAL from err from one call to
nvgpu_priv_cmdbuf_alloc() - the -EAGAIN from the failed allocation is
important.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I09d02bd44d50a5451500d09605f906d74009a8a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329657
(cherry picked from commit 25412412f31436688c6b45684886f7552075da83)
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2020-12-15 14:13:28 -06:00
Dinesh
1c1da3d6b4 gpu: nvgpu: Syncpoint invalid value to ~0.
As qnx syncpoint's invalid value is ~0, change the code
to handle this.

Bug 200603716

Change-Id: I5ec79688cd9e60066725781f1effe57692ec0c27
Signed-off-by: Dinesh <dt@nvidia.com>
(cherry picked from commit 705260565a75bc90683841c4c08e4c857bda39f0)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
e9747d5477 gpu: nvgpu: remove wait_fence_fd from incr_user
The wait_fence_fd parameter in nvgpu_channel_sync_incr_user() has not
been used since commit 1a4647272f ("gpu: nvgpu: remove fence
dependency tracking") where it was used to save a dependency fd to
sema-based post fences. The commit probably should have removed this
param; it has no purpose in the current design.

Jira NVGPU-4548

Change-Id: Id7e68b24f8e9ba0e43ff01b7af946434580b166e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2326604
(cherry picked from commit f8031142270fb87ac41597ae70a80505078ae6d5)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
aa1322f975 gpu: nvgpu: move syncpt priv cmd allocation
channel_sync_syncpt_gen_wait_cmd() is rather simple now and is called
from two places where one has the buf preallocated and the other
doesn't. Remove the preallocated flag from the function, moving the
allocation to the single place where it is needed.

Jira NVGPU-4548

Change-Id: I48083f4f6f1093d64b67c63582291392a3481932
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325101
(cherry picked from commit afb566721e2b4c15349ff79d51f5eddc49b66014)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
39844fb27c gpu: nvgpu: hide priv cmdbuf mem writes
Add an API to append data to a priv cmdbuf entry. Hold the write pointer
offset internally in the entry instead of having the user keep track of
where those words are written to.

This helps in eventually hiding struct priv_cmd_entry from users and
provides a more consistent interface in general. The wait and incr
commands are now slightly easier to read as well when they're just
arrays of data.

A syncfd-backed prefence may be composed of several individual fences.
Some of those (or even a fence backed by just one) may be already
expired, and currently the syncfd export design releases and nulls
semaphores when expired (see gk20a_sync_pt_has_signaled()) so for those
the wait cmdbuf is appended with zeros; the specific function is for
this purpose.

Jira NVGPU-4548

Change-Id: I1057f98c1b5b407460aa6e1dcba917da9c9aa9c9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325099
(cherry picked from commit 6a00a65a86d8249cfeb06a05682abb4771949f19)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
00203b42f2 gpu: nvgpu: split add_sema_cmd to wait and incr
The internal add_sema_cmd() used when making cmd buf entries has so many
branches it makes sense to split it at the bool acquire flag into two
functions. The wait part doesn't even need the wfi flag, and the incr
part doesn't need offset.

Jira NVGPU-4548

Change-Id: Iab26b9bc14564e2958935ab7ffda03aa873dd9b1
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323320
(cherry picked from commit 9fe2830aa9ee2b0b165edc959defa74dfb49c6ba)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
6202ead057 gpu: nvgpu: split sema sync hal to wait and incr
Instead of one HAL op with a boolean flag to decide whether to do one
thing or another entirely different thing, use two separate HAL ops for
filling priv cmd bufs with semaphore wait and semaphore increment
commands. It's already two ops for syncpoints, and explicit commands are
more readable than boolean flags.

Change offset into cmdbuf in sem wait HAL to be relative to the cmdbuf,
so the HAL adds the cmdbuf internal offset to it.

While at it, modify the syncpoint cmdbuf HAL ops' prototypes to be
consistent.

Jira NVGPU-4548

Change-Id: Ibac1fc5fe2ef113e4e16b56358ecfa8904464c82
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323319
(cherry picked from commit 08c1fa38c0fe4effe6ff7a992af55f46e03e77d0)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
b3d16b23d5 gpu: nvgpu: extract priv cmdbuf from channel.c
Move private command buffer related functionality to priv_cmdbuf.c. This
is used only for kernel mode submits, so it makes sense to group it out,
and the priv cmdbuf stuff is used also by things that don't care about
channels.

Jira NVGPU-4548

Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146
(cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
52835c39ae gpu: nvgpu: do not skip completed syncpt prefences
A corner case has existed since ancient times for syncpoint-backed
prefences to not cause a gpu wait if the fence is found to be completed
in the submit path. This adds some unnecessary complexity, so don't
check for completion in software. Let the gpu "wait" for these
known-to-be-trivial waits too. Necessary priv cmdbuf space has been
allocated anyway.

Originally nvhost had 16-bit fences which would wrap around relatively
quickly, so waiting for an old fence could have looked like waiting for
a fence that will expire long in the future. With 32-bit thresholds,
this hasn't been the case for several Tegra generations anymore, and
nvhost doesn't ignore waits like this either.

The wait priv cmdbuf in submit path can still be missing even with a
prefence supplied because the Android sync framework supports sync fds
that contain zero fences inside; this can happen at least when merging
fences that have all been expired. In such conditions the wait cmdbuf
wouldn't even get allocated.

[this is squashed with commit 8b3b0cb12d118 (gpu: nvgpu: allow no wait
cmd with valid input fence) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325677]

Jira NVGPU-4548

Change-Id: Ie81fd8735c2614d0fedb7242dc9869d0961610eb
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321762
(cherry picked from commit 8f3dac44934eb727b1bf4fb853f019cf4c15a5cd)
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
2d9b839f21 gpu: nvgpu: remove user sync related apis
Set safe state and get syncpt address in the kernel submission tracking
syncs was implemented for userspace syncs. Now that it's clear that the
user sync object provides them, there are no users left for these APIs.
Remove them.

Jira NVGPU-4548

Change-Id: I58e04162dee55bb8d8547c9252033f40ed908144
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321950
(cherry picked from commit a95c8f7ace562a11ca235d71496d3a7ce150bc7d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324251
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
4f80c6b8a9 gpu: nvgpu: add channel_user_syncpt
Refactor user managed syncpoints out of the channel sync infrastructure
that deals with jobs submitted via the kernel api. The user syncpt only
needs to expose the id and gpu address of the reserved syncpoint. None
of the rest (fences, priv cmdbufs) is needed for that, so it hasn't been
ideal to couple with the user-allocated syncpts.

With user syncpts now provided by channel_user_syncpt, remove the
user_managed flag from the kernel sync api.

This allows moving all the kernel submit sync code to be conditionally
compiled in only when needed, and separates the user sync functionality
in a more clear way from the rest with a minimal API.

[this is squashed with commit 5111caea601a (gpu: nvgpu: guard user
syncpt with nvhost config) from
https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325009]

Jira NVGPU-4548

Change-Id: I99259fc9cbd30bbd478ed86acffcce12768502d3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321768
(cherry picked from commit 1095ad353f5f1cf7ca180d0701bc02a607404f5e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319629
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
d0ffb335dc gpu: nvgpu: move nvgpu_has_syncpoints
nvgpu_has_syncpoints is more general than a channel synchronization
related, so move it to nvhost.c from channel_sync.c. Move the
declaration from gk20a.h to nvhost.h.

As the debugfs knob is Linux related, move it from struct gk20a to
struct nvgpu_os_linux.

Jira NVGPU-4548

Change-Id: I4236086744993c3daac042f164de30939c01ee77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318814
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
46761356e5 gpu: nvgpu: make channel sync ops const
The function pointers for the syncpoint and semaphore implementations of
struct nvgpu_channel_sync do not change in runtime. Make this more
explicit by having the pointers in predefined private structures. Each
instance of a sync (which there are one per open channel) gets a pointer
to an ops structure instead of a list of all the individual ops.

Jira NVGPU-4548

Change-Id: I361b74bdfe32470203760d11c30e048cb4d20b77
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2318242
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
f2446737fd gpu: nvgpu: fifo: add coverage & traceability
This patch adds new channel and sync test to improve coverage. This
patch also updates SWUTs target tag to increase function traceability
and updates test type.

Jira NVGPU-4817

Change-Id: I52a7fa27f61e7e465d2ede25b92745413f17e50b
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280963
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2020-12-15 14:13:28 -06:00
Adeel Raza
fd870b300e gpu: nvgpu: rename nvhost_dev to nvhost
A couple of structure member variables were named "nvhost_dev". This
causes a name conflict with a structure name. MISRA frowns upon name
conflicts. Therefore, rename the member variables to "nvhost".

JIRA NVGPU-3873

Change-Id: I4d35eb2d121b3c17499055d8781a61641594811e
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262190
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2020-12-15 14:10:29 -06:00
Adeel Raza
26af1c2270 gpu: nvgpu: MISRA integer fixes
Apply various MISRA integer related fixes. Some fixes simply required
adding a "U" suffix to integer constants. Other fixes were more
complicated and required breaking up complex composite expressions into
multiple smaller expressions.

JIRA NVGPU-3873

Change-Id: Id8a08a17d1cf9e20193bd3e4f2d4104774d81767
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262189
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2020-12-15 14:10:29 -06:00
Adeel Raza
eb0b0c78d4 gpu: nvgpu: sync: remove snprintf usage
snprintf() usage is banned by MISRA because it uses variable arguments.
Replace snprintf() with other string operations.

JIRA NVGPU-3873

Change-Id: I22205f91500c997c155fe1759ccea90b3f481d59
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262188
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2020-12-15 14:10:29 -06:00
ddutta
83103cdcca gpu: nvgpu: move set_min_max out of safety build
nvgpu_channel_sync_set_min_eq_max is not used as part of the safety
build and hence is moved out. channel_sync_syncpt_set_min_eq_max is
also moved out as a part of the above function.

Also add a branch coverage for the case when g->disable_syncpoints is
set to true.

Jira NVGPU-913

Change-Id: I2512d01e105551732aad63b2800bb4cb6d913cb2
Signed-off-by: ddutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263003
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2020-12-15 14:10:29 -06:00
Debarshi Dutta
037c5761e7 gpu: nvgpu: handle syncpoint buffer alloc failure
Add check for syncpoint buffer allocation failure in the function
nvgpu_channel_sync_syncpt_create. Return NULL if the allocation fails.

Also, put a reference to the syncpoint allocated if the above
buffer allocation fails.

Change-Id: I56ab03df3b37a3c8148ee17ec6a7829686e44de6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247637
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2020-12-15 14:10:29 -06:00
dinesh
25abe6a352 gpu: nvgpu: Compile out linux nvhost
This is added to compile out some non safety code from safety build.

JIRA NVGPU-4146

Change-Id: Ie2b05f7c1bf1d0400184ae95d39103828c28de1e
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217415
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2020-12-15 14:10:29 -06:00
Nitin Kumbhar
f8e4393ace gpu: nvgpu: fix possible buffer overflow issue
As sprintf() is used to populate pool_name[20], it can overflow
for larger u32 values (u32 max decimal number chars are 10) i.e.
20 < strlen("semaphore_pool-") i.e. 15 + 10.

Fix this overflow by removing pool_name as it's not used.

Bug 2626446

Change-Id: I4e0a222a2cd34dcd09e69294bc46e2242abb04bb
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205356
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2020-12-15 14:05:52 -06:00
Debarshi Dutta
92d009e796 gpu: nvgpu: add safety build flag CONFIG_NVGPU_SW_SEMAPHORE
Added the safety build flag CONFIG_NVGPU_SW_SEMAPHORE to compile out
sw semaphore implementation in NVGPU. sw semaphore is only used for
presilicon bringup of GPU and hence is not needed for safety build.

Jira NVGPU-3172

Change-Id: I6a46ef22f1e2059437f710198f4ea49a47656fef
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164216
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2019-07-31 23:26:19 -07:00
Debarshi Dutta
f6c96f620f gpu: nvgpu: add CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag
The following functions belong to the path of kernel_mode submit and
the flag CONFIG_NVGPU_KERNEL_MODE_SUBMIT is used to compile these out
of safety builds.

channel_gk20a_alloc_priv_cmdbuf
channel_gk20a_free_prealloc_resources
channel_gk20a_joblist_add
channel_gk20a_joblist_delete
channel_gk20a_joblist_peek
channel_gk20a_prealloc_resources
nvgpu_channel
nvgpu_channel_add_job
nvgpu_channel_alloc_job
nvgpu_channel_alloc_priv_cmdbuf
nvgpu_channel_clean_up_jobs
nvgpu_channel_free_job
nvgpu_channel_free_priv_cmd_entry
nvgpu_channel_free_priv_cmd_q
nvgpu_channel_from_worker_item
nvgpu_channel_get_gpfifo_free_count
nvgpu_channel_is_prealloc_enabled
nvgpu_channel_joblist_is_empty
nvgpu_channel_joblist_lock
nvgpu_channel_joblist_unlock
nvgpu_channel_kernelmode_deinit
nvgpu_channel_poll_wdt
nvgpu_channel_set_syncpt
nvgpu_channel_setup_kernelmode
nvgpu_channel_sync_get_ref
nvgpu_channel_sync_incr
nvgpu_channel_sync_incr_user
nvgpu_channel_sync_put_ref_and_check
nvgpu_channel_sync_wait_fence_fd
nvgpu_channel_update
nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_channel_update_priv_cmd_q_and_free_entry
nvgpu_channel_wdt_continue
nvgpu_channel_wdt_handler
nvgpu_channel_wdt_init
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_restart_all_channels
nvgpu_channel_wdt_rewind
nvgpu_channel_wdt_start
nvgpu_channel_wdt_stop
nvgpu_channel_worker_deinit
nvgpu_channel_worker_from_worker
nvgpu_channel_worker_init
nvgpu_channel_worker_poll_init
nvgpu_channel_worker_poll_wakeup_post_process_item
nvgpu_channel_worker_poll_wakeup_process_item
nvgpu_submit_channel_gpfifo_kernel
nvgpu_submit_channel_gpfifo_user
gk20a_userd_gp_get
gk20a_userd_pb_get
gk20a_userd_gp_put
nvgpu_fence_alloc

The following members of struct nvgpu_channel are compiled out of
safety build.

struct gpfifo_desc gpfifo;
struct priv_cmd_queue priv_cmd_q;
struct nvgpu_channel_sync *sync;
struct nvgpu_list_node worker_item;
struct nvgpu_channel_wdt wdt;

The following files are compiled out of safety build.

common/fifo/submit.c
common/sync/channe1_sync_semaphore.c
hal/fifo/userd_gv11b.c

Jira NVGPU-3479

Change-Id: If46c936477c6698f4bec3cab93906aaacb0ceabf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127212
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2019-06-30 22:04:48 -07:00
Debarshi Dutta
f39a5c4ead gpu: nvgpu: rename gk20a_channel_* APIs
Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.

Jira NVGPU-3248

Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
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2019-05-21 09:26:16 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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2019-05-15 16:46:27 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
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2019-05-09 04:39:34 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
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2019-05-06 02:56:53 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
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2019-05-01 15:06:57 -07:00
Thomas Fleury
e69b5f75ba gpu: nvgpu: move sync cmdbuf to hal/sync
Moved
- common/sync/sema_cmdbuf_gk20a.c -> hal/sync/sema_cmdbuf_gk20a.c
- common/sync/sema_cmdbuf_gk20a.h -> hal/sync/sema_cmdbuf_gk20a.h
- common/sync/sema_cmdbuf_gv11b.c -> hal/sync/sema_cmdbuf_gv11b.c
- common/sync/sema_cmdbuf_gv11b.h -> hal/sync/sema_cmdbuf_gv11b.h
- common/sync/syncpt_cmdbuf_gk20a.c -> hal/sync/syncpt_cmdbuf_gk20a.c
- common/sync/syncpt_cmdbuf_gk20a.h -> hal/sync/syncpt_cmdbuf_gk20a.h
- common/sync/syncpt_cmdbuf_gv11b.c -> hal/sync/syncpt_cmdbuf_gv11b.c
- common/sync/syncpt_cmdbuf_gv11b.h -> hal/sync/syncpt_cmdbuf_gv11b.h

Updated makefiles and #include directives.

Jira NVGPU-1984

Change-Id: I5df008512a9243572081a89310d12a77c2354924
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101322
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2019-04-22 23:54:35 -07:00
Thomas Fleury
c270bb73ae gpu: nvgpu: rename syncpt and sema HALs
Renamed the following HALs
- syncpt.alloc_syncpt_buf -> syncpt.alloc_buf
- syncpt.free_syncpt_buf -> syncpt.free_buf
- syncpt.add_syncpt_wait_cmd -> syncpt.add_wait_cmd
- syncpt.get_syncpt_wait_cmd_size -> syncpt.get_wait_cmd_size
- syncpt.get_syncpt_incr_per_release -> syncpt.get_incr_per_release
- syncpt.add_syncpt_incr_cmd -> syncpt.add_incr_cmd
- syncpt.get_syncpt_incr_cmd_size -> syncpt.get_incr_cmd_size
- syncpt.get_sync_ro_map -> syncpt.get_sync_ro_map
- sema.get_sema_wait_cmd_size -> sema.get_wait_cmd_size
- sema.get_sema_incr_cmd_size -> sema.get_incr_cmd_size
- sema.add_sema_cmd -> sema.add_cmd

Renamed HAL implementations as:
- gk20a_alloc_syncpt_buf -> gk20a_syncpt_alloc_buf
- gk20a_free_syncpt_buf -> gk20a_syncpt_free_buf
- gk20a_add_syncpt_wait_cmd -> gk20a_syncpt_add_wait_cmd
- gk20a_get_syncpt_wait_cmd_size -> gk20a_syncpt_get_wait_cmd_size
- gk20a_get_syncpt_incr_per_release -> gk20a_syncpt_get_incr_per_release
- gk20a_add_syncpt_incr_cmd -> gk20a_syncpt_add_incr_cmd
- gk20a_get_syncpt_incr_cmd_size -> gk20a_syncpt_get_incr_cmd_size
- gv11b_alloc_syncpt_buf -> gv11b_syncpt_alloc_buf
- gv11b_free_syncpt_buf -> gv11b_syncpt_free_buf
- gv11b_add_syncpt_wait_cmd -> gv11b_syncpt_add_wait_cmd
- gv11b_get_syncpt_wait_cmd_size -> gv11b_syncpt_get_wait_cmd_size
- gv11b_add_syncpt_incr_cmd -> gv11b_syncpt_add_incr_cmd
- gv11b_get_syncpt_incr_cmd_size -> gv11b_syncpt_get_incr_cmd_size
- gv11b_get_syncpt_incr_per_release -> gv11b_syncpt_get_incr_per_release
- gv11b_get_sync_ro_map -> gv11b_syncpt_get_sync_ro_map
- gk20a_get_sema_wait_cmd_size -> gk20a_sema_get_wait_cmd_size
- gk20a_get_sema_incr_cmd_size -> gk20a_sema_get_incr_cmd_size
- gk20a_add_sema_cmd -> gk20a_sema_add_cmd
- gv11b_get_sema_wait_cmd_size -> gv11b_sema_get_wait_cmd_size
- gv11b_get_sema_incr_cmd_size -> gv11b_sema_get_incr_cmd_size
- gv11b_add_sema_cmd -> gv11b_sema_add_cmd

Jira NVGPU-1984
Jira NVGPU-1986

Change-Id: I3eb3f669093588df422a82c54fa1ca64788a490c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096374
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-16 10:46:32 -07:00
Thomas Fleury
656a9aa170 gpu: nvgpu: split sync HAL into syncpt and sema
Split sync HAL into sync.syncpt and sync.sema

Jira NVGPU-1984
Jira NVGPU-1986

Change-Id: I66bd6948e1d77b7728a667de3d3b1ae2adc62e27
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-16 10:46:17 -07:00
Seema Khowala
312f91f991 gpu: nvgpu: move fence_gk20a to common/fence
Move gk20a/fence_gk20a.c to common/fence/fence.c

Renamed
gk20a_fence_from_semaphore -> nvgpu_fence_from_semaphore
gk20a_fence_from_syncpt -> nvgpu_fence_from_syncpt
gk20a_alloc_fence_pool -> nvgpu_fence_pool_alloc
gk20a_free_fence_pool -> nvgpu_fence_pool_free
gk20a_alloc_fence -> nvgpu_fence_alloc
gk20a_init_fence -> nvgpu_fence_init
gk20a_fence_put -> nvgpu_fence_put
gk20a_fence_get -> nvgpu_fence_get
gk20a_fence_wait -> nvgpu_fence_wait
gk20a_fence_is_expired -> nvgpu_fence_is_expired
gk20a_fence_install_fd -> nvgpu_fence_install_fd
gk20a_fence_ops struct -> nvgpu_fence_ops struct
gk20a_fence struct -> nvgpu_fence_type struct

JIRA NVGPU-1982

Change-Id: Ife77b2c3c386ff4368683c78ca02f00c99cddb4b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093002
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-10 17:24:52 -07:00
Nicolas Benech
ee6ef2a719 gpu: nvgpu: resolve MISRA 17.7 for WARN_ON
MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch ensures that WARN and WARN_ON always return void; and
introduces a new nvgpu_do_assert construct to trigger the equivalent
of WARN_ON(true) so that stack can be dumped (depends on OS support)

JIRA NVGPU-677

Change-Id: Ie2312c5588ceb5b1db825d15a096149b63b69af4
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2018706
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-03-05 11:14:46 -08:00
Debarshi Dutta
8db1955d74 gpu: nvgpu: split semaphore.c file into multiple units
The file semaphore.c is now split into 4 units namely
semaphore, semaphore_hw, semaphore_pool and semaphore_sea.

Each of the above units now have separate compilation units under
common/semaphore/. The public APIs corresponding to each unit is
present in include/nvgpu/semaphore.h. The dependency graph of the
below units is as follows where '->' indicates left depends on right.

semaphore -> semaphore_hw -> semaphore_pool -> semaphore_sea

Some of the other major changes made in this patch are as follows
  i) Renamed some of the functions.
  ii) Some functions are changed from private to public.
  iii) Public header for semaphore contains only the declaration of the
       corresponding structs as an opaque structure.
  iv) Constructed a private header to contain internal functions common
      to all the units and struct definitions corresponding to each unit.
  v)  Added new functions to provide access to internal members of the
      units.

Jira NVGPU-2076

Change-Id: I6f111647ba9a9a9f8ef9c658f316cd5d6276c703
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022782
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-27 12:54:15 -08:00
Philip Elcan
ab5684ce1b gpu: nvgpu: channel: use u32 for syncpt id
Make the APIs nvgpu_channel_sync_get_syncpt_id() and
channel_sync_syncpt_get_id() return u32s rather than converting to
ints and back.

Also define FIFO_INVAL_SYNCPT_ID to use for invalid syncpt IDs rather
than using magic numbers.

JIRA NVGPU-1008

Change-Id: I4dde6b15fd3708fb0126b46c6fea8ac1b447c7ce
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014821
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-02-11 12:55:36 -08:00
Adeel Raza
d828e013db gpu: nvgpu: common: MISRA rule 15.6 fixes
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the common directory.

JIRA NVGPU-775

Change-Id: I0dfb38dbf256d49bc0391d889d9fbe5e21da5641
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011655
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2019-02-05 19:23:47 -08:00
Alex Waterman
f766c6af91 gpu: nvgpu: Make "phys" nvgpu_mem impl
Make a physical nvgpu_mem implementation in the common code. This
implementation assumes a single, contiguous, physical range. GMMU
mappability is provided by building a one entry SGT.

Since this is now "common" code the original Linux code has been
moved to commom/mm/nvgpu_mem.c.

Also fix the '__' prefix in the nvgpu_mem function. This is not
necessary as this function, although somewhat tricky, is expected
to be used by arbitrary users within the nvgpu driver.

JIRA NVGPU-1029
Bug 2441531

Change-Id: I42313e5c664df3cd94933cc63ff0528326628683
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1995866
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2019-01-30 16:44:06 -08:00
Debarshi Dutta
911d25dda2 gpu: nvgpu: move sema specific cmdbuf methods to common/sync/
sema cmdbuf specific functions are only for the sync functionality
of nvgpu and donot belong to fifo.

construct files sema_cmdbuf_gv11b.h and sema_cmdbuf_gv11b.c
under common/sync to contain the syncpt specific cmdbuf functions
for arch gv11b.

Jira NVGPU-1308

Change-Id: I440847e8b996e0956d81fe6cdde331937deda40e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975923
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-25 02:46:23 -08:00
Debarshi Dutta
20b15e6f40 gpu: nvgpu: move sema specific cmdbuf methods to common/sync/
sema cmdbuf specific functions are only for the sync functionality
of nvgpu and do not belong to fifo.

construct files sema_cmdbuf_gk20a.h and sema_cmdbuf_gk20a.c
under common/sync to contain the syncpt specific cmdbuf functions
for arch gk20a.

Jira NVGPU-1308

Change-Id: Iebeebe7a3de627f2de08d4ced74bb1aabf1eb53c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-25 02:46:06 -08:00
Debarshi Dutta
89c6bd2690 gpu: nvgpu: move syncpt specific cmdbuf methods to common/sync/
Syncpt cmdbuf specific functions are only for the sync functionality
of nvgpu and do not belong to fifo.

Construct files syncpt_cmdbuf_gv11b.h and syncpt_cmdbuf_gv11b.c under
common/sync to contain the syncpt specific cmdbuf functions for arch gv11b.

The word 'fifo' is also removed from the name of these functions.

Jira NVGPU-1308

Change-Id: I4253fd04b5f2ae48611ea501a9abf2b0e42a2c0e
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975921
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-25 02:45:49 -08:00
Debarshi Dutta
ebe6fa7fac gpu: nvgpu: move syncpt specific cmdbuf methods to common/sync/
syncpt cmdbuf specific functions are only for the sync functionality of
nvgpu and donot belong to fifo.

construct files syncpt_cmdbuf_gk20a.h and syncpt_cmdbuf_gk20a.c under
common/sync to contain the syncpt specific cmdbuf functions for arch
gk20a.

The word 'fifo' is also removed from the name of these functions.

Jira NVGPU-1308

Change-Id: I1a1fd1d31f7decd1398f8e2ff625f95cf1f55033
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975920
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-01-25 02:45:40 -08:00
Debarshi Dutta
8b57b3b938 gpu: nvgpu: restructure sync cmdbufs specific gpu_ops
sync cmbbuf specific ops pointers are moved into a new struct sync_ops
under the parent struct gpu_ops. The HAL assignments to the gk20a and
gv11b versions are updated to match the new struct type.

Jira NVGPU-1308

Change-Id: I1d9832ed5e938cb65747f0f6d34088552f75e2bc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975919
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-25 02:45:11 -08:00