Commit Graph

8894 Commits

Author SHA1 Message Date
Debarshi Dutta
e9a8fa028e gpu: nvgpu: disable ssync access when MIG is enabled
Disable access to ssync unit when MIG is enabled as ssync is
part of GR and not Compute. A runtime check is now added for the below
function.

gv11b_gr_intr_enable_hww_exceptions

The following priv errors are seen.

SYS write error: ADR 0x00405a14 WRDAT 0xc0000000 master 0x00000000
[ERR]  INFO 0x19400200: (subid 0x00000019 priv_level 0 local_ordering 1)
[ERR]  CODE 0xbadf1100

Jira NVGPU-6699

Change-Id: I9a08f1b6ab58affdcaa18e8ca314a4a00478a3e5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-04-20 07:47:19 -07:00
Richard Zhao
643eb158a3 gpu: nvgpu: move mapped regs to gk20a
- moved reg fields to gk20a
- added os abstract register accessor in nvgpu/io.h
- defined linux register access abstract implementation
- hook up with posix. posix implementation of the register accessor uses
  the high 4 bit of address to identify register apertures then call the
  according callbacks.

It helps to unify code across OSes.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ifcb737e4b4d5b1d8bae310ae50b1ce0aa04f750c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497937
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2021-04-19 19:45:24 -07:00
Debarshi Dutta
0a25376965 gpu: nvgpu: disable access to PE unit when MIG is enabled
PE unit belongs to GR pipeline but not compute.
Hence disabled access to the PE register in the GR Boot flow
to prevent following PRIV error when SMC mode is enabled.

PRI timeout: ADR 0x00503018 READ  DATA 0x00000000
FECS_ERRCODE 0xbadf1100
[Error Type]: decode error

Jira NVGPU-6699

Change-Id: Ia6f58258611a010252c7ead46b1b48cbf1b64001
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514894
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2021-04-19 16:19:09 -07:00
Antony Clince Alex
95bfa039f5 gpu: nvgpu: tu104: implement l2 sector promotion
Introduce new HAL gops_ltc.set_l2_sector_promotion to configure L2
sector promotion policy. The follow three promotion settings are support:
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_NONE
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_64B
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_128B

Add ioctl "NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION" to the gpu tsg node
to support l2 sector promotion. On chips which do not support sector
promotion, the ioctl returns 0.

Bug 200656177

Change-Id: Iad835a5c954d3b10da436cfafb388aaaa04f44c7
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460553
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2021-04-16 03:35:57 -07:00
Antony Clince Alex
5517e14e57 gpu: nvgpu: tu104: support regops to lts_tstg_cfg2/3 registers
In-order to support L2 sector promotion, lts_tstg_cfg2,3 registers were
added to the SYS priv save segment of the ctxsw'ed image.

Update gops_gr.decode_priv_addr HAL to include regops support to the
above two registers.

Introduce HAL ops gops_ltc.pri_is_lts_tstg_addr to detect lts_tstg
addresses.

Bug 200656177

Change-Id: I0f6c24d802edf8ac72917ed099d7ae153f6b4219
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510281
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GVS: Gerrit_Virtual_Submit
2021-04-16 03:35:52 -07:00
Sagar Kamble
ff706e5456 gpu: nvgpu: handle ctx_reload when force unbinding the channel
When force closing the channel, NEXT and CTX_RELOAD bits might be set.
Currently CTX_RELOAD bit is ignored. However, due to this, the channel
created after the erroneous unbind encounters FECS fault.

If the channel is unbound while it is running, fifo unbind error
happens and can lead to unspecified behavior.

By moving CTX_RELOAD to other channel in the TSG, the channel can be
unbound safely. In other cases, if the channel is truly running
something when it is being unbound it should either get
preempted or be handled through engine reset.

Bug 200701444

Change-Id: Iba956544dcaa1144c6064247257c64cbe9a29ae6
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515083
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2021-04-15 16:21:44 -07:00
ajesh
848d80e4d7 gpu: nvgpu: fix MISRA violation in bug
Fix the violation of MISRA Rule 8.4 in Posix bug unit.

JIRA NVGPU-6538

Change-Id: I80c8d5702a7d37ec31a49af9ad3a7876ef98e7c7
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512726
(cherry picked from commit 9c994fe5eccbd7659c557db2df7a5bdeafd9cc35)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514635
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2021-04-14 15:08:52 -07:00
ajesh
394b013911 gpu: nvgpu: address DVR comments for common.utils
Address the issues in common.utils unit which came up in DVR.

JIRA NVGPU-6595

Change-Id: I0573dc97cb33ab7f0618ed43fb60e9b950ccc086
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510296
(cherry picked from commit 3e8a049377d4f3b9ea6f41d9d21eca90bf374b52)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512609
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2021-04-13 07:13:06 -07:00
ajesh
a3958e6e66 gpu: nvgpu: address DVR comments for posix unit.
Fix the issues in posix unit as per the DVR comments.

JIRA NVGPU-6615

Change-Id: I0069824c763e80df201df12efa38531eb2399762
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510842
(cherry picked from commit 7eed91174306ba358bb9a4ad6192479d52edde15)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512606
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2021-04-13 07:13:01 -07:00
Prateek sethi
d6d1b03496 gpu: nvgpu: implement ioctls to access GPU VA ranges
Patch adds below two ioctls to access GPU VA.
- NVGPU_DBG_GPU_IOCTL_GET_MAPPINGS
- NVGPU_DBG_GPU_IOCTL_ACCESS_GPU_VA

Bug 2108651
Bug 2543387

Change-Id: Iebcfa777c1a623eda070a866aed069ca9b3ec49d
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2383317
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GVS: Gerrit_Virtual_Submit
2021-04-10 13:43:40 -07:00
Tejal Kudav
d67cea61f1 gpu: nvgpu: Move SDL err info structs to common
The SDL's error reporting code will be leveraged by central interrupt
controller (CIC) or common.cic unit.
This is a base patch to move SDL error reporting code from QNX
to common. Move the data structures used during error reporting to
common header - nvgpu_err_info.h

JIRA NVGPU-6522

Change-Id: Ie6b209323a14b9bb38e3402c2427fbcdaae52206
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504726
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2021-04-09 17:36:42 -07:00
Lakshmanan M
d4c33de919 gpu: nvgpu: Skip determine ppc config for MIG
Added a logic to skip the query ppc config when MIG is enabled.

JIRA NVGPU-5650

Change-Id: Id95d016cd3fd1e7ee283ebd9e7e8c5ee677eafd3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510884
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2021-04-07 20:16:43 -07:00
Lakshmanan M
7de19b0956 gpu: nvgpu: Add api to get the physical gpc mask
1) Added a utility api to query the physical gpc mask for a
gpu instance.
2) Expose physical gpc mask during MIG case (par with legacy case).

JIRA NVGPU-5650

Change-Id: I7efb031ac6539d8859b265f42d269233a3a421bf
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510854
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Reviewed-by: Dinesh T <dt@nvidia.com>
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2021-04-07 20:16:38 -07:00
Seshendra Gadagottu
f17d0c1c70 gpu: nvgpu: call prod programming hals for slcg ringstation units
Added following helper function to program slcg prod values for
all priv_ring units:
static void nvgpu_cg_slcg_priring_load_prod(struct gk20a *g, bool enable);

Added slcg prod value programming hals for ringstation units in above
helper function.

Jira NVGPU-6026

Change-Id: I3aedb3428ee17f27ef4fc407da18ab6a3880dda7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2501059
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Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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2021-04-07 09:22:04 -07:00
Mayur Poojary
6277d57936 gpu: nvgpu: Add new api for setting longer timeslice on dbg node
Add new ioctl api for setting longer timeslice and get timeslice
inside 'dbg' dev node.
Update ioctl gpu_get_characteristic to pass the max timeslice value
Add debugfs to access and change the max timeslice value

Bug 1842244

Change-Id: I7e80f59162cf5d90496f9752fc128f5fa8dcc7d2
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471569
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2021-04-06 04:37:38 -07:00
Prateek sethi
0335fa69ec arch: move sync unit to sub-unit of common.fifo
Currently sync unit is neither a full unit nor part of lite unit.
Treating common.sync as separate unit will trigger multiple changes
including changes to RM SWAD. Due to the reason making sync unit to
subunit of common.fifo.

Jira NVGPU-6371

Change-Id: I6f44848b58397e3870b53d9180a1bf09090490dc
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503186
(cherry picked from commit d8e3babc2c77bcfccab40e793d4ce78777011fca)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2505491
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2021-04-01 17:47:02 -07:00
srajum
a3efb4cc98 gpu: nvgpu: Hiding extra branch with nvgpu_assert(), BUG_ON() API
- A static inline for POSIX/QNX so that we can hide the branch in
  nvgpu_assert(), BUG_ON() from the branch analysis for users of this
  function.

- A macro for BUG_ON() is showing the extra branch for every instance,
  which causes huge drop in branch coverage.

JIRA NVGPU-6547

Change-Id: Iaa77df2b4d5b3d49596f05d9554604582b1209ae
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503609
(cherry picked from commit 6f36f0b47ac9911526b6c434a8cf5c4a456aeacf)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504692
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2021-03-30 19:05:21 -07:00
Rajesh Devaraj
0a713d366a gpu: nvgpu: add doxygen for macros
This patch adds doxygen for macros related to SDL unit.
Also, it removes macros related to unused service IDs.

LTC_RSTG is not present in GV11B. So, the error injection
should not be supported for LTC_RSTG. This patch moves
ltc_gv11b_debug_fusa as part of non-safety build.

JIRA NVGPU-6181

Change-Id: Iede1612f1c85e2fad80e22bcc9d10c4552c73a92
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
(cherry picked from commit 6bdd4781d8311613eebaf1cccead01823a45084e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506140
Reviewed-by: svcacv <svcacv@nvidia.com>
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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2021-03-30 07:51:36 -07:00
Antony Clince Alex
2d5d8e882f gpu: nvgpu: fix ce interrupt mask update
The CE interrupt mask update should not be skipped if the driver doesn't
implement stall or non-stall interrupt handlers. At present, the mask update is
skipped if either is not implemented causing the other to remain disabled which
is not correct.

Update nvgpu_ce_engine_interrupt_mask to always return engine interrupt mask.

Bug 200709761

Change-Id: I503338e3f4d53c1e0b85b0974d862f7b88545ef2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506292
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2021-03-29 19:02:16 -07:00
Bitan Biswas
bfa644d7fa gpu: nvgpu: fix external profile build
The config CONFIG_GK20A_PM_QOS is not set for k5.10 and kstable. Adjust
the default config selection logic.

bug 200705253

Change-Id: I9455af6bfa3d7ef68f2d4551e148ee9c67f001d0
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504877
Reviewed-by: svcacv <svcacv@nvidia.com>
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2021-03-27 08:23:53 -07:00
Divya Singhatwaria
6ffadc0e32 gpu: nvgpu: Remove hard coded constants from ACR
During code inspection use of some hard coded
constants was found in some parts of the code.
Some constants are replaced by macros and some
are declared using const keyword.

JIRA NVGPU-6260

Change-Id: I95112dfcac7c8b996789a68e7ddf78b16713a823
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485727
(cherry picked from commit b7e554267d9ef94ae5ac4529f4758127b97d3ba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492451
Reviewed-by: svcacv <svcacv@nvidia.com>
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Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
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2021-03-27 04:57:37 -07:00
Martin Radev
38e6c9ae98 gpu: nvgpu: Check for int overflow in MAPPING_MODIFY path
The check `buffer_offset + buffer_size > mapped_buffer->size` can
be bypassed with a large `buffer_size`, and that may lead to some
corruption. This patch combines the bounds checks into a more
robust one.

Jira NVGPU-6374

Change-Id: I55c8664134e763c66715bf3492867bc73686b694
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504890
Reviewed-by: Scott Long <scottl@nvidia.com>
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2021-03-26 14:20:18 -07:00
Richard Zhao
a56d93aa2f gpu: nvgpu: linux: remove definition of ecc_sysfs_stats_htable
No one uses it anymore.

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I0ea7f62e4e4e53d8da66bc00dcbe08a1f94e19a8
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497936
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2021-03-25 14:08:18 -07:00
Vedashree Vidwans
e445b57b04 gpu: nvgpu: Move interrupt ISR code to common
This is one of the steps in restructuring of interrupt code.
- Move ISR logic to common code. This will allow us to add mixed ASIL
error handling levels.
- Modify nonstall ISR to use threaded interrupts. Bottom half of
nonstall ISR will run nonstall operations instead of adding work to
workqueues.
- Remove nonstall workqueue implementation.

JIRA NVGPU-6351

Change-Id: I5f891b0de4b0c34f6ac05522a5da08dc36221aa6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467713
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2021-03-25 02:34:57 -07:00
Sagar Kamble
ecfd675d9b gpu: nvgpu: free pmu variables allocated in early_init on error in rtos_init
On error in pmu_rtos_init, pmu state was freed partly. That lead to
invalid access on subsequent nvgpu poweron. Free all pmu state in
such case.

Bug 200575409

Change-Id: I11166b55dbe00a225e811425d21500c3143a354c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503577
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2021-03-24 14:47:44 -07:00
Divya Singhatwaria
4d02580df0 gpu: nvgpu: remove ZBC save/restore by PMU
- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
  ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
  feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
  for GP10B
- Updated the GP10B PMU app version for the ucode:
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260

P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520

Bug 3233071
Bug 200696431

Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
(cherry picked from commit 9170f2b77c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500641
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2021-03-24 03:36:40 -07:00
Richard Zhao
beeec12e17 gpu: nvgpu: vgpu: add compression and fault recovery flags
It added missing flags nvgpu core introduced recently:

NVGPU_SUPPORT_COMPRESSION
NVGPU_SUPPORT_FAULT_RECOVERY

Jira GVSCI-4622

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I7eb19b9fdcb834dd479707d8e8a7d21a9640dcfa
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500558
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2021-03-23 16:43:06 -07:00
Antony Clince Alex
7f4e39aaf4 gpu: nvgpu: update pma stream teardown sequence
On nvgpu-next chips additional steps are required for pma stream teardown.
Introduce wrapper function: NVGPU_NEXT_PROFILER_QUIESCE to perform this.

Jira NVGPU-5689

Change-Id: Iafdb9c6091b468b51295827467078d24e47d5e1f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491755
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2021-03-23 04:39:20 -07:00
Antony Clince Alex
78dbec7f44 gpu: nvgpu: tu104: update CAU hal
Update CAU hal tu104_gr_init_cau to use regops.get_cau_register_stride
hal function.

Jira: NVGPU-5689

Change-Id: I7c6e933630587e2d69b92173fd8c3fa8a7021c1d
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2489388
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2021-03-23 04:39:14 -07:00
srajum
df6b305399 gpu: nvgpu: allowlist MISRA 10.3 and CERTC INT31-C QNX OS specified violations
JIRA NVGPU-6548

Change-Id: I302070bb42acbf77b6e38490615d39ae9381215f
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492668
(cherry picked from commit 80a46f6febcc03bf04e3ceff27952dc7bbfd714d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2501391
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2021-03-22 06:39:33 -07:00
Vedashree Vidwans
8ebe7ca314 gpu: nvgpu: resolve GCC 9.3 toolchain errors
Using updated GCC 9.3 toolchain results into build failure with string
functions. The updated toolchain requires strncat API to be independent
of source string length.
Update strncat used in nvgpu_worker_init_name to use destination length
only.

Bug 3270814

Change-Id: Ie50a2bed2dc09a5e34d14012e1ba878ef4ff176f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500503
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2021-03-22 02:23:48 -07:00
Sagar Kamble
ff8fbf1004 Revert "gpu: nvgpu: disable DGPU_THERMAL_ALERT for k5.9 temporarily"
Bug 200669739

This reverts commit d3f5905a0c.

Change-Id: I76a4ca4ec5be316c24410860a722a13383a3cea3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2501427
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2021-03-19 14:37:00 -07:00
shashank singh
46cdc4d5ca gpu: nvgpu: add field in characteristics struct for max gpfifo entries
Expose max gpfifo entries supported by nvgpu-rm. This limit will then be
propagated to application by nvrm_gpu.

Jira NVGPU-5846

Change-Id: Ibbbed9e1929c3bcc4eaaec9636d76e9e115e0c0c
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2482936
(cherry picked from commit b099a700aa055a5864ddb65cb546c9294c02b2b9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497486
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2021-03-19 10:09:44 -07:00
Divya Singhatwaria
cc34df76f9 gpu: nvgpu: Add support for ELPG_MS feature
- To enable ELPG_MS feature, add identifier for
  MS_LTC engine.
- The identifier is then passed
  as pg_engine_id to enable the MS_LTC engine.
- Add enable flag NVGPU_ELPG_MS_ENABLED for
  enabling/disabling ELPG_MS feature at init.

JIRA NVGPU-6430

Change-Id: Ie1f477918332d85ec98b3bd4d05b8e773d74eab8
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480750
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2021-03-18 15:29:06 -07:00
ajesh
e10f201602 gpu: nvgpu: add checks as part of BVEC analysis
Add checks in common.utils unit as part of BVEC analysis.
The check in enabled.c makes sure that unauthorized memory access
is not performed and string.c is modified with a check to avoid
a possible invocation of BUG.

Jira NVGPU-6268

Change-Id: I672c9c54a2d7b61219dee1b249b9e1345381a965
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2494951
(cherry picked from commit 464e101b23b0143ff2e26e07659e34d1678dbf9d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497647
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2021-03-17 18:23:42 -07:00
ajesh
3c519157f5 gpu: nvgpu: fix CERTC violations in Posix unit
Fix violations of CERT POS54-C in Posix unit. Check the return
status from the function pthread_cond_broadcast.

JIRA NVGPU-6535

Change-Id: I8b7cc04534c856d609b14aef80e87fe1e0884a8e
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2495485
(cherry picked from commit 778e71defa2c1860f8560e2661a055207486f3c0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497641
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2021-03-17 18:23:36 -07:00
scottl
75d98f55d7 gpu: nvgpu: add SUPPORT_MAPPING_MODIFY flags
Add new NVGPU_SUPPORT_MAPPING_MODIFY enable flag that is used to
control the value of the exported NVGPU_GPU_FLAGS_SUPPORT_MAPPING_MODIFY
flag.

These flags are currently only enabled on linux in non-virtualized
environments.

Jira NVGPU-6374

Change-Id: Ia85c353b767b4f7d0aebc04838f44996bc38c61f
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2490986
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2021-03-16 14:07:21 -07:00
Divya Singhatwaria
806ba3b870 gpu: nvgpu: checkpatch: Update for k5.10
- svcacv showed -1 for the new patches due to
  "Unescaped left brace" error.
- Literal braces need to be escaped for latest version
  of Perl(> 5.26).
- Update the checkpatch.pl, spelling.txt files and add
  const_structs.checkpatch for k5.10

Change-Id: I96dfa28d8b324bd845a9d69aed00aed5b2de7761
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2494108
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2021-03-16 06:09:34 -07:00
Sagar Kadamati
9e13fd900d nvgpu: gpu: update runlist in vserver
On QNX, Setting runlist is not happening till runlist submit. On Linux,
Setting runlist is happening at the time of channel open. due to
implimentations, which effect's channel configuration.

We need runlist for channel configuration from now.

Adding runlist parameter for below calls
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX

Bug 200701789

Change-Id: Ibd3262b43e38f54c76c4ae67ce683eccf4460cdc
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485256
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2021-03-16 06:07:30 -07:00
Sumit Gupta
e5491327fa gpu: nvgpu: fix mutex wrong acquire
Wrong acquire/release sequence.

 DEBUG_LOCKS_WARN_ON(rt_mutex_owner(lock) != current)
 ....
 CPU: 4 PID: 5404 Comm: cyclictest.sh Not tainted 4.9.201-rt134-tegra #1
 Hardware name: Jetson-AGX (DT)
 ....
 Call trace:
 [<ffffff800810e4f8>] debug_rt_mutex_unlock+0x58/0x68
 [<ffffff8008f34d0c>] rt_mutex_unlock+0x4c/0xb0
 [<ffffff8008f36ea8>] _mutex_unlock+0x20/0x2c
 [<ffffff8000f69d80>] nvgpu_cg_elcg_set_elcg_enabled+0x78/0xf0 [nvgpu]
 [<ffffff8000f7bd44>] nvgpu_intr_nonstall_cb+0x21bc/0x22f0 [nvgpu]
 [<ffffff800875b304>] dev_attr_store+0x44/0x60
 [<ffffff80082dca44>] sysfs_kf_write+0x5c/0x78
 [<ffffff80082dbd28>] kernfs_fop_write+0xc0/0x1d8
 [<ffffff8008245b60>] __vfs_write+0x48/0x128
 [<ffffff8008246b3c>] vfs_write+0xac/0x1b8
 [<ffffff800824808c>] SyS_write+0x5c/0xc8

Bug 3227296

Suggested-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Change-Id: I932a23700539422c07de045dde516c52dd8348cf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2472903
(cherry picked from commit 535e9b1dd7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2487498
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2021-03-15 14:40:19 -07:00
Antony Clince Alex
7072b39783 gpu: nvgpu: gv11b: update prop hww handling
Update prop hww handling to read and print additional diagnostic
registers.

Generate following registers:
- gr_gpc0_prop_hww_esr_coord_r
- gr_gpc0_prop_hww_esr_format_r
- gr_gpc0_prop_hww_esr_state_r
- gr_gpc0_prop_hww_esr_state2_r
- gr_gpc0_prop_hww_esr_offset_r

Rename following registers and associated fields:
- pes_hww_esr => gpc0_ppc0_pes_hww_esr
- setup_hww_esr = > gpc0_setup_hww_esr
- zcull_hww_esr => gpc0_zcull_hww_esr
- prop_hww_esr => gpc0_prop_hww_esr

Jira NVGPU-6078
Bug 2865015

Change-Id: I131c48d2375ef0a76ac6c57ff1eb019f7c113286
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2472894
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2021-03-12 04:38:04 -08:00
Antony Clince Alex
f41e5975d8 gpu: nvgpu: add ioctl to configure l2 max_ways_evict_last
Add ioctl support to configure and read the max number of lines/ways
in a L2 cache set that can be marked as EVICT_LAST. This is accomplished
through two new ltc hals: set_l2_max_ways_evict_last,
get_l2_max_ways_evict_last. These hals will only be set for nvgpu-next
chips. Incase of legacy chips, the IOCTLs will return error -ENOSYS.

Generate following litter constants to get the number of sets in a l2
slice and the number of ways in each set:
- GPU_LIT_NUM_LTC_LTS_SETS
- GPU_LIT_NUM_LTC_LTS_WAYS

Add gpu characteritics flag: NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED to
allow userspace driver to determine if L2_MAX_WAYS_EVICT_LAST ioctl is
supported.

Bug 200605474

Change-Id: Id3180f891399f5e128500f3835d762aee59953e0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445884
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2021-03-12 04:36:22 -08:00
Prateek sethi
fe03443161 gpu: nvgpu: replace hardcoded subscript with macro
size of syncpt_name is hardcoded. Patch replaces hardcoded value with
macro.

Jira NVGPU-6371

Change-Id: I7a025f8f3687e104f61e0305096ac9e48d245a48
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485732
(cherry picked from commit 6e373be0c5377b7c251787caa79934db9a389e70)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2493073
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2021-03-09 04:46:44 -08:00
shashank singh
1d86da257b gpu: nvgpu: fix some assertion/nvgpu_safe* APIs call in devctl path
Fix following issues in devctl processing path
- Remove assertion for kind>=0. It is already checked in function
  nvgpu_vm_do_map.
- Check for possible overflow of map_addr and mapping size without using
  nvgpu_safe* API for NVGPU_AS_DEVCTL_MAP_BUFFER_EX and
  NVGPU_AS_DEVCTL_ALLOC_SPACE devctl.

Jira NVGPU-6496

Change-Id: I569c89d50900100f57bc9727fd032d6cd2c331e4
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2487550
(cherry picked from commit 6d340d7e73ba8e031f50679991d259daa682a006)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492291
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2021-03-05 19:39:57 -08:00
shashank singh
b91f57d933 gpu: nvgpu: remove assert in devctl processing path
Asserting in the path of devctl processing is not safe here because
incompr_kind can be passed out of range by a malicious app and it will
cause nvgpu-rm to crash. Instead return error in case of out of range
value.

Jira NVGPU-6496

Change-Id: I9c3264776110f606a67f27ce7b01fdce82aa3021
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485752
(cherry picked from commit 689054d65fff2c61b9f1d413eef4a44a5f27fc54)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492290
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2021-03-05 19:39:46 -08:00
Vedashree Vidwans
625d942c52 gpu: nvgpu: update gops_fifo.intr_1_isr logic
Update gops_fifo.intr_1_isr to clear interrupt and return
NVGPU_NONSTALL_OPS_WAKEUP_SEMAPHORE only if channel interrupt is pending

Jira NVGPU-6222

Change-Id: I976f8bcf53c7735b154f40bb70b5f401020c8dd4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2479250
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2021-03-05 01:27:39 -08:00
Vedashree Vidwans
3b6eb25668 gpu: nvgpu: update common.ce doxygen comments
- Update function documentation
- Rename test_setup_env and test_free_env to test_ce_setup_env and
test_ce_free_env respectively. This will make sure that ce test has
independent setup and free functions.
- Add doxygen comments for nonstall workqueue operations in mc.

Jira NVGPU-6249

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I451d7b77e9a4f60fa30a9de640d423199c1a206c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2459666
(cherry picked from commit b367d3d0ea7f92b722aebdc8cf6018979fe74c47)
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2021-03-04 11:04:25 -08:00
Vedashree Vidwans
0477ce539a gpu: nvgpu: add variable range common.mc doxygen
Update common.mc API doxygen comments to add input variable ranges.

Jira NVGPU-6240

Change-Id: I512cf3a6975e745fc28b50048513a1cfe3f0b0ee
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry-picked from commit 63c1be64f4d2c07e0b5c447914bc21e827bf6d76)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2482060
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2021-03-04 11:04:20 -08:00
Vedashree Vidwans
26fc64fb0b gpu: nvgpu: update common.mc function and docs
- Update documentation for common.mc and gops_mc functions.
- Rename test_setup_env and test_free_env to test_mc_setup_env and
test_mc_free_env respectively. This will make sure that mc test has
independent setup and free functions.
- Add doxygen comments for mc.enable and mc.disable.
- Modify MC unit test description.

Jira NVGPU-6240

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I87291ee5f90b8e3c29c475c00a78c7855de5740e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457183
(cherry picked from commit c62ff36f87878a8a7513bef06e111117d96c61c8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480602
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2021-03-04 11:04:15 -08:00
ajesh
d1e836f059 gpu: nvgpu: Fix MISRA violations in Posix
Fix violations of MISRA Rule 21.2 in Posix unit.

JIRA NVGPU-6533

Change-Id: I21bb6c4c18f7a904d639bf210bcd3d29f37d69bd
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2486766
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 5239352b4acbe29a7cdb39821e68a717b132d2c9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491861
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2021-03-04 00:37:20 -08:00