To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute
on different hardware resources.
This feature requires a change in software to make it possible
to modify the virtual SM id to TPC mapping across mission and
redundant contexts.
This CL adds only SM diversity flags which are exposed to
its clients through ioctl/devctl interfaces.
Actual virtual SM id to TPC mapping implementation
will be part of upcoming patch sets.
Added NvGpu CFLAGS to identify the safety build
"CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY"
JIRA NVGPU-4133
Change-Id: I5a18256780e6726e399e39c1c8d155d2ef07d7bd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250461
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Add the following tests to target makefile:
- engine
- engine/gm20b
- engine/gp10b
- engine/gv100
- engine/gv11b
Fix build issues for unit tests on QNX safety.
Update export files to fix link issues.
Update list of required tests in JSON file.
Jira NVGPU-3695
Change-Id: I373c6c8575ed4cbf6c5597502f2ca6ec2f078ca4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253506
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HAL gops.gr.config.init_sm_id_table() initializes SM count in struct
nvgpu_gr_config. It is almost impossible that SM count is detected as
zero.
Hence remove the error check and add an assert instead.
This also helps with code coverage tests since it is difficult to
simulate error condition of having zero SMs detected.
Also, HAL gops.gr.config.init_sm_id_table() should always be defined
for each platform. Hence remove unnecessary check.
Jira NVGPU-4373
Change-Id: Ibd9b301b28d5bd2952367346a8f12fabcee2abd9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247845
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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nvgpu_mc_log_pending_intrs is debugging related function hence compile
out that and related functionality under CONFIG_NVGPU_NON_FUSA.
nvgpu_mc_intr_enable is applicable for older chips hence compile out
under CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA.
Update BUS, CE, ECC, FIFO, MC, PRIV_RING, GR, LTC, FB, PMU units'
doxygen comments based on recent ECC and MC refactoring.
JIRA NVGPU-4439
Change-Id: I337318683d6311b9c2b5748f2fb07dff29a6584f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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MIRA Advisory Rule 4.4 states that sections of code
should not be commented out.
This change removes the following unused regop type from
our regops support:
/*#define NVGPU_DBG_REG_OP_TYPE_FB (0x00000020)*/
Jira NVGPU-3178
Change-Id: I2a65c50aabf6b51072dd6fc1e344d543e3359525
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245762
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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This patch constructs the initial setup for sync unit.
There are three simple tests currently. The first test inits the
environment necessary such as regspace init, hal init. The second
step simply fails the creation of the sync and the last test is meant
as a deinit step.
JIRA NVGPU-913
Change-Id: I1db72d9833c3c4bc3c3903a7d81cce06e9983509
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248493
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- Remove non-safe TPC powergate feature from the safety
build by introducing a new flag:
CONFIG_NVGPU_TPC_POWERGATE
- Move nvgpu_init_power_gate_gr() under same compile time flag.
and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c
- Also, remove the negative test scenario and
usage of tpc_powergate from unit tests
JIRA NVGPU-4149
Change-Id: If489482401e94de499e472b16b1bc091b00992e6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242323
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FECS ucode introduces separate register lists for control registers, so
that they can be restored separately from PM state.
Added support for:
- LIST_compressed_nv_perf_sys_control_ctx_regs
- LIST_compressed_nv_perf_pma_control_ctx_regs
- LIST_compressed_nv_perf_fbp_control_ctx_regs
- LIST_compressed_nv_perf_gpc_control_ctx_regs
Bug 200507276
Change-Id: Ifce398bcb298822f3a46cf372ef9610a46a8df0c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193528
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Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.
gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.
Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.
Jira NVGPU-3968
Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247346
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Change approach to how the fault injection state is stored to facilitate
propagating fault injection state to child-threads. Rather than each
unit maintaining a thread-local object, there is a thread-local
container stored in the posix-fault-injection itself. This container is
initialized for each test module so that is independent of other other
test modules (for parallel test module execution). When child threads
are created with nvgpu_create_thread(), the fault injection container is
configured for the child.
JIRA NVGPU-3981
Change-Id: I9b580dc7f1621a7770eef8eba796f3918f2738bf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2238474
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Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.
For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.
JIRA NVGPU-4336
Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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Typically, the PMU init thread will finish up long
before the golden context image has been initialized,
which means that ELPG hasn't truly been enabled at that
point.
Create a new function, nvgpu_pmu_reenable_pg(), which
checks if elpg had been enabled (non-zero refcnt), and
if so, disables then re-enables it.
Call this function from nvgpu_gr_obj_ctx_alloc() after
the golden context image has been initialized to ensure
that elpg is truly enabled.
Bug 200543218
Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245768
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