Add NVGPU_INIT_TABLE_ENTRY for nvgpu_sw_quiesce_init_support.
Add g->sw_quiesce_init_done to avoid multiple initializations,
and check if deinit is needed in nvgpu_sw_quiesce_remove_support.
This avoids issues in common.init unit tests.
Jira NVGPU-4089
Change-Id: Ife3aa43d5f1f86899a895e4576e38ecc28a8e371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2217779
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For MMU and PBDMA faults, error notifier needs to be set
before entering SW quiesce. Otherwise it ends up with
default NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT.
Added nvgpu_rc_mmu_fault to:
- call g->ops.fifo.recover when recovery is enabled
- set MMU error when recovery is disabled
Updated nvgpu_rc_pbdma_fault to set PBDMA error when
recovery is disabled as well.
Wait for deferred interrupts to complete before actually
entering SW quiesce state, to make sure error notifier has
been set.
Jira NVGPU-4127
Change-Id: Ia84c723e021e397391c6c609d4bb96c06afdcc47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210909
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc
APIs. So, move the enum into mc.h, and replace the include of unit.h
with mc.h where appropriate. And update the yaml arch.
JIRA NVGPU-4144
Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2216106
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MISRA Rule 17.1 forbids use of stdarg.h features which are defined for
variable arguments.
This patch modifies logging macros to use slogf function for QNX builds.
This avoids use of variable argument functions used for formatting log
message.
Jira NVGPU-4075
Change-Id: I5b6bb1107a7e431afaa960003858193a477b2ee6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2192016
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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid
PRIV ring or bus access etc. Handlers for those IRQs can't access the
full state related to the IRQ unless nvgpu is fully powered on.
In order to let the IRQ handlers know about the nvgpu power-on state
gk20a.power_on_state variable has to be protected through spinlock
to avoid the deadlock due to usage of earlier power_lock mutex.
Further the IRQs need to be disabled on local CPU while updating the
power state variable hence use spin_lock_irqsave and spin_unlock_-
irqrestore APIs for protecting the access.
JIRA NVGPU-1592
Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203860
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This change eliminates MISRA Advisory Rule 18.4 violations in the
following cases:
* nvgpu_submit_append_gpfifo_user_direct()
* nvgpu_submit_append_gpfifo_common()
- use array-indexing to access gpfifo entry lists
* gv11b_gr_intr_record_sm_error_state()
- use array-indexing to access sm_error_states table
Advisory Rule 18.4 states that the +, -, +=, and -= operators should
not be applied to an expression of pointer type.
JIRA NVGPU-3798
Change-Id: I736930e4ba09a88888b0ef48f62496c4082ea5a1
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210173
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Change nvgpu_finalize_poweron() to call the subunit init functions by
using a table. The table is local to nvgpu_finalize_poweron() since the
function pointers are stored at runtime in the gk20a struct during HAL
init. The table also includes a field for checking an enable flag before
calling the init op, if required.
The primary motivation for this change is to reduce CCM for
nvgpu_finalize_poweron(). This change reduced the TCC metric from 40 to
10.
The init unit test is disabled until it can be updated to match the new
design.
JIRA NVGPU-3980
Change-Id: Ic93d3fdd185cc7feb883c898284e15b251277a8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202974
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove the second parameter for the nvgpu_bios_sw_init()
function so the function only requires the gk20a object. The
g->bios was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Id70e2b6b3a9b2705815591d02730d2d2620771c0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202972
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove the second parameter for the nvgpu_init_sec2_setup_sw()
function so the function only requires the gk20a object. The
g->sec2 was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.
JIRA NVGPU-3980
Change-Id: I22f526d961da44da64d563f5f3136c62cf9f4adf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Remove the second parameter for the pmu_early_init() and pmu_init()
functions so they only require the gk20a object. The g->pmu was always
passed for this parameter. And this makes the API signature match the
other init functions in the driver.
JIRA NVGPU-3980
Change-Id: Iae9361a5f14bc5c1d02f4ddb6583f30b71b22d59
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This change eliminates MISRA Advisory Rule 18.4
violations in the following by accessing g->fifo.channel
with array indexing:
* nvgpu_channel_init_support()
* nvgpu_channel_semaphore_wakeup()
Advisory Rule 18.4 states that the +, -, +=, and -=
operators should not be applied to an expression
of pointer type.
JIRA NVGPU-3798
Change-Id: I6b1bf360db6ec25894cc0ea430c33067e0cddf64
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207550
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The correct config to be used is CONFIG_NVGPU_SW_SEMAPHORE and not
CONFIG_NVGPU_SW_SEMAPHPORE.
Due to this the s/w semaphores were not getting freed.
Bug 200542024
Change-Id: I5eee0d52f0c1116e68a304b94e01fd407e74526e
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207182
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Improve the code complexity for the rbtree function delete_fixup().
Create smaller functions, delete_fixup_right_child() and
delete_left_child() to handle those parts of the agorithm. Also, create
helper function has_no_red_children() to handle a common check in these
new functions.
This brings the TCC metric to 7.
JIRA NVGPU-4094
Change-Id: If34167be308093ae3b597e02bbd3da8b4e9d27aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205844
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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nvgpu_kzalloc can fail in gv11b_init_eng_method_buffers.
Added checks on returned pointer.
Also changed g->ops.tsg.init_eng_method_buffers to return an int,
and check return value in callers.
Jira NVGPU-3788
Change-Id: Icb541665c40b89d512929cc9cf9f6a3e7a0033db
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205851
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Currently after sending change seq RPC, nvgpu waits for a fixed time
of 20ms.
This CL replaces this with pmu_wait_message_cond, which will return
immediately after getting change seq completion event.
Also added debug fs node to get the change seq execution time.
Bug 200545366
Change-Id: Iba283f65d4949858be9cbff88de4d21a8c92ff81
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202423
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