Commit Graph

9897 Commits

Author SHA1 Message Date
Ramalingam C
24475ad46b gpu: nvgpu: pci power management for iGPU-PCIe devices
Use the PCI power management functions for iGPU-PCIe devices.

JIRA NVGPU-9896

Change-Id: I1ac4ae67fa727e0a8e37ed2037d1417c5c19bb17
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2886799
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-14 08:20:47 -07:00
Austin Tajiri
24bebfabaf gpu: nvgpu: add engine base vector HALs
Add HALs for getting the base vectors for stall and nonstall engine
interrupts. The engine interrupt IDs are added to these base vectors
to determine the engine stall and nonstall interrupt vectors.

Jira NVGPU-9217

Change-Id: Ieaf0e75caac0f7e23684b80466fbf1dc3a57f68d
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880426
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-13 22:16:13 -07:00
Shashank Singh
21cb70f58d gpu: nvgpu: remove kind control capability
Kind is controlled by nvgpu userspace library so related capability
flags can be removed from kernel and uapi interface.

Jira NVGPU-9832
Bug 4034184

Change-Id: Id2b0a4e1cd784638362116b8d99177467fba998b
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880391
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-13 12:21:46 -07:00
Austin Tajiri
56a4680a3b gpu: nvgpu: refactor gr.intr.handle_sw_method
- Add defintions of the gfx/compute classes and methods that are
  generated from the hw/sw class header files. Use these definitions
  instead of the hard-coded ones so that mismatches may be caught by
  the HAL checker.
- Abstract out the sw method handling functionality of
  gr.intr.handle_sw_method into gr.intr.handle_gfx_sw_method and
  gr.intr.handle_compute_sw_method and have gr.intr.handle_sw_method
  call these two new HALs.

Jira NVGPU-9217

Change-Id: Ia30fcba6174878d9b5b7b5910c564c879a702ddc
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2885547
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-13 12:20:33 -07:00
Divya
7a4fff4b17 gpu: nvgpu: add hal for pmu sequence cleanup
- On older chips, PMU uses CMD-MSG queue method to
  communicate with NvGPU.
- From Turing onwards, PMU uses RPC method for this.
- During poweroff, we release pmu_sequence and reset the
  members of the structure.
- For chips that use RPC, we need to free the payload as well
  and then reset the members.
- Add pmu_seq_cleanup hal for this.

Bug 4019694
Bug 4059157

Change-Id: Ieb474fe4ed81f54d78480214cde53b51d45652c6
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882267
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-12 16:28:52 -07:00
Divya
db9a411a06 gpu: nvgpu: sync free of rpc_payload
- During driver unload, shutdown or RG path as part of
  pmu destroy, pmu sequences have to be cleaned up to
  free payload memory and allocation info which is stored
  as part of pmu_sequence.
- While doing so there can be race condition with pmu_isr
  or nvgpu_pmu_rpc_execute path where it waits for fw ack.
- This race condition can lead to freeing of payload memory
  before nvgpu_pmu_sequences_cleanup() does.
- This can lead to memory corruption or double free issue
  when the cleanup code again tries to free the payload mem.
- To resolve this add a new function nvgpu_pmu_seq_free_release()
  which will check for seq->id in pmu seq tbl before freeing the
  memory and other info from pmu_sequence.
- Use this nvgpu_pmu_seq_free_release() in non-blocking RPC calls
  and also when fw ack fails or driver is dying scenario.
- For blocking call, synchronise freeing of rpc payload memory by
  using a new boolean seq_free_status.

Bug 4019694
Bug 4059157

Change-Id: Id45a6914a2d383a654539a87861c471a77fb6850
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2882210
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-12 16:28:41 -07:00
Ramalingam C
b2c4cdb25b gpu: nvgpu: sim init for iGPU-PCIe
Implement the sim init for the iGPU-PCIe devices.

JIRA NVGPU-9348

Change-Id: I9088308b96c57bb1cea01959326446ccad0a8c24
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2851163
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-10 20:45:50 -07:00
Prathap Kumar Valsan
d0ed86ab1e gpu: nvgpu: update PT lvl array to six levels
Increase the size of page table level array to index six levels.

Jira NVGPU-9760

Change-Id: I482639fd028ecd504ee8bc313c39f3bd710e81a9
Signed-off-by: Prathap Kumar Valsan <prathapk@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868918
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-07 21:08:45 -07:00
Kishan
c6d5fb348c gpu: nvgpu: Capture thread name for every channel created
This change ensures that in scenarios where GPU enters a bad
state because of the work submitted by a misbehaved thread,
we should be able to capture thread name as part of our
1st set of failure logs.
Changes for QNX env is pending.

JIRA NVGPU-7783

Change-Id: I65d55a6ade749ff91739458e0642ed2dafaae5cc
Signed-off-by: Kishan <kpalankar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2879197
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-06 10:12:48 -07:00
Ramalingam C
af48120169 gpu: nvgpu: configure CWD sm id regs before ucode load
GPCCS ucode is expecting the SM ID programmed in GPM and CWD registers
to be in sync. So create a hal called gr.init.load_sm_id_config()
for the sm_id programming for the CWD registers and invoke them before
the ucode load.

Initialize this hal only for the required GPUs.

JIRA NVGPU-9757

Change-Id: Ib0984fd6326c37e0c2a06123041032575a23ec04
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2864999
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-06 10:09:14 -07:00
Timo Alho
3ff15b69de gpu: nvgpu: fix return value check of MRQ_STRAP
The return value of tegra_bpmp_transfer() API is only for a low level
wire-protocol errors. When checking BPMP-FW response to MRQ_STRAP
request, the return value in the MRQ response payload need to be
checked.

Bug 3744064
Bug 3317279

Signed-off-by: Timo Alho <talho@nvidia.com>
Change-Id: I165431a5d2ed5a09965eb84b7ee09766bb09d091
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859267
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-06 00:41:59 -07:00
Ramalingam C
7ba33f3dec gpu: nvgpu: Handle iGPU in pci probe and remove
When iGPU is probed as pci device, power and clocks are driven from the
platform, hence the pci_probe and pci_remove to handle both
iGPU and dGPU. Also enable the runtime PM for the PCI-iGPU
device.

JIRA NVGPU-9348

Change-Id: Id5dd88dc0c905655f9174ecd7936bdf2996f06e6
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-05 05:53:03 -07:00
Ramalingam C
ebb60b7f5e gpu: nvgpu: Add a flag CONFIG_NVGPU_PCI_IGPU
To support the pci probe for the integrated GPU, add a new config
flag called CONFIG_NVGPU_PCI_IGPU.

This will help us in compiling the pci related files for igpu safety
builds too

JIRA NVGPU-9348

Change-Id: I1824060db56b2cf555d4ad55bd870f3a20c95741
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835339
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-05 05:52:52 -07:00
Shashank Singh
28cbdcde73 gpu: nvgpu: remove partial mapping capability flag
Remove NVGPU_SUPPORT_PARTIAL_MAPPINGS kernel flag and the
corresponding uapi gpu charaacteristics flag
NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS. This functionality is
supported by fixed mapping ioctl by default.

Jira NVGPU-9832
Bug 4034184

Change-Id: Ie887c753f152afb6a4a1e4aafb5f8f6fd3b7b398
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2879793
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-04 21:51:24 -07:00
Austin Tajiri
7cab0e7124 gpu: nvgpu: add ltc.intr.retrigger HAL
Add an ltc.intr.retrigger HAL for chips that need to retrigger pending
interrupts in the LTC ISR.

Jira NVGPU-9217

Change-Id: I1fe74c2f72afc7cf852cf0d273c7a8f8652a53c9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869902
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:42:26 -07:00
Austin Tajiri
db22d49239 gpu: nvgpu: add LTC interrupt register HALs
Add HALs for reading and writing LTC interrupt configuration registers.

Jira NVGPU-9217

Change-Id: I2d3a913ae5e69009d7888495af9b79acb4960ac9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869901
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:42:20 -07:00
Austin Tajiri
b1ac11e0e0 gpu: nvgpu: add ltc.intr.handle_illegal_compstat HAL
Add ltc.intr.handle_illegal_compstat to handle the case in which a chip
does not support the ILLEGAL_COMPSTAT LTC interrupt.

Jira NVGPU-9217

Change-Id: I40ddcbda6176ffa36037bd1998af4ec1bed67ec9
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869900
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:42:14 -07:00
Austin Tajiri
3a69b445fc gpu: nvgpu: fix MMU fault register mismatches
Fix the following MMU register mismatches by using the appropriate HALs
when possible:
 - fb_mmu_fault_status_r
 - fb_mmu_debug_ctrl_r

Jira NVGPU-9217

Change-Id: I3380ac449f20f2ce47b439303b9abd19010e6b26
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869899
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:42:08 -07:00
Austin Tajiri
f2ce282b7e gpu: nvgpu: add HALs for ECC interrupt handling registers
Add HALs for reading ECC status, retrieving ECC error info, and clearing
ECC errors. Use these HALs in place of direct register access in
GV11B/GA10B ECC interrupt handlers.

Jira NVGPU-9217

Change-Id: I792f05ede5576b958b678bc5eb8f2b8dc5e7c4d7
Signed-off-by: Austin Tajiri <atajiri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869898
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:42:03 -07:00
Santosh BS
a7caa8da79 gpu: nvgpu: fix misra dir 4.6 and rule 20.7
Fix below misra violations:

directive_4_6_violation: Using basic numerical type "int" rather than
                         a typedef that includes size and signedness
                         information.
rule_20_7_violation: Macro parameter expands into an expression without
                     being wrapped by parentheses

Bug 3763551

Change-Id: I74f2edaef0b21369b76afd596b69157123eca261
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868944
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: V M S Seeta Rama Raju Mudundi <srajum@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-04-04 21:41:34 -07:00
Laxman Dewangan
f5b50fec4d nvgpu: Add out-of-tree headers path when building as OOT module
It is required to build nvgpu as separate module from OOT modules
because its source will be continue to be in different repository.
The nvgpu module will depends on the headers and symvars from
core kernel and OOT modules.
Add the path of headers of OOT modules when compiling the nvgpu as
OOT module.

Bug 4038415

Change-Id: I0f42c8e75ca63784c9d9ba3624e5ed0141e1df77
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880466
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-04-01 10:56:05 -07:00
Sagar Kamble
821699d3a3 gpu: nvgpu: unset async subctx VM with correct index
On deleting the subcontext, tsg->subctx_vms[] entries are set to NULL as
per the subcontext id. For async subcontexts the index logic was used
from that of tsg->async_veids bitmask. However subctx_vms is an array
shared by all subcontexts hence index should be subcontext id aka veid.

Also update the description of function nvgpu_tsg_validate_ch_subctx_vm
as some of the functionality is now moved to another function
nvgpu_tsg_create_sync_subcontext_internal.

Bug 3979886

Change-Id: Ic290fb175b34988c6ffabe9c9dc4ec124d2c70af
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2879025
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-31 13:33:45 -07:00
Sagar Kamble
410d3603ff gpu: nvgpu: update dmabuf locking
All drivers that use dma-bufs have been moved to the updated locking
specification wherein dma-buf reservation is to be locked while
accessing the dmabuf internal data. Lock is removed. So lock
the resv object onwards while updating dmabuf private data
used for compression and buffer metadata.

With this, we can enable compression for all kernel versions that
was disabled earlier for v6.2+ kernels.

Bug 3974855
Bug 3995618

Change-Id: Iece3ab57912d0420d4bc5c07d2c0d2e03ff19292
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2877633
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-31 13:32:58 -07:00
Sagar Kamble
a5640d61bd gpu: nvgpu: free VEID if the channel is closed
In case of process crash or forceful closure of the channels, userspace
may not release the VEID. In that case, creating further subcontexts
may not be possible.

Hence, when the channel is closed forcibly (linux), release the VEID on
closure of the last channel in the subcontext.

With this, normally on linux, channel close will not relase the VEID
However, on qnx it will release the VEID. So delete subcontext devctl
call on qnx will be nop in normal case hence changed the error print
and error return to success.

Also added check in the subcontext delete ioctl fn that all channels
are unbound before deleting the subcontext. This is to ensure that
channels don't refer to dangling subcontext pointer.

Bug 3979886

Change-Id: I434944b01740720011abce3664394ae8cb0d4e2e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858060
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-31 13:25:53 -07:00
Sagar Kamble
53dc53a8b4 gpu: nvgpu: add hal to get the bar2 vm size
On ga10b+ platforms, more VM space is needed to map various buffers
to bar2 vm. Engine method buffer is mapped for each pbdma and for
maximum supported TSGs this requires more than 32MB of space.
Also we need to consider fault buffer space and vab buffer
space requirement.

Bug 3958581

Change-Id: I9ee87119f762352ee12859b71c08a5f75b3554e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872811
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-25 02:45:47 -07:00
Santosh BS
2a865e3aad gpu: nvgpu: NVENC support on TU104
This patch adds nvenc support for TU104
- Fetch engine/dev info for nvenc
- Falcon NS boot (fw loading) support
- Engine context creation for nvenc
- Skip golden image for multimedia engines
- Avoid subctx for nvenc as it is a non-VEID engine
- Job submission/flow changes for nvenc
- Code refactoring to scale up the support for other multimedia
  engines in future.

Bug 3763551

Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0
Signed-off-by: Santosh BS <santoshb@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-24 17:07:49 -07:00
Ramalingam C
faf6ff3f34 gpu: nvgpu: Add pci driver support for NVGPU_NEXT_PCI_DEVICES
Add the NVGPU_NEXT_PCI_DEVICES and NVGPU_NEXT_PCI_IDS into the list
of the pci devices and pci ids.

JIRA NVGPU-9348

Change-Id: I3d42eebc1a61f8821ef1f0f9a93262a4d84e8650
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2835338
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
2023-03-24 17:05:47 -07:00
Jon Hunter
9b58826f97 gpu: nvgpu: Fix build for Linux without virtualization
L4T does not support virtualization currently and so we should be able
to build NVGPU without virtualization support. This avoids having to
build many virtualization drivers for Tegra.

The build flag CONFIG_TEGRA_VIRTUALIZATION was added for building
out-of-tree drivers to select if virtualization is enabled or not. This
is enabled by default. However, if this is not set, then driver should
still build. Currently, NVGPU is not building when
CONFIG_TEGRA_VIRTUALIZATION is not set because
CONFIG_TEGRA_GR_VIRTUALIZATION is now always enabled for NVGPU. Fix this
by wrapping CONFIG_TEGRA_GR_VIRTUALIZATION with
CONFIG_TEGRA_VIRTUALIZATION.

Jira GVSCI-16046

Change-Id: I5448ad73d4d4e3e151ef216a7fcf0469890fd5ec
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868502
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-22 03:25:42 -07:00
Sagar Kamble
dc0dc2e96a gpu: nvgpu: refcount ctrl node with tsg open and close
Since tsg close refers to the ctrl node to revoke the share tokens, need
to ensure that ctrl node remains active until after contained tsgs are
released.

Bug 3946749

Change-Id: I3b514f6d2a041cbf3d517f846f202f956747d726
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872115
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-21 09:46:05 -07:00
Martin Radev
ac9a59075e gpu: nvgpu: Print flags after all flags are set
Without this change, nvgpu would print out some
flags as disabled in dmesg but enable them shortly after.
This leads to confusion when examining UMD and nvgpu
reporting in UMDs.

This patch adds code to print out the flags after
all flags are set.

Bug 4031904

Change-Id: I67b9a4567886fd5e076f7ac3b8f284b52c03d7e4
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2871606
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 09:45:13 -07:00
Rajesh Devaraj
8d091a4548 gpu: nvgpu: add pce_map_value gops for ce
This patch adds pce_map_value gops for CE.

JIRA NVGPU-9329

Change-Id: Ic1e599b8e23e46a537daa92aa9601953eb826997
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2861879
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 09:37:15 -07:00
vivekku
d5e00ef380 gpu: nvgpu: hal: enable gsp scheduler
- enable gsp scheduler for orin silicon platforms
- disabled gsp scheduler for simulation and enabled KMD scheduler

Bug 3935433

Change-Id: I38cb35937ffb25b76fbf37fa4eeb9e993f0370c5
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872897
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 02:38:01 -07:00
srajum
02834f8739 gpu: nvgpu: fix CERT-C issues
- CID 10165014
  Dereference before null check

- CID 10166579
  Unused value

Bug 3952896

Change-Id: I6a7f2b97b4a6519272607e560d09c138048bd665
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2872276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 02:37:08 -07:00
Richard Zhao
f791adf880 gpu: nvgpu: move .runlist.hw_submit to use runlist_id
Use detailed function parameters runlist_id, iova/aperture and count, so
the HAL could be reused on server side.

Jira GVSCI-15773

Change-Id: I28f68682b9eea4e798af5c850c87840bd9b79970
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 02:31:29 -07:00
Richard Zhao
a587d94f5a gpu: nvgpu: init nvs scheduler for vf
nvs does not have a clean cut. runlist submit path uses nvs worker no
matter whether the feature is enabled.

Jira GVSCI-15773

Change-Id: I6f6db1e766b8079ad6ca4a6b530b3ec27094f840
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863443
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-21 02:31:21 -07:00
Richard Zhao
da1da8f563 gpu: nvgpu: move .preempt_trigger/.is_preempt_pending to IDs
.preempt_tsg uses .preempt_trigger/.is_preempt_pending, so they both
have to use runlist_id and tsgid too.

Jira GVSCI-15770

Change-Id: Ida24d160c362ea1348d7c19e6d0352bb390d0a64
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863442
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 02:30:57 -07:00
Richard Zhao
8f5adab299 gpu: nvgpu: .preempt_tsg move to use runlist_id/tsgid
It's for making .preempt_tsg reusable on server side.

Jira GVSCI-15770

Change-Id: Id9f477baa29cb63fb0e1d1650f4b1e6a2fa248c0
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863441
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-21 02:30:49 -07:00
Jon Hunter
f20a5b412c gpu: nvgpu: Fix vgpu build with compression disabled
When building VGPU with compression disabled, then build fails as
follows:

 error: ‘struct gk20a’ has no member named ‘max_comptag_mem’
   505 |  gk20a->max_comptag_mem = totalram_size_in_mb;                                                                                                                                                                                              |       ^~
 error: implicit declaration of function ‘gk20a_dma_buf_priv_list_clear’
  [-Werro r=implicit-function-declaration]                                                                                                                                                                                                       523 |  gk20a_dma_buf_priv_list_clear(l);                                                                                                                                                                                                          |  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Fix these build failures by guarding the applicable code with
CONFIG_NVGPU_COMPRESSION.

Bug 4014315

Change-Id: I8c7287ab57ef513ba11a3d85c2edfce243f07418
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869169
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-18 16:19:00 -07:00
Rajesh Devaraj
4f96f59c15 gpu: nvgpu: perform support_ls_pmu check
Perform support_ls_pmu check before dereferencing pmu from gpu struct g
to avoid the possibility of kernel panic when LS PMU support is not
enabled.

JIRA NVGPU-9283

Change-Id: I65caac449f884164d797dedc2041d6ee4292e326
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868250
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
2023-03-17 10:04:59 -07:00
Richard Zhao
4ec683975a gpu: nvgpu: obj_ctx: fix possible mem leak
When generate golden image, subctx_mask memory was not freed on fail.
It was detected by code coverity checker.

Bug 3952896

Change-Id: Iae0c78b11003980c6b09ec0e72bebfda0a244b17
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2868150
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 10:04:45 -07:00
Jon Hunter
9bf41e7ae6 gpu: nvgpu: Fix build for Linux v6.3
Upstream Linux commit bc292ab00f6c ("(HEAD) mm: introduce vma->vm_flags
wrapper functions") breaking building the NVGPU driver because the
vm_flags variable is made a const and can no longer be set directly. Fix
the build for Linux v6.3 by using the helper functions for setting the
flags.

Bug 4014315

Change-Id: Ie58d1f43b59167869742ff01ffe4e1841dbb1d6e
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2867167
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 10:03:54 -07:00
prsethi
505690f505 gpu: nvgpu: add validation check for domain name
Currently there is no validation checks for domain name used in domain
create command which can cause some security risk.
Patch enable the validation for domain name by only allowing char from
([a-z], [A-Z], [0-9], -, _) list.

Bug 3994374

Change-Id: Ia2cb6f533ed136e74e7a72934ad5267803d1236d
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2871515
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 04:17:14 -07:00
Richard Zhao
41823694a3 gpu: nvgpu: add .init_golden_image HAL
golden image is created differently on native and VF.

Jira GVSCI-15772

Change-Id: I8d78d1214d8aac1d39d6529b68adef1dd6f8a516
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863440
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 04:04:33 -07:00
Richard Zhao
067e3590d5 gpu: nvgpu: runlist: init engine info of runlist for VF
- init engine info for VF which is needed to setup ramfc
- avoid register access in nvgpu_runlist_get_device_id. It could use
rleng_id.
- alloc physical addressed memory for vf runlist mem.

Jira GVSCI-15773

Change-Id: I63494b306a2f56d090a61ea1fa581083224d1cb6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863432
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 04:04:21 -07:00
Richard Zhao
64e22ee54b gpu: nvgpu: vgpu: add rleng_id to constants
rl_eng_id is used to construct ram_fc_target_w. VF creates inst_block
and ramfc on client side.

Jira GVSCI-15769

Change-Id: Id641e644e829bfaf6a3bb0bb758c142f0a514db3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2863431
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 04:04:09 -07:00
atanand
9dd2a8fc73 gpu: nvgpu: Get GA10B EMC floorsweeping status
The memory bandwidth reported by the nvgpu driver is a resultant of FBP and EMC floorsweeping status. The FBP floorsweep status was already getting reported in the GPU characterstics so the status of EMC was fetched and reported in this change.

Jira NVGPU-9609
Bug 3661074

Change-Id: Ia2fe6cb029d086765da15d9e964ea77256e06604
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859237
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 04:00:00 -07:00
vivekku
ce4293ab20 gpu: nvgpu: gsp: disabling multiple gsp firmware read
Changes:
- disabled gsp firmware release during railgating
- firmware read happen only during power on

Bug 3935433

Change-Id: I9156c015ab7f90ab640c33ca99dc7f3e289b7659
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2870170
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 03:56:36 -07:00
vivekku
eb52414f22 gpu: nvgpu: ga10b: disable gsp scheduler
Changes:
- disabling gsp scheduler

Bug 3935433

Change-Id: Iedb049b0ad1f052e8b3d1692d9280e80dcee9163
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2869839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 03:56:24 -07:00
vivekku
da78da60f3 gpu: nvgpu: Makefile: Enabling gsp sched flag
Bug 3935433

Change-Id: Ib265adf561a09ede25d481f13e9c06b773976030
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2860795
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 03:56:08 -07:00
vivekku
9773e7ca68 gpu: nvgpu: gsp: erase queue command for safety scheduler
Changes:
- implemented erase queue command for safety scheduler to depopulate
control fifo parameters in safety scheduler FW.

NVGPU-9590
Bug 3935433

Change-Id: I2cd6cd967ac4dba61992dd285e45b18f34dda2ca
Signed-off-by: vivekku <vivekku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2858533
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2023-03-17 03:55:31 -07:00