The delay value used in gr usleep_range calls is
too high. We can start at a much lower value.
Change-Id: Id141df70b8892bc1ed1b49623c4aa125d541a636
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/715928
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Currently new gpu rail gating delay is not effective
until next gpu rail gate and ungate. To make new
rail gate delay effective immediately, wakeup gpu after
setting new delay.
Change-Id: I80889687e9d3d577ea783cdf5688074c06d602cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/714961
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Introduce mem_desc, which holds all information needed for a buffer.
Implement helper functions for allocation and freeing that use this
data type.
Change-Id: I82c88595d058d4fb8c5c5fbf19d13269e48e422f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/712699
Bug 200066741
As we are just getting out of reset and this reg is not
written before, so we dont stand the risk of loosing
any data
Change-Id: Ifc1bcaa3c224038e4e2a47882a4523f7633cb660
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/715652
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
New members are added in nvgpu_gpu_characterstics to export more
information required specially from CUDA tools.
Change-Id: I907f3bcbd272405a13f47ef6236bc2cff01c6c80
Signed-off-by: Sujeet Baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/679202
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
The current CUDA drivers have been using the regops to
directly accessing the GPU registers from user space through
the dbg node. This is a security hole and needs to be avoided.
The patch alternatively implements the similar functionality
in the kernel and provide an ioctl for it.
Bug 200083334
Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/711758
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
We currently have below exceptions enabled but we do
not have any handler for them. So if any of these
exception is raised, we do not clear it.
NV_PGRAPH_EXCEPTION_PD
NV_PGRAPH_EXCEPTION_SCC
NV_PGRAPH_EXCEPTION_DS
NV_PGRAPH_EXCEPTION_MME
NV_PGRAPH_EXCEPTION_SKED
Hence do not enable above exceptions.
Bug 200078514
Change-Id: I0dd3a2299f80f3fe06994818f64151e7cc83a84e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/714166
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
In gk20a_gr_isr(), handle memfmt exception as below :
- read NV_PGRAPH_PRI_MEMFMT_HWW_ESR
- debug print for contents of above register
- write same value back to NV_PGRAPH_PRI_MEMFMT_HWW_ESR and
clear the exception
Bug 200078514
Change-Id: I5b9afacd7f99b5a37de953041582b3a53b863642
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713713
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Timestamps read in an interrupt handler and when fence state
is being updated can differ by variable amount. That
add unnecessary jitter to original interrupt times.
This patch adds support for passing timestamp from the device
driver thereby allowing more accurate timestamps.
Bug 1543760
Change-Id: Idcfd5cb435b0bd585e3c16cd299c6f456d4509c4
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/360939
First, defining a new structure to support gk20a
power domain. Then making necessary modifications
to add so as to add DT support for gpu power-domain.
bug 200070810
Change-Id: I29e1c24b181e14743d3969103abfd1882d171f07
Signed-off-by: Sumit Singh <sumsingh@nvidia.com>
Reviewed-on: http://git-master/r/668973
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Added support for dumping vpr/wpr info for gm20b.
This dump info called when ever gk20a_mm_fb_flush
is timed-out.
Bug 200082817
Change-Id: I21b0372d0e3f976a189c9c428c015165b715bf88
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/711439
(cherry picked from commit b69897d71c8f6119b49ceb8d3273cdb354178cc5)
Reviewed-on: http://git-master/r/712675
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Use busy looping for l2 tag flush and elpg flush
operations. This is making total flash time more
accurate and reduced overall time compared with
usleep. Also added trace points to measure
performance for these operations.
Also corrected timeout error check for non-silicon
platforms.
Bug 200081799
Change-Id: I63410bb7528db9258501633996fbdee5fdec1c74
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/710472
(cherry picked from commit 18684cf9d5d6870a1a1fd5711c4fc2d733caad20)
Reviewed-on: http://git-master/r/710986
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Allow enabling of PC sampling hardware workaround. It is only
applicable to gm20b.
Bug 1517458
Bug 1573150
Change-Id: Iad6a3ae556489fb7ab9628637d291849d2cd98ea
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/710421
The server does an implicit TLB invalidate after map and
unmap operations.
Bug 1616964
Change-Id: Ib6f4a23389f1e5d796d0f4b0be312f438c52927c
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/713221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add "force_reset" flag to __gk20a_do_idle()
For real world use cases like VPR resizing, we cannot wait
for railgate_delay (which is 500 mS). Hence use CAR reset
for this use case. (this is done via gk20a_do_idle() API
with force_reset = true)
Some of the test cases make use of sysfs "force_idle" and
they expect GPU to be into really railgated state and
not in CAR reset.
Hence when called from sysfs, set force_reset = false.
When global flag "force_reset_in_do_idle" is set, it will
override local flags and force CAR reset case.
This is desired in cases where railgating is not enabled
Also, set force_reset_in_do_idle = false for GM20B since
railgating has been enabled for GM20B
Bug 1592997
Change-Id: I6c5af2977c7211ef82551a86a7c1eb51b8ccee60
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/711615
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix below sparse warnings by making below APIs static :
kernel/drivers/gpu/nvgpu/gk20a/mm_gk20a.c:1795:5:
warning: symbol 'update_gmmu_pde_locked' was not declared. Should it be
static?
kernel/drivers/gpu/nvgpu/gk20a/mm_gk20a.c:1841:5:
warning: symbol 'update_gmmu_pte_locked' was not declared. Should it be
static?
Bug 200067946
Change-Id: I8158aaf503378b176cfd5cc129db9557803003c1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/713024
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Below check assumes that available syncpt range
starts from 0
id >= nvhost_syncpt_nb_pts_ext()
Instead of using this API, use nvhost_syncpt_is_valid_pt_ext()
which validates the syncpt id against both upper and lower
boundaries
Bug 1611482
Change-Id: I7c4465a2bc84b63fefaa17c64f02582885924c5e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/711211
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
-CDE firmware v0 is not used anymore so we can remove support for
it.
-Bump the threshold for a large surface warning to 8k.
Bug 1566740
Change-Id: Ia0434a04cdd453a10a8de08d259e92e6b9a3e964
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/709452
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add a big mutex for protecting the channel during ioctls, in case the
userspace uses the same channel from several threads at once. The lock
is taken during all operations except CHANNEL_WAIT, which could deadlock.
Bug 1603482
Change-Id: Ibed962eadc9f00645abd54413dde9aaee00377ab
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/678871
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
don't unmap compbits_buf explicitly from system vm early but store it in
the dmabuf's private data, and unmap it later when all user mappings to
that buffer have been disappeared.
Bug 1546619
Change-Id: I333235a0ea74c48503608afac31f5e9f1eb4b99b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/661949
(cherry picked from commit ed2177e25d9e5facfb38786b818330798a14b9bb)
Reviewed-on: http://git-master/r/661835
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Pass always the directory structure to mm functions instead of
pointers to members to it. Also split update_gmmu_ptes_locked()
into smaller functions, and turn the hard
coded MMU levels (PDE, PTE) into run-time parameters.
Change-Id: I315ef7aebbea1e61156705361f2e2a63b5fb7bf1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672485
Reviewed-by: Automatic_Commit_Validation_User
CUDA devtools need to be able to flush the GPU's cache
in a sideband fashion and so cannot use methods. This
change implements an nvgpu_gpu_ioctl to flush and
optionally invalidate the GPU's L2 cache and flush fb.
Change-Id: Ib06a0bc8d8880ffbfe4b056518cc3c3df0cc4988
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/671809
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Disable GO_IDLE timeout when pushing SW methods. This stops FE_GI bit
from getting enabled, so remove polling for that, too.
Change-Id: I695aa9fbc68d4fe722ae46a28d7f4cc05db75b3b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709878
Map/unmap buffers for HWPM and deal with its instance block, the minimum
work required to run the HWPM via regops from userspace.
Bug 1517458
Bug 1573150
Change-Id: If14086a88b54bf434843d7c2fee8a9113023a3b0
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/673689
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Call validate_reg_ops() even when allow_all is set, since that function
takes care of counting ctxsw regops which would not be executed without
the counters set.
Bug 1517458
Change-Id: Ie6173229fb6580e8812b7d2a52bfa8661f3d95e5
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/709439
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
bug 200069748
Invalidating FECS code instblk is required only if
FECS uses bootloader to load. Added check for same
instead of using PMU support to invalidate.
Handle elpg enable/disable call in case PMU is OFF.
Change-Id: I28abbbbe1f22edd9e0417df9d0e831bbd770502c
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/670664
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Tested-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Dump GR status registers in case of ctxsw timeout.
This is helpful in case where ctxsw timeout is encountered
during stress testing but we lose the bad state since we do
the recovery. So dump as much status as we can when timeouts
are seen
Bug 200062436
Change-Id: Ie7d320cefa7b272f2cc607cdb5c01ba1f43ba1f2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/708465
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
We have infinite timeouts for loops in emulation. Some functions with
the loops still return error if we exceed the original retry count.
Change-Id: I1f9ddbfc0acd9f30f6bd49d9e748d8d8fbefa154
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709491
Introduce a new struct gk20a_mm_entry. Allocate and store PDE and PTE
arrays using the same structure. Always pass pointer to this struct
when possible between functions in memory code.
Change-Id: Ia4a2a6abdac9ab7ba522dafbf73fc3a3d5355c5f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/696414
fd_install() should be called only once all other initialization is
done and no errors can happen.
Bug 1589104
Change-Id: I822511a64d4c6fa59c8e772a896dbd6818459c97
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/706928
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
The GVA was increased to 128GB but for vgpu, the split
was not updated to reflect the correct small and large
page split (16GB for small pages, rest for large pages).
Bug 1606860
Change-Id: Ieae056d6a6cfd2f2fc5066d33e1247d2a96a3616
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/681340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add below APIs to dump various GR status registers
1. debugfs : /d/gpu.0/gr_status
Read this debugfs at runtime to get status registers
2. API gk20a_gr_debug_dump()
Add this API in code to dump registers at any point
Bug 200062436
Change-Id: Ic1115b5a2fc16362954b5ed8a9e70afb872a8d91
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/486465
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
bug 200078367
using udelay for fecs status polling
during GR init phase brings down fecs
transaction time to < 20usec from few
hundred usec.
Change-Id: I61a27daaf1187ac086a42779b46aa3fbee3b37f2
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/691918
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
