- Added status check for nvgpu_pmu_disable_elpg() return value
& prints error information upon failure.
- Below CID's are due to missing status check of function
nvgpu_pmu_disable_elpg() return value, so this CL helps to fix it
2624546
2624547
2624548
Bug 200291879
Change-Id: I263fc6bc9e2667af478bfd7160fe205167556f99
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565998
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
clk_pmu_freq_controller_load used the default mask and affected
all the clock frequency controllers (CFC) which had their bits
set in the mask. We wish to enable/disable the CFCs in isolation
through debugfs. So we add a parameter(bit_idx) to the function
which will help affect only one CFC at a time
JIRA DNVGPU-207
DEPENDS ON: <http://git-master/r/1563302>
Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563303
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Develop a file heirarchy to hold clock frequency
controller(CFC) related debugfs nodes.
/gpu_root -> /clk_freq_ctlr
-> sys
-> ltc
-> xbar
-> gpc
Reading the file should tell if the particular
CFC is enabled(1) or disabled(0). Write 0 to
the file to disable the CFC and 1 to enable the
CFC. We can write 0 to all the files to disable
all CFCs.
JIRA DNVGPU-207
DEPENDS ON: <http://git-master/r/1563303>
Change-Id: I845a4aab8b1195b24fe2377a697c1de0cfe9ecfd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563302
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Reading gr_pri_fe_chip_def_info_r() during
gv11b_init_fifo_setup_hw on RTL platforms is giving
"0xbadf1201" error because fecs part of priv ring
is still in reset. This needs to be fixed after
identifying relevant engine that needs to be
brought out of reset. Until that time, use constant
value from hw definition(whose value is 64):
gr_pri_fe_chip_def_info_max_veid_count_init_v().
Bug 1983643
Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568139
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Added new defines for following litter values:
GPU_LIT_SMPC_PRI_BASE
GPU_LIT_SMPC_PRI_SHARED_BASE
GPU_LIT_SMPC_PRI_UNIQUE_BASE9
GPU_LIT_SMPC_PRI_STRIDE
Calculate offsets for ctx operations considering
sm per tpc. Following functions are modified for this:
gr_gk20a_get_ctx_buffer_offsets
gr_gk20a_get_pm_ctx_buffer_offsets
__gr_gk20a_exec_ctx_ops
Bug 200337994
Change-Id: I3a4ca470a4107d3078b708f38601762626ce1bf1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1539069
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The patch adds a forward declaration of nvgpu_sgt
in nvgpu_mem.h header file to be referred inside
struct nvgpu_sgt_ops. This is to prevent
compilation issue while including this header
elsewhere without explicit forward declaration.
Change-Id: I5cfe5c723e961813425be5301d9bb770bb10c896
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567713
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Before updating ctxheader in gr_gk20a_ctx_patch_smpc()
add cpu access with nvgpu_mem_begin.
After updating ctxheader, close cpu access
with nvgpu_mem_end.
Reviewed usage of ctxheader in other places and its
cpu access is taken care correctly.
Bug 200333285
Change-Id: I88ab0b040f95240673a4be55bcfe880a1440655b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564764
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
The Pg init task hogs the kernel by having a wait condition with no timeout
waiting for pg state change, but ps state may not post a change in a long time
depending on runtime conditions, so we get soft-crashes warning spews in the
kernel
We solve this by making the condition wait interruptible
bug 200346134
Change-Id: I8a3349031acc5065b767dc22eec6e5df113d3ad7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566545
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
- Added falcon interface/HAL for IMEM-copy-from
to read data from IMEM from given location with requested
size
-Added falcon interface to print data of IMEM/DMEM
from given location with requested size using falcon HAL.
JIRA NVGPU-105
Change-Id: I84cf7b5769b84a2baee2c7e65027539598ec1295
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514536
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- Added support to dump flacon controller status
- Method to print recent PC history to know call trace
- Method to dump IMBLK info
- Updated falcon hw header files to include
registers of PC trace & IMBLK
JIRA NVGPU-105
Change-Id: Id4aaafd87113d47e552afb21b87f8b087d36004e
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1515371
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kthread_run can fail if SIGKILL is triggered on an application during
driver load.
On this change we defer the channel worker init to the enqueue to avoid
this condition during driver power on which would cause the driver state to be
corrupted leaving subsequent attempts to load the driver unsuccesful.
By moving this code to a later time, it is now needed to protect the task
structure with a mutex.
JIRA: EVLR-956
Bug 1816515
Change-Id: I3a159de2d1f03e70b2a3969730a927532ede2d6e
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1462490
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1460689
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This change solves two problems:
(*) the possibility of a crash due to interrupting the gpu
initialization following a bind
(*) a IOVA memory leak that could prevent the GPU from binding after
about 200 bind/unbind cycles
A detailed list of fixes:
- chek that arbiter is initialized before freeing it.
- do not re-enable interrupts when MSI is enabled on unbind.
- free the semaphore sea on unbind.
- ensure we dont double load the vbios.
- check return value of nvgpu_mutex_init for semaphores.
- add corresponding nvgpu_mutex_destroy calls.
bug 1816516
Change-Id: Ia8af73019e0e1183998855d55bb3eea09672a8b7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1465302
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: David Jarrett <djarrett@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563019
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This change solves crashes during bind that were introduced in the driver
during the OS unification refactoring due to lack of coverage of the remove()
function.
The fixes during remove are:
(1) Prevent NULL dereference on GPUs with secure boot
(2) Prevent NULL dereferences when fecs_trace is not enabled
(3) Added PRAMIN blocker during driver removal if HW is no longer accesible
(4) Prevent double free of debugfs nodes as they are handled on the
debugfs_remove_recursive() call
(5) quiesce() can now be called without checking is HW accesible flag is set
(6) added function to free irq so no IRQ association is left on the driver after
it is removed
(7) prevent NULL dereference on nvgpu_thread_stop() if the thread is already
stopped
JIRA: EVLR-1739
Change-Id: I787d38f202d5267a6b34815f23e1bc88110e8455
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563005
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The basic nvgpu_mem_sgl implementation provides support
for OS specific scatter-gather list implementations by
simply copying them node by node. This is inefficient,
taking extra time and memory.
This patch implements an nvgpu_mem_sgt struct to act as
a header which is inserted at the front of any scatter-
gather list implementation. This labels every struct
with a set of ops which can be used to interact with
the attached scatter gather list.
Since nvgpu common code only has to interact with these
function pointers, any sgl implementation can be used.
Initialization only requires the allocation of a single
struct, removing the need to copy or iterate through the
sgl being converted.
Jira NVGPU-186
Change-Id: I2994f804a4a4cc141b702e987e9081d8560ba2e8
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1541426
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The last major item preventing the core MM code in the nvgpu
driver from being platform agnostic is the usage of Linux
scattergather tables and scattergather lists. These data
structures are used throughout the mapping code to handle
discontiguous DMA allocations and also overloaded to represent
VIDMEM allocs.
The notion of a scatter gather table is crucial to a HW device
that can handle discontiguous DMA. The GPU has a MMU which
allows the GPU to do page gathering and present a virtually
contiguous buffer to the GPU HW. As a result it makes sense
for the GPU driver to use some sort of scatter gather concept
so maximize memory usage efficiency.
To that end this patch keeps the notion of a scatter gather
list but implements it in the nvgpu common code. It is based
heavily on the Linux SGL concept. It is a singly linked list
of blocks - each representing a chunk of memory. To map or
use a DMA allocation SW must iterate over each block in the
SGL.
This patch implements the most basic level of support for this
data structure. There are certainly easy optimizations that
could be done to speed up the current implementation. However,
this patches' goal is to simply divest the core MM code from
any last Linux'isms. Speed and efficiency come next.
Change-Id: Icf44641db22d87fa1d003debbd9f71b605258e42
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530867
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- Added function to read WPR info from FB
MMU registers
- Added HAL to point wpr info read function
- Replaced wpr info read from MC with HAL
- Removed debugfs header include from acr files.
JIRA NVGPU-128
Change-Id: I5ebec46bfe03b9200f2aa569f2e5a780a715616d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1564683
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Make the kmem debugging prints much more easily usable. Previously the
prints would only take effect if the full tracking was enabled:
CONFIG_NVGPU_TRACK_MEM_USAGE
However, there are many times when just the debug prints would be nice
to have by simply setting the log mask bit in the log mask.
echo 0x80000 > /sys/kernel/debug/<gpu>/log_mask
Also this change now uses the real nvgpu_log() function instead of the
legacy nvgpu_dbg() function. This makes the logging appear with proper
GPU printing as well.
Change-Id: If545da3d357d38fe8252e7d548c6765b995cd3d7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1560248
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
ctx header holds only gpu va for each address space.
All other information will be held in main
context. Ctx header will have gpu va for following
fields:
ctxsw_prog_main_image_context_buffer_ptr
ctxsw_prog_main_image_context_buffer_ptr_hi
ctxsw_prog_main_image_zcull_ptr
ctxsw_prog_main_image_zcull_ptr
ctxsw_prog_main_image_pm_ptr
ctxsw_prog_main_image_pm_ptr_hi
ctxsw_prog_main_image_full_preemption_ptr_hi
ctxsw_prog_main_image_full_preemption_ptr
ctxsw_prog_main_image_full_preemption_ptr_xxxx0
ctxsw_prog_main_image_full_preemption_ptr_xxxx0_v
ctxsw_prog_main_image_patch_adr_lo
ctxsw_prog_main_image_patch_adr_hi
Changes done as part of this CL:
- Read ctx_id from from main context header
- Golden context creation:
Use gold_mem for for golden context creation
and copy golden context from save gold local
memory to main context. No need to restore
golden context to context header.
- Write ctx_patch_count and smpc_ctxsw_mode in
main context header only.
- Update preemption mode in main context header and
preemption buffer va in context header.
- Updated image patch buffer va in context header.
Bug 1958308
Change-Id: Ic076aad8b1802f76f941d2d15cb9a8c07308e3e8
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562680
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GVS: Gerrit_Virtual_Submit
Initialize following counters in context header
for all legacy chips:
ctxsw_prog_main_image_num_save_ops
ctxsw_prog_main_image_num_restore_ops
This was already present in the code but move to a function
gk20a_gr_init_ctxsw_hdr_data, so that it can be re-used across
chips.
Additionally initialize following preemption related counters
for gp10b onwards in context header:
ctxsw_prog_main_image_num_wfi_save_ops
ctxsw_prog_main_image_num_cta_save_ops
ctxsw_prog_main_image_num_gfxp_save_ops
ctxsw_prog_main_image_num_cilp_save_ops
Bug 1958308
Change-Id: I0e45ec718a8f9ddb951b52c92137051b4f6a8c60
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1562654
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GVS: Gerrit_Virtual_Submit
Add a function to check if an nvgpu_mem is allocated (valid) or not.
Also fix possibly leaked state in nvgpu_mems when they fail to
allocate.
Also ensure that in the case of a failure to allocate no state is
accidentally leaked to the caller. This should hopefully make it
less likely that a caller thinks a buffer that failed to allocate
is actually allocated.
Change-Id: I43224ece7da84e63b2f43f36f04941126fabf3c7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1559419
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NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is only used by realtime
priority EGL context, which checks for CAP_SYS_NICE during context
creation in userspace, so it wasn't secure against unprivileged program
spoofing submit ioctl with this flag to stall GPU progress of others.
This flag does increase duration of submit by approx 16us,
mostly due to register accesses and PMU FIFO mutex.
Bug 1989493
Bug 1854791
Bug 1968813
Change-Id: I086b1d14f286abf8bd2d2dfae5945974b7fe6d1f
Reviewed-on: https://git-master.nvidia.com/r/#/c/1558644
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1558644
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Allow userspace to control directly the PTE kind for the mappings by
supplying NVGPU_AS_MAP_BUFFER_FLAGS_DIRECT_KIND_CTRL for MAP_BUFFER_EX.
In particular, in this mode, the userspace will tell the kernel
whether the kind is compressible, and if so, what is the
incompressible fallback kind. By supplying only the compressible kind,
the userspace can require that the map kind will not be demoted to the
incompressible fallback kind in case of comptag allocation failure.
Add also a GPU characteristics flag
NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL to signal whether direct
kind control is supported.
Fix indentation of nvgpu_as_map_buffer_ex_args header comment.
Bug 1705731
Change-Id: I317ab474ae53b78eb8fdd31bd6bca0541fcba9a4
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1543462
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Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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