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ce3c2a3c43
The HS ucode runs on PMU with all interrupts disabled. So it will not be able to detect any data corruption introduced in the IMEM or DMEM due to bit flips. In order to mitigate this issue validate the integrity of IMEM and DMEM at the end of HS ucode bootstrap and fail the boot incase of any un-corrected errors. Jira NVGPU-3555 Change-Id: Icd9a2bf2c29470629be8524c9b99f90e3036abdc Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2124107 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>