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0908547ad2
Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr unit as below g->ops.gr.intr.set_hww_esr_report_mask() g->ops.gr.intr.handle_tpc_sm_ecc_exception() g->ops.gr.intr.get_esr_sm_sel() g->ops.gr.intr.clear_sm_hww() g->ops.gr.intr.handle_ssync_hww() g->ops.gr.intr.log_mme_exception() g->ops.gr.intr.record_sm_error_state() g->ops.gr.intr.get_sm_hww_global_esr() g->ops.gr.intr.get_sm_hww_warp_esr() g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask() g->ops.gr.intr.get_sm_hww_warp_esr_pc() g->ops.gr.intr.tpc_enabled_exceptions() g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val() Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to common.gr.gr unit All of above functions and hals will be needed in safety build Jira NVGPU-3506 Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2127753 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>