Terje Bergstrom 3d08b0dc35 gpu: nvgpu: Add ELPG_ENABLE register ...

Change-Id: I8b2272641c7f406cec9bb2649846e4b4b195e21a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/708720
GVS: Gerrit_Virtual_Submit

2016-12-27 15:22:04 +05:30

..

fb_gp10b.c

gpu: nvgpu: gp10b: Compression page size to 64k

2016-12-27 15:22:03 +05:30

fb_gp10b.h

gpu: nvgpu: gp10b: Add new supported kind

2016-12-27 15:22:02 +05:30

fifo_gp10b.c

gpu: nvgpu: gp10b: Set correct PBDMA signature

2016-12-27 15:22:03 +05:30

fifo_gp10b.h

gpu: nvgpu: gp10b: Set correct PBDMA signature

2016-12-27 15:22:03 +05:30

gr_ctx_gp10b.c

gpu: nvgpu: gp10b: Enable cycling through ctx bins

2016-12-27 15:22:03 +05:30

gr_ctx_gp10b.h

gpu: nvgpu: gp10b: Enable cycling through ctx bins

2016-12-27 15:22:03 +05:30

gr_gp10b.c

gpu: nvgpu: gp10b: Enable warnings as errors

2016-12-27 15:22:03 +05:30

gr_gp10b.h

gpu: nvgpu: gp10b: Enable CILP mode for compute

2016-12-27 15:22:03 +05:30

gr_ops_gp10b.h

gpu: nvgpu: t18x, gp10b framework

2016-12-27 15:22:02 +05:30

hal_gp10b.c

gpu: nvgpu: gp10b: Set correct PBDMA signature

2016-12-27 15:22:03 +05:30

hal_gp10b.h

gpu: nvgpu: gp10b: Fill class numbers

2016-12-27 15:22:02 +05:30

hw_bus_gp10b.h

gpu: nvgpu: gp10b: update headers

2016-12-27 15:22:03 +05:30

hw_ccsr_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_chiplet_pwr_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_ctxsw_prog_gp10b.h

gpu: nvgpu: gp10b: update headers

2016-12-27 15:22:03 +05:30

hw_fb_gp10b.h

gpu: nvgpu: Synchronize gp10b headers with gm20b

2016-12-27 15:22:02 +05:30

hw_fifo_gp10b.h

gpu: nvgpu: headers for linsim CL 34116551

2016-12-27 15:22:03 +05:30

hw_flush_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_fuse_gp10b.h

gpu: nvgpu: headers for linsim CL 34000094

2016-12-27 15:22:03 +05:30

hw_gmmu_gp10b.h

gpu: nvgpu: gp10b: Add new supported kind

2016-12-27 15:22:02 +05:30

hw_gr_gp10b.h

gpu: nvgpu: reg with FECS HALT method

2016-12-27 15:22:03 +05:30

hw_ltc_gp10b.h

gpu: nvgpu: read gobs_per_comptagline_per_slice

2016-12-27 15:22:03 +05:30

hw_mc_gp10b.h

gpu: nvgpu: Add ELPG_ENABLE register

2016-12-27 15:22:04 +05:30

hw_pbdma_gp10b.h

gpu: nvgpu: Synchronize gp10b headers with gm20b

2016-12-27 15:22:02 +05:30

hw_pri_ringmaster_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_pri_ringstation_sys_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_proj_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_pwr_gp10b.h

gpu: nvgpu: Synchronize gp10b headers with gm20b

2016-12-27 15:22:02 +05:30

hw_ram_gp10b.h

gpu: nvgpu: headers for linsim CL 34116551

2016-12-27 15:22:03 +05:30

hw_therm_gp10b.h

gpu: nvgpu: Synchronize gp10b headers with gm20b

2016-12-27 15:22:02 +05:30

hw_timer_gp10b.h

gpu: nvgpu: gp10b headers

2016-12-27 15:22:01 +05:30

hw_top_gp10b.h

gpu: nvgpu: Use queried interrupt ids

2016-12-27 15:22:02 +05:30

ltc_gp10b.c

gpu: nvgpu: gp10b specific LTC ISR

2016-12-27 15:22:04 +05:30

ltc_gp10b.h

gpu: nvgpu: gp10b: Implement L2 query

2016-12-27 15:22:02 +05:30

Makefile

gpu: nvgpu: gp10b: Set correct PBDMA signature

2016-12-27 15:22:03 +05:30

mc_gp10b.c

gpu: nvgpu: gp10b: enable replayable fault interrupt

2016-12-27 15:22:03 +05:30

mc_gp10b.h

gpu: nvgpu: Handle MC pmu interrupts

2016-12-27 15:22:03 +05:30

mm_gp10b.c

gpu: nvgpu: gp10b: Add Bar2 support

2016-12-27 15:22:03 +05:30

mm_gp10b.h

gpu: nvgpu: gp10b: Define physical address width

2016-12-27 15:22:02 +05:30

platform_gp10b_tegra.c

gpu: nvgpu: enable CDE for t18x

2016-12-27 15:22:03 +05:30

pmu_gp10b.c

gpu: nvgpu: gp10b: gpmu elpg support

2016-12-27 15:22:03 +05:30

pmu_gp10b.h

gpu: nvgpu: gp10b: gpmu elpg support

2016-12-27 15:22:03 +05:30