Remove below variables from struct gr_gk20a
u32 bundle_cb_default_size;
u32 min_gpm_fifo_depth;
u32 bundle_cb_token_limit;
u32 attrib_cb_default_size;
u32 alpha_cb_default_size;
u32 attrib_cb_gfxp_default_size;
u32 attrib_cb_gfxp_size;
u32 attrib_cb_size;
u32 alpha_cb_size;
Instead add below hals in hal.gr.init unit to get all of above sizes
u32 (*get_bundle_cb_default_size)(struct gk20a *g);
u32 (*get_min_gpm_fifo_depth)(struct gk20a *g);
u32 (*get_bundle_cb_token_limit)(struct gk20a *g);
u32 (*get_attrib_cb_default_size)(struct gk20a *g);
u32 (*get_alpha_cb_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_size)(struct gk20a *g);
u32 (*get_attrib_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_alpha_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_global_attr_cb_size)(struct gk20a *g, u32 max_tpc);
Define these hals for all gm20b/gp10b/gv11b/gv100/tu104 chips
Also add hal.gr.init support for gv100 chip
Remove all accesses to variables from struct gr_gk20a and start using
newly defined hals
Remove below hals to initialize sizes since they are no more required
g->ops.gr.bundle_cb_defaults(g);
g->ops.gr.cb_size_default(g);
g->ops.gr.calc_global_ctx_buffer_size(g);
Also remove definitions of above hals from all the chip files
Jira NVGPU-2961
Change-Id: I130b578ababf22328d68fe19df581e46aebeccc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077214
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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