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83fe3fd35e
Update PES, ROP exception handling for NVGPU_ERRATA_3524791. Enable the errata for all Volta+ chips. ROP, PES exceptions are being reported using the physical-id, where logical-id should have been used. All ESR status registers are reported using logical-id, so this matches with the SW expectation. To address the (1), update ROP, PES exception handler translate from physical to logical-id before reading the status registers. Bug 3524791 Change-Id: Ieacbfb306bb0e69cf0113dc92f18e401573722e3 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2680029 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>