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4492c62ffe
Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
65 lines
1.8 KiB
C
65 lines
1.8 KiB
C
/*
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* GM20B MMU
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include <nvgpu/timers.h>
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#include "bus_gm20b.h"
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#include "gk20a/gk20a.h"
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#include "gk20a/bus_gk20a.h"
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#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
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static int gm20b_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
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{
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struct nvgpu_timeout timeout;
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int err = 0;
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u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
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u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
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gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
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gk20a_writel(g, bus_bar1_block_r(),
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gk20a_aperture_mask(g, bar1_inst,
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bus_bar1_block_target_sys_mem_ncoh_f(),
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bus_bar1_block_target_vid_mem_f()) |
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bus_bar1_block_mode_virtual_f() |
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bus_bar1_block_ptr_f(ptr_v));
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nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
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do {
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u32 val = gk20a_readl(g, bus_bind_status_r());
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u32 pending = bus_bind_status_bar1_pending_v(val);
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u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
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if (!pending && !outstanding)
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break;
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udelay(5);
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} while (!nvgpu_timeout_expired(&timeout));
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if (nvgpu_timeout_peek_expired(&timeout))
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err = -EINVAL;
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return err;
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}
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void gm20b_init_bus(struct gpu_ops *gops)
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{
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gops->bus.init_hw = gk20a_bus_init_hw;
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gops->bus.isr = gk20a_bus_isr;
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gops->bus.read_ptimer = gk20a_read_ptimer;
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gops->bus.bar1_bind = gm20b_bus_bar1_bind;
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}
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