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df94d474a8
Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w
variables for pbdma_intr_0 interrupt masks for each GPU version separately
pbdma_intr_0 field differences for each GPU version:-
-gk20a : bit 28 does not exists in hw
-gm20b : bit 8(lbreq), 20(xbarconnect) and 28 do not exist in hw
-gp10b : bit 8(lbreq), 20(xbarconnect) do not exist in hw. bit 28,
(syncpoint_illegal) added in hw but is not being handled.
-gk20a/gm20b/gp10b
bit 24 eng_reset and bit 25 semaphore always existed in hw but never
handled
JIRA GPUT19X-47
Change-Id: I209191f57c5ea5b15081b7dc2411801d3537017c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325402
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>