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445 Commits

Author SHA1 Message Date
Hareesh Kesireddy
e0e2a6b200 osi: remove extra args for tx complete callback 
Dma phy address, virtual address and packet length can be
obtained from tx swcx structure. Hence passing
pointer to tx swcx is sufficient. In future, if more information
from osi is needed, it can be embedded into tx swcx itself rather than
adding more arguments to osd tx complete call back.

Bug 3576506

Change-Id: I061ea27cd1b4d68c19f3e9d95a247505c511ce0c
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
0a01e7abf3 osi:macsec reduce complexity of MACSEC APIs 
Issue: Complexity of OSI APIs cannot be greater than 10

Fix: Split the functionality of complex APIs to multiple APIs.
Added De-oxygen comments as well for macsec osi APIs

Bug 3460422

Change-Id: I2383904d8581efa54a8d2ec2f85a50cb12b22e89
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688990
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
325e60b63c osi:macsec: Fix MISRA defects in QNX OSD 
Dependent change made in osi to fix a misra defect in QNX OSD

Bug 3598679

Change-Id: Ie6b48a6d1cb8d34b00c437cc3b57971ad447fa3b
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2695627
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bibhay Ranjan
83082b51e3 nvethernetrm: fix code defects 
Issue: SPARSE errors
Fix: Fix code as per the guidelines in the errors

Bug 3568991

Change-Id: If52bf7d5b3e8d4ca10a254e802ee5257a8816633
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688520
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Nagaraj Annaiah
b3b3455115 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
f238abc016 osi:macsec: Separate lut_status for each IP 
Issue: If macsec is created on EQOS and then created on MGBE, we are
over writing the lut_status of EQOS with MGBE lut_status.

Fix: Create different lut_status structure in osi_core so that each
IP will have its own lut_status structure.

Bug 3587231

Change-Id: I826c3d210ed18350140f1cbcb41b748550f92844
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2690839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
8cad7eb750 osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
a7c927d757 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
a0d542c61c osi:macsec:Change to update MACSEC MTU 
Issue: If MTU is increased after Supplicant is initialized
we are not updating the MACSEC MTU so the frames will get
dropped as the MACSEC MTU is lesser than the frames received

Fix: Changes to update the MACSEC MTU along with MAC MTU

Bug 3577143

Change-Id: Iff61099ff2a9ae1f6fe6e48948d842604fd9e2c4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2685281
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
39949b7869 osi:macsec: Address SC over-writing issue 
Issue: In multi VM use case if multiple SCs are added using supplicants
Then we may over-write an exisitng SC if we stop and start the first
supplicant

Fix: Before adding an SC find the vacant SC slot

Bug 3522740

Change-Id: Ic10f7a542a01328876b0103c34cc1115bfd426b5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675003
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
cb1599e9f2 osi: dma: Define macro for DMA TX max buffer size 
Bug 3528173

Change-Id: If7152ec75bcf21d820cd68c3aff31e3c6aa8ae6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675628
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
7bcef9fd39 nvethenetrm: core: SW WAR implementation for switching of Gates 
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Gaurav Asati
3224505db9 osi: dma: update tx and rx completion API's. 
- Add tx and rx completion API's with
  failure return value.

JIRA T23XMGBE-443

Change-Id: Ib6aa3b559f1356e9285f8d4cc129abc049884342
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618556
(cherry picked from commit 6bd8b7fe13f258928bb81ebe22c30fe5b51688c0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2658600
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Gaurav Asati
018b0034dc osi: update API headers 
Use @usage instead of @note and group all classification and API
group details under @usage.

Bug 3350640

Change-Id: If77cfd76519f17427b95a2300ad722dc6f83f518
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587106
(cherry picked from commit 0002e2d0b2cf85811b09e8c7157dbd777c8fc117)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657079
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Gaurav Asati
cbff6cfa1c osi: Add Async-sync details to API header 
Issue:
Async-sync details to API header is needed.

Fix:
Add Async-sync details to API header and remove duplicate Thread
details.

Bug 3350640

Change-Id: I0838e53951389c9fa408323324cedba0268f4706
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2572939
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
(cherry picked from commit 8acef05c924ed72e256e792a8cd623a221494287)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657054
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
8044116c0e macsec: get next PN and IRQ stats cmd with server 
Some of the commands such as get next PN and irq stats
are not working if thernet server is enabled, fixed the same.
And also moved HKEY generation to OSD, to avoid dependency on
Crypto libs on LK. devmemr/w can read/write to macsec addresses

Bug 3522740

Change-Id: Id3b328cfd83aa976ef5bde8adc057588bb6fed38
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652212
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
098a8d324d osi: fix mmc.h dependency on osi_common.h 
mmc.h uses few definition from osi_common.h

Bug 3500728

Change-Id: I95696ddd63cee4979c0a79cda9a87e65b895dee0
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2663878
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
f8f6bef4f8 nvethernetrm: macsec qnx OSI changes 
Macsec qnx driver OSI changes

Bug 3338180

Change-Id: I2ad4f1b8b919893f2823a120973c1805b58bbb88
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2612659
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
6e2c40c639 osi: Avoid macsec and fpe coexistance on MGBE 
Issue: Internal FIFO over/underflows if MACSEC and FPE are enabled on MGBE
interafce and pre-emptable and express frames are sent in interleaved
fashion

Fix: Do not allow enabling any of MACSEC and FPE if the other is already
enabled.

Bug 3484034

Change-Id: Ifc80eb9333c836652a86362a1f7788a0ce70dbb7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2647788
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
dcc9c26474 core: add support configure pps out signal 
Issue: Default pps output is 1 pulse (of width
clk_ptp_i) every second.

Fix: option to configure to binary rollover is 2 Hz,
and the digital rollover is 1 Hz.

Bug 3462227

Change-Id: Ic777bfaf51a72ec91c8f165910e824c55cae3057
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2641896
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
b89c6aa340 osi:macsec:Changes to enable AN after key program 
Issue: In longer stress tests we see unint_key_slot
errors if the key programing is done after AN is
enabled.

Fix: Fix is to program the key and then enable AN.
Done some code cleanup as well

Bug 3422356

Change-Id: I7aeb2f9ab681509b54e9f6763464dfedb46cd26e
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2626062
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bibhay Ranjan
590c2a437d nveqos:fix MISRA_C-2012_Rule_8.13 and 10.4 issues 
MISRA FIXES
===== DIFF ======
Total misra violation count changed by -21
Rule: MISRA_C-2012_Rule_10.4 Diff: -1
Rule: MISRA_C-2012_Rule_8.13 Diff: -20
Rule: Total Diff: -21

CERT FIXES
===== DIFF ======
Total cert violation count changed by 0

Bug 200770325

Change-Id: Ib6cca8c2eaff5ae8cddd718b2f0c309c6888d4fc
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
5e965e8e0d osi:macsec:lowest pn changes to enable sa 
Enhancement to receive lowest_pn from supplicant
as part of receive AN enable

Bug 3371004

Change-Id: If81f8449f7ebda996c95117e2c84722fdc57c5d0
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2619949
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
e424035b9b nvethernetrm: core: MAC to MAC tsync dynamic support 
Add code to support enable/disable M2M sync using
ioctl.

Bug 200733666

Change-Id: Ifedad7981644c816345f3e10a0b0f8289e032200
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614964
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
b89da89028 nvethernetrm: MAC to MAC time sync 
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
1ca3dc41dc osi:macsec: changes to send next PN to supplicant 
As part of MKA, supplicant requests for Next PN
used by SecY. Added changes to OSI to send to
send the Next PN for a given SCI and AN.

Bug 3371004

Change-Id: Iaf001ba5e6b5480396e2f774a42927831160a2e5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614365
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mohan Thadikamalla
ad67821d0c osi: core: Add MTU IOCTL support 
Issue:
When the ethernet server got enabled,
the MTU changes are not getting
communicated to the ethernet server.

Fix:
Add new OSI IOCTL and implement HAL
and IVC message for ethernet server.

Bug 3402313

Change-Id: I28bab58c2847d275324e54229ac50459d3059d26
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2610189
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
725237b513 core: add CMD_PTP_TSC_CAP to capture time 
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
95fcfbff30 osi: mgbe: add handling of tx errors 
handle Tx buffer underflow
handle Tx jabber timeout
handle Tx IP header error
handle Tx Payload checksum error

Bug 200565898

Change-Id: I2de4cd11580251f0387039c1f8f3c39792c1ab65
Signed-off-by: narayanr <narayanr@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2596092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
1d23574418 core: mgbe: use lock for time stamping 
Using lock for protect critical section between
common interrupt and ioctl call to read
timestamp

Add mmc counters for lock failure during node
addition and deletion.

Bug 200743666

Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099
Tested-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
915f70df96 osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID based on MAC instance ID through HV window

Bug 200761024

Change-Id: I1a37455647429e917e7558e812fe7e512d646918
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592482
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
fac4de5278 dma: mgbe: update RWT and RWUT programming for silicon 
Issue: RWT and RWUT programmed for uFPGA

Fix: Update RWIT programming
     Update minimum rx coalescing timer value

Bug 200767374

Change-Id: I09c21764f0c294021c7546f75351c19c34a0b9db
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589496
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
fcbf3cf7e2 Revert "osi: eqos: mgbe: program SID through HV window" 
This reverts commit b16c09af3b.

Reason for revert: Created regression for AV + L

Bug 3358505
Bug 200761024

Change-Id: I31fbd921f9655cd62073918be9d4151f5cc29f8b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584378
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
5b45034d1c osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID through HV window

Bug 3358505
Bug 200761024

Change-Id: I1db99c85e875aeaf6c692011a0d2fbe16277d288
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2582062
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
9d30f1630f eqos: set ssnic to 6 
Set SSIN to 6 for EQOS mac version 5.3

Bug 200760072

Change-Id: I72923d42313880dd362b7b6b197269f3495a18de
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2575178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
7eb67cff3e osi: Add core debug for registers/structures 
- Adds core debugging for registers/structures.
- Add change to use single macro for CORE and DMA.

Bug 200737108

Change-Id: If96af2ef0c39e01b6c1dad74ee11fd820df76a8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559319
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
6bf817d42b osi: Update MGBE MAC version 
On uFPGA MGBE MAC version is 0x31 and it got updated
to 0x40 on silicon.

Bug 200751806

Change-Id: Ic9d35b7a36cff158dd17feeddce6267a3ec2a082
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559464
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
ee41c275a3 nvethernetrm: address review comments 
- Convert primitive data type to nv_ type's
- Replace debug pr_ prints with OSI_CORE_ print macro's
- Add all macsec register macro's with prefix MACSEC_
- Update all osi function header as per 5.2 coding guidelines(PLC)
- Remove printk.h header file and use OSI_CORE_ERR macro's in all prints
- Implement clean up LUT's in add_upd_sc() and del_upd_sc()

Bug 3264523

Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
a1ee9f8156 osi: use max_chans based on MAC version 
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
c4efd17817 osi: dma: Add debug capabilities 
- Dumps the descriptor if enable_desc_dump flag enabled.
- Dumps registers/structure through OSI DMA IOCTL.

Bug 200737108

Change-Id: I75924cdbd815528dcddba7b9d33dbd4a162f9bbe
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2550985
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
b1be67f7cf eqos: core: pad calibration 
Issue:
   1. Current pad calibration does not check for RGMII/MDIO
      interfaces idle
Fix:
  1. Make sure RGMII and MDIO interface are idle before
     doing pad calibration as per spec

Bug 2831220

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I6b3f35017f62444575d16366d9ac31a5c96fecf7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2321641
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
13808b2444 osi: core: add different XFI/USXGMII modes 
This change takes care of configuring different
connection speeds of XFI/USXGMII modes

Bug 200718307

Change-Id: I28aedb4f7b3a8e4a6bd4acd319487785c8294c05
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2550414
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
rakesh goyal
9c0bebcfd4 osi: common: Add support for MGBE 2 step timestamp 
- OSI DMA
-- During Trasnmit:
 2024-02-21 16:32:06 +05:30
Nagarjuna Kristam
fce6bc8aaa osi: common: Move VM IRQ configuration core to dma 
Issue:
VM IRQ configuration needs is done using DMA base, instead of RM
base.

Fix:
Add VM IRQ configuration code to osi core init sequence.
Remove the same code in DMA.

Bug 200718904
Bug 200730767

Change-Id: I5bf41c85d745a977875ed2eeb044b4db088e0b64
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2539623
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:32:00 +05:30
nannaiah
5008d33c8b nvethernetrm: Update IVC support for macsec 
1. Cleanup ivc_cmd to remove unwanted commands.
2. Update macsec IVC API's.
3. Add HAL read and write register.

Bug 2694285
Bug 2694285

Change-Id: I4d120b7bcfdc9ed65e2bf35a54fa4233a8b6e534
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2529496
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-02-21 16:32:00 +05:30
Mahesh Patil
1e48034244 nvethernetrm: Remove osd callback from osi 
Remove calling osd callback from osi to program SAK and
program SAK from OSD itself.

Bug 3308383

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I2b27cea66bd9770aec52ed53ba430eb276cf73f7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2528707
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:00 +05:30
Nagarjuna Kristam
0710ba642b osi: common: Fix mgbe xpcs and osi_common code 
- Return success xpcs-base is null for now.
- Add is mac enable support for MGBE.
- Call HW type common API base on MAC HW.
- Add generic channel mask macro.

Bug 200718904

Change-Id: Icc228697d0464c18af77312457a6bcfbf484ab7d
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2532466
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
Nagarjuna Kristam
cee49f109c osi: dma: Add vm_num entry in irq_data 
Issue:
irq_data structure uses index of its array as VM number assosciated
with that channel. Which is not true.

Fix:
Add vm_num entry in irq_data which is updated by OSD to its corresponding
DMA channels.

Bug 200730767

Change-Id: Ida3219f8d4cef9bda1890e50a20853553f9bd930
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2532465
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
Bhadram Varka
f1c23b4adf osi: update XPCS speed based UPHY GBE mode 
Bug 3288030

Change-Id: Ic33774fce09d1d426d107a8c4bfa883e9a576f6e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2531231
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:32:00 +05:30
nannaiah
43aa0ee73d nvethernetrm: Add PTP config to ioctl 
Bug 200671160

Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: I71bad68eb995b9a64f6fdfa85147a722bf751e91
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2525909
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30