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Author SHA1 Message Date
Srinivas Ramachandran
1e8dfafa84 osi: Use osd_usleep vs osd_udelay appropriately 
Issue: osd_udelay is used irrespective of the
       duration of the delay/sleep. In certain
       environments like HVRTOS, udelay is a
       busy loop and it starves other tasks on the CPU.
Fix:   Use udelay only for small tight checks, and use
       usleep for larger delays.

Bug 4676601

Change-Id: I59d9a403f34d46c6e2d17ca6f7e8a277d5283db5
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3176350
(cherry picked from commit c2abe16a34af853f86fcaa4bb91b7036e2a8eb79)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3250083
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
 2024-12-04 08:06:03 -08:00
Mohan Thadikamalla
8b85eca5f2 OSI: Fix giza compilation Issues 
Issue:
Doxygen compilation issues were observed
due to changes associated with 4569357 bug.

Fix:
Updated Doxygen comments in the OSI public
header files to resolve the compilation errors.

Bug 4569357

Change-Id: I4b87a5a498e956678f25f2674e7d84aefac17767
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3257876
Reviewed-by: Aniruddha Paul <anpaul@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-11-28 12:55:14 -08:00
Sanath Kumar Gampa
35eda10b40 osi: Segregate the MACSEC HSI code 
Move MACSEC HSI code to MACSEC h/w specific lib

Bug 4942473

Change-Id: I8f04526f26774736d975fad340de3bfcbbc45dd1
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3243835
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2024-11-28 12:39:46 -08:00
Aniruddha Paul
fc6e9530b6 OSI: Set Tx IOC for every fixed number of descs 
A new field 'use_tx_descs' gets programmed by OSD layer.
Tx ring accounts current desc counts and when the current desc
count increases above use_tx_descs and the last bit is set
in the desc, we set the IOC bit.

Bug 4569357

Change-Id: Ida2c7b84e0096007b874e79e3b7502c997f71980
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3207582
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2024-11-20 21:53:02 -08:00
Aniruddha Paul
22a75ac576 osi: Remove duplicate macros 
The below macros were duplicated in the respective
components of osi/core and osi/dma.
1. MGBE_DMA_CHX_MAX_PBL
2. MGBE_DMA_CHX_PBL_16
3. MGBE_DMA_CHX_PBL_8
4. MGBE_DMA_CHX_PBL_4
5. MGBE_DMA_CHX_PBL_1
6. osi_valid_pbl_value()
7. osi_memset()

Move these common macros and APIs which are used by both
osi/core and osi/dma to include/osi_common.h

This also statically assigns TxPBL=16 for Orin.

Bug 4569357

Change-Id: I390e0ad9c0bfda47a1a7f9dd94cf5f7f45d96b9c
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3211481
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-11-20 21:52:52 -08:00
Mohan Thadikamalla
8cf1ea5184 osi: Fix ICD doxygen compilation issues 
Issue:
ICD Doxygen compilation issues have been
observed with Docker version 1.9.0.

Fix:
Update the Doxygen comments in the OSI
public header files to resolve
the Doxygen compilation issues.

Jira NET-1801

Change-Id: I15f305cbdb1bb1a88132498886da353d2bbb714f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3242062
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-11-07 16:22:45 -08:00
Sanath Kumar Gampa
25a07d7228 osi_core: macsec: Reorg MACSec code for DOS-SHR-10437 
Reorganize MACSec source code to accommodate N1Auto MACSec HW IP OSI
driver.

Separated MACSec hardware-specific code into a different static lib

Bug 4874880

Change-Id: I74e4cca8ba615def283ec938cc94985d32099190
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3214907
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2024-10-29 08:12:49 -07:00
Mahesh Patil
8ebeeaafe3 osi: Add osi dma/core release functions 
- Adding osi dma and osi core release function to release resources

Bug 4791340

Change-Id: I031d11ca34a31d2f7c5c8460251509714cba5509
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3214558
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-10-16 19:47:53 -07:00
Mahesh Patil
45f67fb52f osi: Add PCS BASE-R FEC setting 
Adding PCS BASE-R FEC setting using on
sysfs node

Bug 4674473

Change-Id: Icdc2300705d11ce2c96e2c8e1663599a3bb4fadd
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3201974
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
 2024-10-05 04:20:43 -07:00
Rakesh Goyal
cc7aae9570 osi: core: correct SSINC value for thor EQOS 
Issue: SSINC and ptp_ref_clk are wongly
programmed
Fix: SSINC should be 4 as per HW guideline
ptp_ref_clk should be 312.5 MHz

Bug 4747430

Change-Id: Ibbcbfa072c91ccb0cf0271169a52fa09869b5038
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3198414
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2024-10-05 04:19:16 -07:00
Mahesh Patil
c8bea5c22f osi: Properly set the dma chan bits 
- Properly set the dma chan bits for chan > 31 in receive chan list
  bitmap when filters are added
- Fix delete condition for T264 when filter is deleted

Bug 4844451

Change-Id: Ia9f9e7a99b5b3d10813d10aded55061754ed1824
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3209203
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2024-09-23 12:50:54 -07:00
Mahesh Patil
7afef3637f osi: Enable all MGBE 48 VDMA channels 
Bug 4746911

Change-Id: Ieff8f483df47083722b85ade5d591217c9a27380
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3178611
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-09-07 11:00:30 -07:00
Bhadram Varka
2e3848b279 mgbe: pcs: Fix offset for T26X_XPCS_WRAP_INTERRUPT_CONTROL 
Fix the offset for T26X_XPCS_WRAP_INTERRUPT_CONTROL
and removes unused macro.

Bug 4778785

Change-Id: I3f2ac54c8119727f05fc77348d95b12e9ac3f525
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3199177
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-08-28 16:59:22 -07:00
Narayan Reddy
a81ae285f2 osi: core: mgbe: Program ANP value for 25G 
Issue: Seeing an increment in the ping RTT when
FRP rule is enabled in 25G.

Fix: by default ANP value is 5, which is recommended
for 10G. For 25G we need to change it to 3 as per HW
team suggestion.

Bug 4745125

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I2e2cc0f49199908fb5919d0b29da2850030e6be2
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3197679
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-08-22 13:35:28 -07:00
Narayan Reddy
c172c2201f mgbe: enable DRCHM for mmc rx counters 
Issue: MMC Rx counters are not getting incremented

Fix: Enable DRCHM MMC_Control register for the
Rx counters to get incremented

Bug 4742494

Change-Id: I2dec776f12a0ecaeb4e3bfd1f4e040e9d7490e45
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3180193
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-08-22 13:18:36 -07:00
Sanath Kumar Gampa
27ab898c1c osi: update delays for uPHY XLGPS init for 25G 
Update the uPHY delays for 25G speed per manual

Bug 4790491

Change-Id: I79dc2d94db204f4e59a19f9763d53fbf7c99c80e
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3191324
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-08-22 04:58:28 -07:00
Sanath Kumar Gampa
e8bb74d0c1 osi: core: xpcs: Program RxEQ for 25G 
Issue: Observed CRC failures when running perf with 25G speed.

Fix: RxEQ is enabled to avoid Rx CRC errors in perf runs

Bug 4756650

Change-Id: Idc531585e3fac686ca5518b56587980e779125ed
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3187277
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-08-09 21:58:19 -07:00
Sanath Kumar Gampa
35d0eb1f7d osi: MACSec: Update IPG changes for EQoS MACSec 
Issue: IPG is not updated when MACsec is enabled for Thor

Fix: Removed the check to program IPG only if MAC type is Orin

Bug 4768403

Change-Id: I68ddac02d241a94e0a270d15d3c441fb7fc945a7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3188748
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-08-09 13:01:29 -07:00
Mahesh Patil
26c551ceba app: FSI EQOS driver bring up 
- Fix GVS build errors

Bug 4552441

Change-Id: Ib9a25b34ad4980d966806238aadf27dc13395044
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3185939
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2024-08-06 15:33:57 -07:00
Rakesh Goyal
4a0972a389 osi: core: fix tsn hw initialization 
Issue: TSN init is not correct for mgbe
Fix: Fix integration error from side branch to
     dev-main by adding missing code. Now TSN
     init is correct.

Bug 4742997
Bug 4436888

Change-Id: I70d4ca4cad0901a367731e699c7d641a4842d442
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3173951
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-08-05 12:21:34 -07:00
Rakesh Goyal
eeeb693843 osi: fix ptp tx timestamp for vdma 
Issue: PTP time sync not working for vdma other
       than 0.
Fix: Fix integration error from side branch to
     dev-main by adding missing code. Now PTP time
     sync works for any vdma

Bug 4768411

Change-Id: I7f5727f5a0ba66de9baf8983707c54e02e7ef25e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3182405
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-08-01 06:04:41 -07:00
Sanath Kumar Gampa
f386d8cba7 osi: Update MGBE MACSec Tx SOT value 
Update the MGBE MACSec Tx SOT value as per MACSec IAS

Bug 4753677

Change-Id: I352debc77f916abd190e47394e46ec1b410c5460
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3180861
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-08-01 06:01:00 -07:00
Mahesh Patil
cfdfccb488 osi: FSI EQOS driver bring up 
Bug 4552441

Change-Id: I490f9680cc7a71754a64035fb7c63ba56d0287ba
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3166031
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-07-28 21:35:56 -07:00
Narayan Reddy
e6c71e09d0 osi: Adding WAR changes for MGBE 25G 
Adding MGBE 25G WAR changes to match HW script sequence

Bug 4709627
Bug 4713751

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: Ie7aaf1c8c8b9bfbe62d4aa404fc65fe62dbf8efe
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3168031
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2024-07-08 15:56:04 -07:00
Rakesh Goyal
b535351c41 osi: core: add support for new ethernet HW 
Issue: kernel crash when set PTP time using phc_ctl
Fix: add register PTP register offset for new
ethernet HW

Bug 4727541

Change-Id: I60cee4e669dce470d19ff780efab08e7e3288ec2
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3167812
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-07-07 12:51:24 -07:00
Sanath Kumar Gampa
ca0db16125 osi: macsec: Update MACSEC_CONTROL1 per h/w 
1) Stop MAC transmit while enabling MACSEC
2) Disallow FPE and MACSEC co-existence
3) Update SOT for T264 MACSEC
4) 10M and 100M speeds are not supported by MACSec

Bug 4588266
Bug 4456073

Change-Id: I3bc598bae8d2786104c2018bac18cc49092adcdd
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3163257
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-07-02 05:08:44 -07:00
Sanath Kumar Gampa
c8272c3000 osi: fix mmc counters issue 
Reduce the ivc message size to lower than 2048 to fix a build error. To
reduce the same macsec mmc counters are updated with lower 4 bytes of
the register values

Bug 4703442

Change-Id: I72e936622ca9740ac1fe28cb19129437d5a67d2c
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3163253
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-07-02 05:07:46 -07:00
Sathyam Panda
ba3950c623 osi: core: handle mtu update with disbaled MACSEC 
In situation when MACSEC is disabled in DT, macsec_ops
are uninitialized. And an attempt to update the MTU
in this state using OSI command OS_CMD_MAC_MTU can cause
kernel panic.
Add aditional checks to avoid this and exit quietly when
MACSEC is disbaled in DT.

Bug 4646570

Change-Id: If87f3e05f0d24f685c5eb99faeea65d1857d5b43
Signed-off-by: Sathyam Panda <sathyamp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3138409
(cherry picked from commit d6897400d2d989c4b5868cb69c31ef54504b69b4)
Reviewed-by: Hardik Shah <hardikts@nvidia.com>
Reviewed-by: Abhijit . <abhijit@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3158143
Tested-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Revanth Kumar Uppala <ruppala@nvidia.com>
 2024-06-28 10:49:07 -07:00
Mahesh Patil
da071420b2 osi: T264 SLT EQOS and MGBE changes 
- Adding WAR changes to match HW scripts during
 SLT EQOS and MGBE bringup

Bug 4709627

Change-Id: I2bb15c66a037a0a42ef6f40b2d07d716b7d97008
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3162307
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-06-26 22:56:48 -07:00
Nagaraj Annaiah
53fa8d800b xpcs_uphy_lane_bring_up: Increase the retry to 1000 for T264 
Issue: Uphy lane bring up fails on T264

Fix: Increase the retry to 1000 for T264 and this is temporary fix.

Bug 4709627

Change-Id: Ia974e439de3a099ef666803033a3b0155f6dfa61
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3160679
Tested-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-06-26 22:50:23 -07:00
Bhadram Varka
a89360f8db osi: eqos: Keep the reset value for T264 EQOS 
Issue: Ethernet driver is programming the ASID - 0x3
for EQOS IP which is different from the value passed from DT.
It resulted SMMU/memory issues while performing data transfers

Fix: Keep the on reset values for T264 EQOS since lower
8-bits of ASID (0x160) needs to program in ASID registers of EQOS IP.

Bug 4701860

Change-Id: I2c799554d054103bea4c8a05a7bdd0961be81683
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3159696
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
 2024-06-19 21:47:06 -07:00
Mahesh Patil
c479ba1650 osi: T26x EQOS changes 
1) Added T26X EQOS bring up changes
2) Fixes added during bring up

Bug 4639097

Change-Id: I0036a12ad08d690bb62a655df6f4efd26a0bf585
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3152936
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-06-18 11:37:38 -07:00
Mahesh Patil
887b450741 osi: T26x EQOS XPCS bring up changes 
Bug 4639097

Change-Id: I02256885285d86d57764ff1f64a44abd98622075
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3153395
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
 2024-06-18 11:37:33 -07:00
Bhadram Varka
42f3fbeca7 Merge remote-tracking branch 'origin/dev/t264-ethernet' into dev-t264 
Bug 4687787

Change-Id: Ie3411c626b31d1ed4b536954c7e5a875aab29e86
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-06-07 15:11:49 +00:00
Bhadram Varka
12bdb2f1ea osi: core: WAR Werror=frame-larger-than and ivc issue 
Issue:
1. compilation issue:
error: the frame size of 3232 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]

Because of increase in the value of OSI_MACSEC_SC_INDEX_MAX
it resulted in increase in the size of ivc_msg_common
more than 2048 bytes.

2. IVC communication breaking because IVC buffer size
increased more than 2048 because of #1.

WAR: Revert back to the orin value for OSI_MACSEC_SC_INDEX_MAX

Bug 4687787

Change-Id: I5262cd772acf6b4275cc3f47696f0072b70916e0
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-06-07 13:16:02 +00:00
Mahesh Patil
ed305924de osi: Add support for XLGPCS for 25G speed 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2953123

Bug 4599341

Change-Id: I2d0f8b871a081b4c30f586854ab0f56b84e9bfe3
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
b236911c75 osi: T26x CAR changes 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3126091

Bug 4228185

Change-Id: Ia9a7eede0230e25366a37dc8ce7f1a4635bd11cf
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
13e42ef1d2 osi: update T264 mgbe perf configs 
Update MGBE perf configs as per IAS recomendations

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2984047

Bug 4228205

Change-Id: I76f55f2f613417728def92a997957a2f6d18099b
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
caae00f95b osi: Mask MMC_IPC_Rx_Interrupt_Mask interrupts 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3072520

Bug 4297728

Change-Id: I9e14e9ebfe6a40f793e2ebd3c0aede0b95018466
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
28b35b22c1 osi: add idle timer window interrupt support 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2963541

Bug 4246781

Change-Id: I89554a105be26958e17878b299aaadb13c39c130
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:32 +00:00
Rakesh Goyal
be2b32250c osi: core: remove vDMA code from onestep 
Issue: Bug 4287805 was not clear for one-step
Fix: pktid/vdmaid are supported in 2-step only
remove code added for bug 4287805

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3056314

Bug 4287805

Change-Id: Ia02877889ef36a18304e194d413ed1688d881c39
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
68addfdb39 osi: Properly calc completed rx descriptors 
Properly calc number of Rx descriptors to be processed
based of completed write back offset and rx_cur_idx

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3032445

Bug 4408683

Change-Id: Id4af063f2a8eb49921ecf10d4d7fff0c5b4bcb5b
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Rakesh Goyal
b3b589004f osi: ptp support for upcoming chip 
Support for PTP and TSN added

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2968052

Bug 4221043

Change-Id: I68287c3961aa194c30ca265dfe646e733fcb52cc
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
0c2228a485 osi: configure mtl Q's size 
Max Tx/Rx MTL Q size in uFPGA is 64K, so adjust
Tx/Rx MTL Q's accordingly

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3031129

Bug 4413578

Change-Id: I7510cb230bd1400dd1ce565092b445c6a6def30d
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
275769b28a osi: Allow more than 31 l2 filter index 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3027948

Bug 4297989

Change-Id: I0365f2136b5d7519946113fc728a58ed8fcccab4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
84310ba297 osi: In T26x, Q2TCMAP field marked reserved 
Avoid read/writing to MTL_TxQ0_Operation_Mode[Q2TCMAP] as
it is marked reserved.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3003833

Bug 4287563

Change-Id: I578a647200c967449bdda94ea0f34a0895bff393
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Nagaraj Annaiah
23dc94a26a osi: Add FRP and L2 support for t264 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2992833

Bug 4334269

Change-Id: Iceade85fa54b407135ec94b4bb11cc204132efe0
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Sanath Kumar Gampa
ea9c74eb3d osi:macsec Defeature MACSEC features on T264 
Defeature fpe and macsec co-exisitannce, confidentiality offset
and MACSEC debug buffers

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3016483

Bug 4134804

Change-Id: I70679c51eb3dbc3965c3acb689901a523b37ba44
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:06:47 +00:00
Sanath Kumar Gampa
a8361d9fb6 osi:macsec: Update LUT programming for 48 SCs 
Issue: SCI LUT has wrong SC Indexfor Indices greater than 16

Fix: Accomodate more bits from lut_data to read more bits to find the
sc_index.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3010673

Bug 4361623

Change-Id: I6cd9fd11e05a202c06785940733d4f64af541675
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:05:51 +00:00
Mahesh Patil
38bcfb8041 osi: Rx write back descriptor ring offset 
Check Rx descriptor write back ring offset(index) with current
ring index before processing Rx packet to avoid processing Rx
packet before it is actually trasfered to system memory

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2964259

Bug 4246781

Change-Id: Iaa947c6e01e1cc59a5e6dc6ea93ef43a757e3317
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00