Issue: In case of virtualization, init_done for
VM's osi_core is not set which leads to give same
osi_core in case of other VM.
Fix: osi_get_core check for if_init_done instead of init_done
Change-Id: Ib8ffe156723685b4f7fde1f197df3c2c589f75ac
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2518053
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Issue: In current implementation virualization
callback are at HW ops level, which leads
to multiple IVC calls.
Fix: - IVC call happens only for core API's in case
virtualization
- For non-virtualization case HW operations will
be invoked directly from OS OSD.
- From Ethernet server OSD - OSI HAL API's
should be called to access the HW operations
Bug 200671160
Change-Id: Ic3730fb822ae37fdf29fabf429f18f5d5bacd210
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2509243
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
To reduce number of external interface APIs,
consolidate all IOCTL API to one interface API.
Bug 200671160
Change-Id: I407ee5c50c8b3293c5be613beda68e1e450dce89
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Issue: Since core_ops/dma_chan_ops are static global
variables and these are stored in data segment of
a process. In linux when insmod happens eqos and mgbe
will get probe which inturn initialize osi core ops.
Since data segment is shared here eqos core ops pointer
overwritten by mgbe core operations.
Fix: Use separe core ops and local global variable
for each instance.
Bug 200671160
Change-Id: I7f093608d812e2ced1bf73339dbd70f0091fe5b4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Don't add accumulated previous counter value when
counter is updated with latest value. Register value
itself is accumulated counter.
Bug 200688810
Change-Id: I93c971724557813a317cc118ce1b4459b9772d83
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
This commit adds support for MACsec controller HW
operations. The MACsec HW ops can be accessed via
osi_core layer.
Currently, MACsec HW is enabled when MAC interface
is brough up, with no LUT entry so that packets
will still be bypassed. MTU check is enabled and
default interrupts are enabled for statistics.
Bug 2913560
Change-Id: I62e8567fac6603db47f4069a40458038f9b4178a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Issue: MCBC queue for preemptable packet is default Queue
0 and update Overhead Bytes Value default value is
not sufficient as per HW update.
Fix: MCBCQ for preemptable packet should be different
from express packet Q. Using residual Queue for
same.
Add OVHD for MGBE as per programming information
from HW team.
Bug 200561100
Bug 200630202
Change-Id: Ib37e37c4d229b62589e76b1879538cd66707024c
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Issue: 1) Return from irq handler if EQOS_MAC_PCS_LNKSTS
is not set without checking FPE interrupt status
bit set.
2) Continue MTL interrupt if GCL wrong configured and
Frames Scheduling error occur.
Fix: 1) As MAC interrupt handler code is updated
to support FPE, SW should check for
possible interrupt status bits before checking
PCS interrupt.
2) Correct FPRQ bit fields
3) Set DFBS bit to drop Frames causing Scheduling
Error
Bug 200604316
Change-Id: I83d35085707d5efd738090f6147b19d5b931d468
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Enable multiple DMA Channels routing support
for MC/BC MAC Address with XDCS.
Bug 200565911
Change-Id: I7c9f9347361dd72e68696846a0a59e2e241e20c9
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
program the recommended values by HW team for
better performance
Bug 200565630
Bug 200570017
Change-Id: I96a870114623ce76804c49706d2961010448ca86
Signed-off-by: narayanr <narayanr@nvidia.com>
Issue: TX and TX completion thread are running in parallel on
different CPUs. As soon as first CPU updates OWN bit and
TX index (before dmb and TAIL), second CPU started processing
this descriptor and found OWN bit as 0. Due to this,
2nd CPU reset the descriptor to 0s in osi_process_tx_completions()
before HW process the descriptor.
Hence HW still waiting at the reset descriptor while
SW clean_idx has moved ahead.
Fix: In TX path update cur_tx_idx only after DMB.
Bug 3296734
Change-Id: Ic9b6e636e4f8dc8d2e4e6b9af6be201f35e72428
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2536248
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
- Define new data structure for the FRP table entry,
declare new frp_table and NVE variables in the OSI
core private structure.
- Define a new data structure for the OSI FRP command.
Add new OSI API to initiate FRP commands from OSD.
Bug 200565623
Change-Id: I84660a6e8270a681b82236d0c39423660b3821ff
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2330182
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Change takes care of -
o Enable PTP for MGBE
o Added flags for One step/two step and also
for PTP master/slave
o Getting timestamp from MAC registers for MGBE.
Bug 200565914
Change-Id: I17346451f2619f0526a737a4a6bffdf130af4fc0
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2314201
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This change programs 40byte Hash key and indirection table
(Hash table) (has DMA channel numbers) in MAC
Once packet received by MAC - 4-tuples will be extracted
from the packet and given to RSS hash engine. Hash function
will generate hash value by using 40byte key.
From hash value LSB bits used as index to RSS lookup table to
find out DMA channel number. If there is a match - packet is
routed to corresponding DMA channel. If there is no match -
packet will be dropped and error will be returned in receive desc.
Bug 200565647
Change-Id: Iffbb5a452f03278b3ba0bc061f09b43c7c994289
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2263398
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
- Add new ptp_rx_queue variable in
osi_ptp_config structure.
- Declare an IP callback function
for PTP RX queue index programming.
- Check and call IP based PTP RX queue
callback in osi_ptp_configuration.
Bug 200596985
Change-Id: Ief040dc5b607ad729af5e9c0c1870249b456dcc7
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
- Define missing register that requires
save and restore support
- Define MGBE-HW-BACKUP group for these
register backup index
- Define new mgbe_core_backup_config core_backup structure
- Add mgbe_core_backup_init call to
initialize reg_addr of mgbe_core_backup_config
- Implement save and restore callbacks to
save and restore of direct and indirect access registers
Bug 200596517
Change-Id: I58e9571a916223c90b3ed1f4622f57648c013c77
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2310184
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Adds support for VLAN insertion/deletion and filtering
on receive side.
Perfect filtering enabled for the VLAN filtering.
HW maximum has 32 VLAN perfect filters. If user adds
more than 32 then all VID's will be allowed
Bug 200565888
Change-Id: I75bdc261a77df4f9d9f5fff9a2943731de9dd4ef
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2312144
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
