nv-tegra-mirror/t23x-public-dts
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/device/hardware/nvidia/t23x-public-dts.git synced 2025-12-22 17:30:17 +03:00
Code Issues Packages Projects Releases Wiki Activity

overlay: remove fragment syntax with preprocessor

Browse Source 
As part of the process to transitioning to a full featured
base dtb, we need the ability to include various files without
completely rewriting them.  This will be an incremental step.
Eventually these preprocessor commands will be removed and
the indentation fixed.

This change is not intended to change any behavior.  It is merely
adding the infrastructure for future patches.  It will be possible
for a base dts file to define REMOVE_FRAGMENT_SYNTAX and directly
include these files.

Bug 4290389

Change-Id: I778bc25dcd7e4fa96f003882e34e38fe5aaf40e7
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2992336
(cherry picked from commit a011a22ad5)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3002425
Reviewed-by: Gautham Srinivasan <gauthams@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-06 01:22:11 +00:00
committed by mobile promotions
parent 5ca30a4eb6
commit 782ead6230
24 changed files with 98 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
overlay/tegra234-base-overlay.dtsi
View File

@@ -21,12 +21,14 @@
#define TEGRA234_POWER_DOMAIN_DLAB 33U #define TEGRA234_POWER_DOMAIN_DLAB 33U
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
overlay-name = "Add nvidia,t234 Overlay Support"; overlay-name = "Add nvidia,t234 Overlay Support";
compatible = "nvidia,tegra234"; compatible = "nvidia,tegra234";
fragment-t234-base@0 { fragment-t234-base@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
aliases { aliases {
serial0 = "/bus@0/serial@3100000"; serial0 = "/bus@0/serial@3100000";
serial1 = "/bus@0/serial@3110000"; serial1 = "/bus@0/serial@3110000";
@@ -799,6 +801,8 @@
nvidia,vm-irq-id = <3>; nvidia,vm-irq-id = <3>;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-camera-p3785.dtsi
View File

@@ -6,9 +6,11 @@
#define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4) #define CAM0_PWDN TEGRA234_AON_GPIO(AA, 4)
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-camera@0 { fragment-camera@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
gpio@c2f0000 { gpio@c2f0000 {
camera-control-output-high { camera-control-output-high {
gpio-hog; gpio-hog;
@@ -402,6 +404,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

5
overlay/tegra234-dcb-p3737-0000-p3701-0000.dtsi
View File

@@ -2,10 +2,11 @@
// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-dcb@0 { fragment-t234-dcb@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
display@13800000 { display@13800000 {
nvidia,dcb-image = [ nvidia,dcb-image = [
55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49 55 aa 16 00 00 37 34 30 30 e9 4c 19 77 cc 56 49
@@ -535,6 +536,8 @@
40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00 40 00 00 00 00 00 00 06 00 00 00 00 00 05 05 00
00 00 00 00 00 00 00 ]; 00 00 00 00 00 00 00 ];
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3701-0000-prod-overlay.dtsi
View File

@@ -2,9 +2,11 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-p3701-prod@0 { fragment-p3701-prod@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
aon@c000000 { aon@c000000 {
prod-settings { prod-settings {
@@ -322,6 +324,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3701-0000.dtsi
View File

@@ -4,9 +4,11 @@
#include "tegra234-p3701-0000-prod-overlay.dtsi" #include "tegra234-p3701-0000-prod-overlay.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3701-0000@0 { fragment-t234-p3701-0000@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
i2c@c240000 { i2c@c240000 {
ina3221@40 { ina3221@40 {
@@ -149,6 +151,8 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3701-0008.dtsi
View File

@@ -2,9 +2,11 @@
// SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3701-0008@0 { fragment-t234-p3701-0008@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
i2c@c240000 { i2c@c240000 {
ina3221@40 { ina3221@40 {
@@ -290,6 +292,8 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

5
overlay/tegra234-p3737-0000+p3701-0000.dts
View File

@@ -16,11 +16,12 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
compatible = "nvidia,p3737-0000+p3701-0000"; compatible = "nvidia,p3737-0000+p3701-0000";
fragment-t234-p3737-p3701@0 { fragment-t234-p3737-p3701@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
cpus { cpus {
idle-states { idle-states {
c7 { c7 {
@@ -336,6 +337,8 @@
display@13800000 { display@13800000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3737-0000.dtsi
View File

@@ -2,9 +2,11 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3737-0000@0 { fragment-t234-p3737-0000@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
spi@3210000{ /* SPI1 in 40 pin conn */ spi@3210000{ /* SPI1 in 40 pin conn */
spi@0 { /* chip select 0 */ spi@0 { /* chip select 0 */
@@ -125,6 +127,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3740-0002+p3701-0008-safety.dts
View File

@@ -7,9 +7,11 @@
#include "tegra234-soc-safetyservice-fsicom.dtsi" #include "tegra234-soc-safetyservice-fsicom.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3740-p3701-safety@0 { fragment-t234-p3740-p3701-safety@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234"; compatible = "nvidia,p3740-0002+p3701-0008", "safety", "nvidia,p3701-0008", "nvidia,tegra234";
bus@0 { bus@0 {
@@ -223,6 +225,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3740-0002+p3701-0008.dts
View File

@@ -15,11 +15,13 @@
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
compatible = "nvidia,p3740-0002+p3701-0008"; compatible = "nvidia,p3740-0002+p3701-0008";
fragment-t234-p3740-p3701@0 { fragment-t234-p3740-p3701@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
chosen { chosen {
bootargs = "console=ttyTCU0,115200n8"; bootargs = "console=ttyTCU0,115200n8";
}; };
@@ -292,6 +294,8 @@
display@13800000 { display@13800000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3740-0002.dtsi
View File

@@ -4,9 +4,11 @@
#include "tegra234-soc-audio-dai-links.dtsi" #include "tegra234-soc-audio-dai-links.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3740-0002@0 { fragment-t234-p3740-0002@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
i2c@31c0000 { i2c@31c0000 {
typec: stusb1600@28 { typec: stusb1600@28 {
@@ -231,6 +233,8 @@
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3767-0000.dtsi
View File

@@ -6,10 +6,12 @@
#include <dt-bindings/interrupt/tegra234-irq.h> #include <dt-bindings/interrupt/tegra234-irq.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
p3767-0000-fragment@0 { p3767-0000-fragment@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
mmc@3400000 { mmc@3400000 {
no-sdio; no-sdio;
@@ -78,6 +80,8 @@
status = "okay"; status = "okay";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-p3768-0000+p3767-0000.dts
View File

@@ -14,11 +14,13 @@
#include "tegra234-soc-camera.dtsi" #include "tegra234-soc-camera.dtsi"
#include "tegra234-dcb-p3737-0000-p3701-0000.dtsi" #include "tegra234-dcb-p3737-0000-p3701-0000.dtsi"
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay"; overlay-name = "Tegra234 P3768-0000+P3767-0000 Overlay";
fragment-t234-p3768-p3767@0 { fragment-t234-p3768-p3767@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bpmp { bpmp {
i2c { i2c {
vrs@3c { vrs@3c {
@@ -455,6 +457,8 @@
display@13800000 { display@13800000 {
status = "okay"; status = "okay";
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

6
overlay/tegra234-p3768-0000.dtsi
View File

@@ -1,10 +1,12 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-p3768-0000@0 { fragment-t234-p3768-0000@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
aconnect@2900000 { aconnect@2900000 {
@@ -36,6 +38,8 @@
hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { }; hdr40_snd_link_i2s: nvidia-audio-card,dai-link@77 { };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-audio-dai-links.dtsi
View File

@@ -7,9 +7,11 @@
#define ADMAIF_CIF(i) (TEGRA186_ADMAIF_CIF_OFFSET + i - 1) #define ADMAIF_CIF(i) (TEGRA186_ADMAIF_CIF_OFFSET + i - 1)
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-audio-links@0 { fragment-audio-links@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
sound { sound {
/* ADMAIF <--> XBAR PCM links */ /* ADMAIF <--> XBAR PCM links */
admaif1_pcm_link: nvidia-audio-card,dai-link@0 { admaif1_pcm_link: nvidia-audio-card,dai-link@0 {
@@ -2276,6 +2278,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

5
overlay/tegra234-soc-camera.dtsi
View File

@@ -12,10 +12,11 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-camera@0 { fragment-camera@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
aliases { /* RCE is the Camera RTCPU */ aliases { /* RCE is the Camera RTCPU */
tegra-camera-rtcpu = "/rtcpu@bc00000"; tegra-camera-rtcpu = "/rtcpu@bc00000";
}; };
@@ -265,6 +266,8 @@
status = "disabled"; status = "disabled";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-display-overlay.dtsi
View File

@@ -5,8 +5,10 @@
/ { / {
fragment-t234-display@0 { fragment-t234-display@0 {
#ifndef REMOVE_FRAGMENT_SYNTAX
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
dce@d800000 { dce@d800000 {
compatible = "nvidia,tegra234-dce"; compatible = "nvidia,tegra234-dce";
@@ -179,6 +181,8 @@
dma-coherent; dma-coherent;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

6
overlay/tegra234-soc-overlay.dtsi
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// //
// This file contains the DT nodes of T234 which are not in base/tegra234.dtsi // This file contains the DT nodes of T234 which are not in base/tegra234.dtsi
@@ -16,9 +16,11 @@
#include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-soc@0 { fragment-t234-soc@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
aliases { aliases {
nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000"; nvdla0 = "/bus@0/host1x@13e00000/nvdla0@15880000";
nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000"; nvdla1 = "/bus@0/host1x@13e00000/nvdla1@158c0000";
@@ -1004,6 +1006,8 @@
status = "disabled"; status = "disabled";
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-prod-overlay.dtsi
View File

@@ -2,9 +2,11 @@
// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. // SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-soc-prod@0 { fragment-t234-soc-prod@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
i2c@3160000 { i2c@3160000 {
prod-settings { prod-settings {
@@ -830,6 +832,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -6,8 +6,10 @@
/ { / {
fragment-fsicom@0 { fragment-fsicom@0 {
#ifndef REMOVE_FRAGMENT_SYNTAX
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@@ -147,6 +149,8 @@
status = "disabled"; status = "disabled";
channelid_list = <0>; channelid_list = <0>;
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-thermal-shutdown.dtsi
View File

@@ -4,9 +4,11 @@
#define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500 #define TEGRA234_THERMAL_SHUTDOWN_TEMP 104500
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-shutdown@0 { fragment-t234-thermal-shutdown@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
thermal-zones { thermal-zones {
cpu-thermal { cpu-thermal {
trips { trips {
@@ -98,6 +100,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-thermal-slowdown-cluster.dtsi
View File

@@ -6,9 +6,11 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-cluster@0 { fragment-t234-thermal-slowdown-cluster@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
gpu@17000000 { gpu@17000000 {
#cooling-cells = <2>; #cooling-cells = <2>;
@@ -222,6 +224,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

4
overlay/tegra234-soc-thermal-slowdown-corepair.dtsi
View File

@@ -6,9 +6,11 @@
#define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000 #define TEGRA234_THERMAL_SLOWDOWN_TEMP 99000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal-slowdown-corepair@0 { fragment-t234-thermal-slowdown-corepair@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
bus@0 { bus@0 {
gpu@17000000 { gpu@17000000 {
#cooling-cells = <2>; #cooling-cells = <2>;
@@ -258,6 +260,8 @@
}; };
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };

5
overlay/tegra234-soc-thermal.dtsi
View File

@@ -4,10 +4,11 @@
#define TEGRA234_THERMAL_POLLING_DELAY 1000 #define TEGRA234_THERMAL_POLLING_DELAY 1000
/ { / {
#ifndef REMOVE_FRAGMENT_SYNTAX
fragment-t234-thermal@0 { fragment-t234-thermal@0 {
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
#endif
thermal-zones { thermal-zones {
cpu-thermal { cpu-thermal {
polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
@@ -54,6 +55,8 @@
polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>; polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
}; };
}; };
#ifndef REMOVE_FRAGMENT_SYNTAX
}; };
}; };
#endif
}; };