t23x: dts: restructure soctherm sensors

Previously soctherm sensors were included in platform-level (cvm+cvb)
files. This change moves them to module-level files, since the settings
are module-specific.

Bug 4893772

Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com>
Change-Id: I3b52dbc6f3183ef18087921cc2782f46d3229fa0
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3226551
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>

nv-platform/tegra234-camera-p3785.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include <dt-bindings/clock/tegra234-clock.h>
 
@@ -339,41 +339,6 @@
 
 	tegra-camera-platform {
 		compatible = "nvidia, tegra-camera-platform";
-		/**
-		* Physical settings to calculate max ISO BW
-		*
-		* num_csi_lanes = <>;
-		* Total number of CSI lanes when all cameras are active
-		*
-		* max_lane_speed = <>;
-		* Max lane speed in Kbit/s
-		*
-		* min_bits_per_pixel = <>;
-		* Min bits per pixel
-		*
-		* vi_peak_byte_per_pixel = <>;
-		* Max byte per pixel for the VI ISO case
-		*
-		* vi_bw_margin_pct = <>;
-		* Vi bandwidth margin in percentage
-		*
-		* max_pixel_rate = <>;
-		* Max pixel rate in Kpixel/s for the ISP ISO case
-		*
-		* isp_peak_byte_per_pixel = <>;
-		* Max byte per pixel for the ISP ISO case
-		*
-		* isp_bw_margin_pct = <>;
-		* Isp bandwidth margin in percentage
-		*/
-		num_csi_lanes = <4>;
-		max_lane_speed = <1500000>;
-		min_bits_per_pixel = <10>;
-		vi_peak_byte_per_pixel = <2>;
-		vi_bw_margin_pct = <25>;
-		max_pixel_rate = <750000>;
-		isp_peak_byte_per_pixel = <5>;
-		isp_bw_margin_pct = <25>;
 
 		/**
 		* The general guideline for naming badge_info contains 3 parts, and is as follows,

nv-platform/tegra234-p3701-0000.dtsi

@@ -2,63 +2,12 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "tegra234-p3701-0000-prod-overlay.dtsi"
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 
 / {
-	bus@0 {
-		i2c@c240000 {
-			ina3221@40 {
-				compatible = "ti,ina3221";
-				reg = <0x40>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "VDD_GPU_SOC";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDD_CPU_CV";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "VIN_SYS_5V0";
-					shunt-resistor-micro-ohms = <2000>;
-					ti,summation-disable;
-				};
-			};
-
-			ina3221@41 {
-				compatible = "ti,ina3221";
-				reg = <0x41>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					status = "disabled";
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDDQ_VDD2_1V8AO";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					status = "disabled";
-				};
-			};
-		};
-
-		spi@3270000 {
-			flash@0 {
-				spi-max-frequency = <51000000>;
-				spi-tx-bus-width = <1>;
-				spi-rx-bus-width = <1>;
-			};
-		};
-	};
-
 	bpmp {
 		i2c {
 			vrs@3c {
@@ -73,11 +22,7 @@
 			};
 
 			tegra_tmp451: thermal-sensor@4c {
-				compatible = "ti,tmp451";
-				reg = <0x4c>;
-				vcc-supply = <&vdd_1v8_ao>;
 				#thermal-sensor-cells = <1>;
-				status = "okay";
 			};
 
 			vrs11_1@20 {

nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
 #include "nv-soc/tegra234-soc-camera.dtsi"
 #include "tegra234-p3737-0000.dtsi"
@@ -36,40 +32,6 @@
 		status = "okay";
 	};
 
-	thermal-zones {
-		cpu-thermal {
-			status = "okay";
-		};
-
-		cv0-thermal {
-			status = "okay";
-		};
-
-		cv1-thermal {
-			status = "okay";
-		};
-
-		cv2-thermal {
-			status = "okay";
-		};
-
-		gpu-thermal {
-			status = "okay";
-		};
-
-		soc0-thermal {
-			status = "okay";
-		};
-
-		soc1-thermal {
-			status = "okay";
-		};
-
-		soc2-thermal {
-			status = "okay";
-		};
-	};
-
 	bus@0 {
 		smmu_test {
 			compatible = "nvidia,smmu_test";

nv-platform/tegra234-p3740-0002+p3701-0008-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-cluster.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-camera.dtsi"
 #include "tegra234-camera-p3785.dtsi"
 #include "tegra234-p3740-0002.dtsi"
@@ -21,12 +17,6 @@
 		bootargs = "console=ttyTCU0,115200n8";
 	};
 
-	bpmp {
-		thermal {
-			status = "okay";
-		};
-	};
-
 	cpus {
 		idle-states {
 			c7 {
@@ -45,8 +35,6 @@
 
 	thermal-zones {
 		cpu-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -55,8 +43,6 @@
 		};
 
 		cv0-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -65,8 +51,6 @@
 		};
 
 		cv1-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -75,8 +59,6 @@
 		};
 
 		cv2-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -85,8 +67,6 @@
 		};
 
 		gpu-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -95,8 +75,6 @@
 		};
 
 		soc0-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -105,8 +83,6 @@
 		};
 
 		soc1-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
@@ -115,18 +91,12 @@
 		};
 
 		soc2-thermal {
-			status = "okay";
-
 			cooling-maps {
 				map-hot-surface-alert {
 					cooling-device = <&hot_surface_alert 0 0>;
 				};
 			};
 		};
-
-		tj-thermal {
-			status = "okay";
-		};
 	};
 
 	bus@0 {

nv-platform/tegra234-p3740-0002.dtsi

@@ -6,6 +6,10 @@
 / {
 	bus@0 {
 		i2c@31c0000 {
+			audio-codec@1c {
+				#sound-dai-cells = <1>;
+			};
+
 			typec: stusb1600@28 {
 				status = "okay";
 				compatible = "st,stusb1600";
@@ -31,32 +35,7 @@
 		};
 
 		i2c@c250000 {
-			ina3221@41 {
+			power-sensor@44 {
-				compatible = "ti,ina3221";
-				reg = <0x41>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "CVB_ATX_12V";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "CVB_ATX_3V3";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "CVB_ATX_5V";
-					shunt-resistor-micro-ohms = <2000>;
-				};
-			};
-
-			ina219@44 {
-				compatible = "ti,ina219";
-				reg = <0x44>;
-				shunt-resistor = <2000>;
 				label = "CVB_ATX_12V_8P";
 			};
 

nv-platform/tegra234-p3767-0000.dtsi

@@ -4,6 +4,10 @@
 #include <dt-bindings/gpio/tegra234-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt/tegra234-irq.h>
+#include "nv-soc/tegra234-soc-thermal.dtsi"
+#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
+#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
+#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 
 / {
 	bus@0 {

nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi

@@ -2,10 +2,6 @@
 // SPDX-FileCopyrightText: Copyright (c) 2023-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 #include "nv-soc/tegra234-overlay.dtsi"
-#include "nv-soc/tegra234-soc-thermal.dtsi"
-#include "nv-soc/tegra234-soc-thermal-slowdown-corepair.dtsi"
-#include "nv-soc/tegra234-soc-thermal-shutdown.dtsi"
-#include "nv-soc/tegra234-soc-thermal-trip-event.dtsi"
 #include "nv-soc/tegra234-soc-audio-dai-links.dtsi"
 #include "tegra234-p3768-0000.dtsi"
 #include "tegra234-p3767-0000.dtsi"
@@ -103,18 +99,6 @@
 			};
 		};
 
-		serial@3100000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		serial@3140000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
 		i2c@3180000 {
 			status = "okay";
 		};
@@ -192,27 +176,6 @@
 
 		i2c@c240000 {
 			status = "okay";
-			ina32211_1_40: ina3221@40 {
-				compatible = "ti,ina3221";
-				reg = <0x40>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				channel@0 {
-					reg = <0x0>;
-					label = "VDD_IN";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-				channel@1 {
-					reg = <0x1>;
-					label = "VDD_CPU_GPU_CV";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-				channel@2 {
-					reg = <0x2>;
-					label = "VDD_SOC";
-					shunt-resistor-micro-ohms = <5000>;
-				};
-			};
 			fusb301@25 {
 				compatible = "onsemi,fusb301";
 				reg = <0x25>;
@@ -231,18 +194,6 @@
 			};
 		};
 
-		pcie-ep@14160000 {/* C4 - End Point */
-			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
-					<&p2u_hsio_7>;
-			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
-			reset-gpios = <&gpio
-					TEGRA234_MAIN_GPIO(L, 1)
-					GPIO_ACTIVE_LOW>;
-			nvidia,refclk-select-gpios = <&gpio_aon
-							TEGRA234_AON_GPIO(AA, 4)
-							GPIO_ACTIVE_HIGH>;
-		};
-
 		/* PWM1, 40pin header, pin 15 */
 		pwm@3280000 {
 			status = "okay";
@@ -359,6 +310,10 @@
 				status = "okay";
 			};
 		};
+
+		pcie@14100000 {
+			nvidia,pex-wake-gpios = <&gpio TEGRA234_MAIN_GPIO(L, 2) IRQ_TYPE_LEVEL_LOW>;
+		};
 	};
 
 	cpus {
@@ -377,40 +332,6 @@
 		status = "okay";
 	};
 
-	thermal-zones {
-		cpu-thermal {
-			status = "okay";
-		};
-
-		gpu-thermal {
-			status = "okay";
-		};
-
-		cv0-thermal {
-			status = "okay";
-		};
-
-		cv1-thermal {
-			status = "okay";
-		};
-
-		cv2-thermal {
-			status = "okay";
-		};
-
-		soc0-thermal {
-			status = "okay";
-		};
-
-		soc1-thermal {
-			status = "okay";
-		};
-
-		soc2-thermal {
-			status = "okay";
-		};
-	};
-
 	dce@d800000 {
 		status = "okay";
 	};
@@ -425,3 +346,5 @@
 		status = "okay";
 	};
 };
+
+/delete-node/ &{/gpio-keys/key-suspend};

nv-soc/tegra234-base-overlay.dtsi

@@ -37,6 +37,26 @@
 	};
 
 	bus@0 {
+		usb@3610000 {
+			/delete-property/ interrupts;
+			interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+				     <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
+			/*
+			   wake0, wake1, wake2 are for USB3.0 ports
+			   wake3, wake4, wake5, wake6 are for USB2.0 ports
+			*/
+			interrupt-names = "xhci", "mbox",
+				  "wake0", "wake1", "wake2", "wake3",
+				  "wake4", "wake5", "wake6";
+		};
+
 		pcie@140a0000 {
 			iommus = <&smmu_niso1 TEGRA234_SID_PCIE8>;
 		};
@@ -420,6 +440,10 @@
 			dma-names = "rx", "tx";
 			dma-coherent;
 			iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
+					  <&bpmp TEGRA234_CLK_QSPI0_PM>;
+			assigned-clock-rates = <199999999 99999999>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
 		};
 
 		hardware-timestamp@3aa0000 {

nv-soc/tegra234-soc-overlay.dtsi

@@ -857,39 +857,12 @@
 		};
 
 		pcie-ep@14160000 {
-			compatible = "nvidia,tegra234-pcie-ep";
-			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
-			reg = <0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */
-				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */
-				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */
-				0x21 0x40000000 0x3 0x00000000>;  /* Address Space (12G)        */
-			reg-names = "appl", "atu_dma", "dbi", "addr_space";
-			num-lanes = <4>;
-			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
-			clock-names = "core";
-			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
-			       <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
-			reset-names = "apb", "core";
-
 			pinctrl-names = "default";
 			pinctrl-0 = <&pex_rst_c4_in_state>;
-			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
-			interrupt-names = "intr";
-			nvidia,bpmp = <&bpmp 4>;
-			nvidia,enable-ext-refclk;
-			nvidia,aspm-cmrt-us = <60>;
-			nvidia,aspm-pwr-on-t-us = <20>;
-			nvidia,aspm-l0s-entrance-latency-us = <3>;
 
 			nvidia,host1x = <&host1x>;
 			num-ib-windows = <2>;
 			num-ob-windows = <8>;
-			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
-				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
-			interconnect-names = "dma-mem", "write";
-			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
-			dma-coherent;
-			status = "disabled";
 		};
 
 		pcie-ep@141a0000 {

nv-soc/tegra234-soc-thermal.dtsi

@@ -6,46 +6,64 @@
 / {
 	thermal-zones {
 		cpu-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		gpu-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv0-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv1-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		cv2-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc0-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc1-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		soc2-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};
 
 		tj-thermal {
+			status = "okay";
+
 			polling-delay = <TEGRA234_THERMAL_POLLING_DELAY>;
 			polling-delay-passive = <TEGRA234_THERMAL_POLLING_DELAY>;
 		};

overlay/tegra234-camera-ar0234-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2018-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2018-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -819,40 +819,7 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <2>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-e3331-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -210,42 +210,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <3>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <800000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-e3333-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2015-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2015-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -63,42 +63,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				* Set this to the highest pix_clk_hz out of all available modes.
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <12>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <160000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-imx185-a00.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2016-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2016-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -402,40 +402,6 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-imx274-dual.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 
 / {
 	fragment-camera@0 {
@@ -712,41 +712,7 @@
 		__overlay__ {
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <8>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <750000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,
 				* The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-imx390-a00.dtsi

@@ -278,40 +278,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				/**
 				* The general guideline for naming badge_info contains 3 parts, and is as follows,

overlay/tegra234-camera-p3762-a00.dtsi

@@ -1391,40 +1391,7 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				 * Physical settings to calculate max ISO BW
-				 *
-				 * num_csi_lanes = <>;
-				 * Total number of CSI lanes when all cameras are active
-				 *
-				 * max_lane_speed = <>;
-				 * Max lane speed in Kbit/s
-				 *
-				 * min_bits_per_pixel = <>;
-				 * Min bits per pixel
-				 *
-				 * vi_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the VI ISO case
-				 *
-				 * vi_bw_margin_pct = <>;
-				 * Vi bandwidth margin in percentage
-				 *
-				 * max_pixel_rate = <>;
-				 * Max pixel rate in Kpixel/s for the ISP ISO case
-				 *
-				 * isp_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the ISP ISO case
-				 *
-				 * isp_bw_margin_pct = <>;
-				 * Isp bandwidth margin in percentage
-				 */
-				num_csi_lanes = <12>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-p3783-a00.dtsi

@@ -1391,40 +1391,7 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				 * Physical settings to calculate max ISO BW
-				 *
-				 * num_csi_lanes = <>;
-				 * Total number of CSI lanes when all cameras are active
-				 *
-				 * max_lane_speed = <>;
-				 * Max lane speed in Kbit/s
-				 *
-				 * min_bits_per_pixel = <>;
-				 * Min bits per pixel
-				 *
-				 * vi_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the VI ISO case
-				 *
-				 * vi_bw_margin_pct = <>;
-				 * Vi bandwidth margin in percentage
-				 *
-				 * max_pixel_rate = <>;
-				 * Max pixel rate in Kpixel/s for the ISP ISO case
-				 *
-				 * isp_peak_byte_per_pixel = <>;
-				 * Max byte per pixel for the ISP ISO case
-				 *
-				 * isp_bw_margin_pct = <>;
-				 * Isp bandwidth margin in percentage
-				 */
-				num_csi_lanes = <12>;
-				max_lane_speed = <15000000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-camera-rbpcv2-imx219.dtsi

@@ -684,41 +684,7 @@
 
 			tcp: tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
+
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <240000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3737-0000+p3701-0000-hdr40.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 /*
  * Device-tree overlay for tegra234-p3737-0000-p3701-0000 40-pin
  * Expansion Header.
@@ -30,9 +30,15 @@
 				};
 				hdr40-pin8 {
 					nvidia,pins = "uart1_tx_pr2";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 				};
 				hdr40-pin10 {
 					nvidia,pins = "uart1_rx_pr3";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin11 {
 					nvidia,pins = "uart1_rts_pr4";
@@ -145,10 +151,16 @@
 				hdr40-pin3 {
 					nvidia,pins = "gen8_i2c_scl_pdd1";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin5 {
 					nvidia,pins = "gen8_i2c_sda_pdd2";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin16a {
 					nvidia,pins = "can1_en_pbb1";
@@ -166,9 +178,15 @@
 				};
 				hdr40-pin27 {
 					nvidia,pins = "gen2_i2c_sda_pdd0";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin28 {
 					nvidia,pins = "gen2_i2c_scl_pcc7";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin29 {
 					nvidia,pins = "can0_din_paa1";

overlay/tegra234-p3737-camera-dual-imx274-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 /*
  * Jetson Device-tree overlay for Camera Dual-IMX274 on t23x platforms
  *
@@ -316,15 +316,6 @@
 			ids = "LPRD-dual-imx274-002";
 			sw-modules = "kernel";
 		};
-		__overlay__ {
-			num_csi_lanes = <8>;
-			max_lane_speed = <1500000>;
-			min_bits_per_pixel = <10>;
-			vi_peak_byte_per_pixel = <2>;
-			vi_bw_margin_pct = <25>;
-			isp_peak_byte_per_pixel = <5>;
-			isp_bw_margin_pct = <25>;
-		};
 	};
 	/* pca9646 i2c mux */
 	fragment@27 {

overlay/tegra234-p3737-camera-e3331-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 
 /dts-v1/;
 /plugin/;
@@ -41,14 +41,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				num_csi_lanes = <3>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <800000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 
 				modules {
 					status = "okay";

overlay/tegra234-p3737-camera-eCAM130A-overlay.dts

@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0 */
-/* SPDX-FileCopyrightText: Copyright (c) 2017-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
+/* SPDX-FileCopyrightText: Copyright (c) 2017-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
 
 /dts-v1/;
 /plugin/;
@@ -1194,11 +1194,6 @@
 
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				num_csi_lanes = <12>;
-				max_lane_speed = <2500000>;
-				min_bits_per_pixel = <16>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <67>;
 
 				modules {
 					cam_module0: module0 {

overlay/tegra234-p3737-camera-imx185-overlay.dts

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2022-2023, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2022-2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 /*
  * Jetson Device-tree overlay for Camera IMX185 on t23x platforms
  *
@@ -178,15 +178,6 @@
 			ids = "LPRD-002001", "LPRD-002", "LPRD-001";
 			sw-modules = "kernel";
 		};
-		__overlay__ {
-			num_csi_lanes = <4>;
-			max_lane_speed = <1500000>;
-			min_bits_per_pixel = <10>;
-			vi_peak_byte_per_pixel = <2>;
-			vi_bw_margin_pct = <25>;
-			isp_peak_byte_per_pixel = <5>;
-			isp_bw_margin_pct = <25>;
-		};
 	};
 	/* pca9646 i2c mux */
 	fragment@30 {

overlay/tegra234-p3767-0000-common-hdr40.dtsi

@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
-// SPDX-FileCopyrightText: Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
+// SPDX-FileCopyrightText: Copyright (c) 2021-2024, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
 /*
  * Copyright (c) 2021-2023, NVIDIA CORPORATION & AFFILIATES.  All rights reserved.
  *
@@ -36,9 +36,15 @@
 				};
 				hdr40-pin8 {
 					nvidia,pins = "uart1_tx_pr2";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 				};
 				hdr40-pin10 {
 					nvidia,pins = "uart1_rx_pr3";
+					nvidia,function = "uarta";
+					nvidia,tristate = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin11 {
 					nvidia,pins = "uart1_rts_pr4";
@@ -206,16 +212,28 @@
 				hdr40-pin3 {
 					nvidia,pins = "gen8_i2c_sda_pdd2";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin5 {
 					nvidia,pins = "gen8_i2c_scl_pdd1";
 					nvidia,pin-label = "i2c8";
+					nvidia,function = "i2c8";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin27 {
 					nvidia,pins = "gen2_i2c_sda_pdd0";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 				hdr40-pin28 {
 					nvidia,pins = "gen2_i2c_scl_pcc7";
+					nvidia,function = "i2c2";
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 				};
 			};
 		};

overlay/tegra234-p3767-camera-p3768-imx219-A.dts

@@ -37,41 +37,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx219-C.dts

@@ -37,41 +37,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx219-imx477.dts

@@ -46,41 +46,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-A.dts

@@ -36,41 +36,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-C.dts

@@ -36,41 +36,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-dual-4lane.dts

@@ -43,41 +43,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-dual.dts

@@ -43,41 +43,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

overlay/tegra234-p3767-camera-p3768-imx477-imx219.dts

@@ -50,41 +50,6 @@
 			};
 			tegra-camera-platform {
 				compatible = "nvidia, tegra-camera-platform";
-				/**
-				* Physical settings to calculate max ISO BW
-				*
-				* num_csi_lanes = <>;
-				* Total number of CSI lanes when all cameras are active
-				*
-				* max_lane_speed = <>;
-				* Max lane speed in Kbit/s
-				*
-				* min_bits_per_pixel = <>;
-				* Min bits per pixel
-				*
-				* vi_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the VI ISO case
-				*
-				* vi_bw_margin_pct = <>;
-				* Vi bandwidth margin in percentage
-				*
-				* max_pixel_rate = <>;
-				* Max pixel rate in Kpixel/s for the ISP ISO case
-				*
-				* isp_peak_byte_per_pixel = <>;
-				* Max byte per pixel for the ISP ISO case
-				*
-				* isp_bw_margin_pct = <>;
-				* Isp bandwidth margin in percentage
-				*/
-				num_csi_lanes = <4>;
-				max_lane_speed = <1500000>;
-				min_bits_per_pixel = <10>;
-				vi_peak_byte_per_pixel = <2>;
-				vi_bw_margin_pct = <25>;
-				max_pixel_rate = <7500000>;
-				isp_peak_byte_per_pixel = <5>;
-				isp_bw_margin_pct = <25>;
 				/**
 				 * The general guideline for naming badge_info contains 3 parts, and is as follows,
 				 * The first part is the camera_board_id for the module; if the module is in a FFD

tegra234-p3701-0000.dtsi

@@ -1,146 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0
 
-#include "tegra234.dtsi"
 #include "tegra234-p3701.dtsi"
 
 / {
 	model = "NVIDIA Jetson AGX Orin";
 	compatible = "nvidia,p3701-0000", "nvidia,tegra234";
 
-	bus@0 {
-		i2c@3160000 {
-			status = "okay";
-
-			eeprom@50 {
-				compatible = "atmel,24c02";
-				reg = <0x50>;
-
-				label = "module";
-				vcc-supply = <&vdd_1v8_hs>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		spi@3270000 {
-			status = "okay";
-
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <102000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-			};
-		};
-
-		mmc@3400000 {
-			status = "okay";
-			bus-width = <4>;
-			cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
-			disable-wp;
-		};
-
-		mmc@3460000 {
-			status = "okay";
-			bus-width = <8>;
-			non-removable;
-		};
-
-		padctl@3520000 {
-			vclamp-usb-supply = <&vdd_1v8_ao>;
-			avdd-usb-supply = <&vdd_3v3_ao>;
-
-			ports {
-				usb2-0 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-1 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-2 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-3 {
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-			};
-		};
-
-		rtc@c2a0000 {
-			status = "okay";
-		};
-
-		pmc@c360000 {
-			nvidia,invert-interrupt;
-		};
-	};
-
-	vdd_5v0_sys: regulator-vdd-5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VIN_SYS_5V0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-
-	vdd_1v8_ls: regulator-vdd-1v8-ls {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_LS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_hs: regulator-vdd-1v8-hs {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_HS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_ao: regulator-vdd-1v8-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_AO";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_ao: regulator-vdd-3v3-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_AO";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_PCIE";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
-		regulator-boot-on;
-		enable-active-high;
-	};
-
-	vdd_12v_pcie: regulator-vdd-12v-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_12V_PCIE";
-		regulator-min-microvolt = <12000000>;
-		regulator-max-microvolt = <12000000>;
-		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
-		regulator-boot-on;
-	};
-
 	thermal-zones {
 		tj-thermal {
 			polling-delay = <1000>;

tegra234-p3701-0008.dtsi

@@ -1,112 +1,29 @@
 // SPDX-License-Identifier: GPL-2.0
 
-#include "tegra234.dtsi"
 #include "tegra234-p3701.dtsi"
 
 / {
 	compatible = "nvidia,p3701-0008", "nvidia,tegra234";
 
-	bus@0 {
+	thermal-zones {
-		i2c@3160000 {
+		tj-thermal {
+			polling-delay = <1000>;
+			polling-delay-passive = <1000>;
 			status = "okay";
 
-			eeprom@50 {
+			trips {
-				compatible = "atmel,24c02";
+				tj_trip_active0: active-0 {
-				reg = <0x50>;
+					temperature = <85000>;
-				label = "module";
+					hysteresis = <4000>;
-				vcc-supply = <&vdd_1v8_hs>;
+					type = "active";
-				address-width = <8>;
+				};
-				pagesize = <8>;
+
-				size = <256>;
+				tj_trip_active1: active-1 {
-				read-only;
+					temperature = <105000>;
+					hysteresis = <4000>;
+					type = "active";
+				};
 			};
 		};
-
-		spi@3270000 {
-			status = "okay";
-
-			flash@0 {
-				compatible = "jedec,spi-nor";
-				reg = <0>;
-				spi-max-frequency = <102000000>;
-				spi-tx-bus-width = <4>;
-				spi-rx-bus-width = <4>;
-			};
-		};
-
-		mmc@3460000 {
-			status = "okay";
-			bus-width = <8>;
-			non-removable;
-		};
-
-		i2c@c240000 {
-			status = "okay";
-		};
-
-		rtc@c2a0000 {
-			status = "okay";
-		};
-
-		pmc@c360000 {
-			nvidia,invert-interrupt;
-		};
-	};
-
-	bpmp {
-		i2c {
-			status = "okay";
-
-			thermal-sensor@4c {
-				status = "okay";
-				reg = <0x4c>;
-				vcc-supply = <&vdd_1v8_ao>;
-			};
-		};
-
-		thermal {
-			status = "okay";
-		};
-	};
-
-	vdd_1v8_ao: regulator-vdd-1v8-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_AO";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_hs: regulator-vdd-1v8-hs {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_HS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_1v8_ls: regulator-vdd-1v8-ls {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_LS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-
-	vdd_3v3_ao: regulator-vdd-3v3-ao {
-		compatible = "regulator-fixed";
-		regulator-name = "vdd-AO-3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	vdd_5v0_sys: regulator-vdd-5v0-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VIN_SYS_5V0";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
 	};
 };

tegra234-p3701.dtsi

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 
+#include "tegra234.dtsi"
+
 / {
 	compatible = "nvidia,p3701", "nvidia,tegra234";
 
@@ -44,5 +46,181 @@
 				status = "okay";
 			};
 		};
+
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@50 {
+				compatible = "atmel,24c02";
+				reg = <0x50>;
+
+				label = "module";
+				vcc-supply = <&vdd_1v8_hs>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
+		spi@3270000 {
+			status = "okay";
+
+			flash@0 {
+				compatible = "jedec,spi-nor";
+				reg = <0>;
+				spi-max-frequency = <102000000>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+			};
+		};
+
+		mmc@3460000 {
+			status = "okay";
+			bus-width = <8>;
+			non-removable;
+		};
+
+		padctl@3520000 {
+			vclamp-usb-supply = <&vdd_1v8_ao>;
+			avdd-usb-supply = <&vdd_3v3_ao>;
+
+			ports {
+				usb2-0 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-1 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-2 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+
+				usb2-3 {
+					vbus-supply = <&vdd_5v0_sys>;
+				};
+			};
+		};
+
+		i2c@c240000 {
+			status = "okay";
+
+			power-sensor@40 {
+				compatible = "ti,ina3221";
+				reg = <0x40>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "VDD_GPU_SOC";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDD_CPU_CV";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "VIN_SYS_5V0";
+					shunt-resistor-micro-ohms = <2000>;
+					ti,summation-disable;
+				};
+			};
+
+			power-sensor@41 {
+				compatible = "ti,ina3221";
+				reg = <0x41>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					status = "disabled";
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDDQ_VDD2_1V8AO";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					status = "disabled";
+				};
+			};
+		};
+
+		rtc@c2a0000 {
+			status = "okay";
+		};
+
+		pmc@c360000 {
+			nvidia,invert-interrupt;
+		};
+	};
+
+	bpmp {
+		i2c {
+			status = "okay";
+
+			thermal-sensor@4c {
+				compatible = "ti,tmp451";
+				status = "okay";
+				reg = <0x4c>;
+				vcc-supply = <&vdd_1v8_ao>;
+			};
+		};
+
+		thermal {
+			status = "okay";
+		};
+	};
+
+	vdd_1v8_ao: regulator-vdd-1v8-ao {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_AO";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_hs: regulator-vdd-1v8-hs {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_HS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_1v8_ls: regulator-vdd-1v8-ls {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_LS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_ao: regulator-vdd-3v3-ao {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_AO";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	vdd_5v0_sys: regulator-vdd-5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VIN_SYS_5V0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+		regulator-boot-on;
 	};
 };

tegra234-p3737-0000+p3701-0000.dts

@@ -3,9 +3,9 @@
 
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/sound/rt5640.h>
 
 #include "tegra234-p3701-0000.dtsi"
-#include "tegra234-p3737-0000.dtsi"
 
 / {
 	model = "NVIDIA Jetson AGX Orin Developer Kit";
@@ -22,23 +22,97 @@
 	};
 
 	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901000 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+			};
+		};
+
 		serial@3100000 {
 			compatible = "nvidia,tegra194-hsuart";
 			reset-names = "serial";
 			status = "okay";
 		};
 
+		i2c@3160000 {
+			status = "okay";
+
+			eeprom@56 {
+				compatible = "atmel,24c02";
+				reg = <0x56>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_sys>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
+		};
+
 		serial@31d0000 {
 			current-speed = <115200>;
 			status = "okay";
 		};
 
+		i2c@31e0000 {
+			status = "okay";
+
+			audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+				sound-name-prefix = "CVB-RT";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s1_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+		};
+
+		pwm@3280000 {
+			status = "okay";
+		};
+
 		pwm@32a0000 {
 			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
 			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
 			status = "okay";
 		};
 
+		pwm@32c0000 {
+			status = "okay";
+		};
+
+		pwm@32f0000 {
+			status = "okay";
+		};
+
+		mmc@3400000 {
+			status = "okay";
+			bus-width = <4>;
+			cd-gpios = <&gpio TEGRA234_MAIN_GPIO(G, 7) GPIO_ACTIVE_LOW>;
+			disable-wp;
+		};
+
 		hda@3510000 {
 			nvidia,model = "NVIDIA Jetson AGX Orin HDA";
 			status = "okay";
@@ -90,6 +164,7 @@
 					mode = "otg";
 					usb-role-switch;
 					status = "okay";
+
 					port {
 						hs_typec_p1: endpoint {
 							remote-endpoint = <&hs_ucsi_ccg_p1>;
@@ -100,6 +175,7 @@
 				usb2-1 {
 					mode = "host";
 					status = "okay";
+
 					port {
 						hs_typec_p0: endpoint {
 							remote-endpoint = <&hs_ucsi_ccg_p0>;
@@ -120,6 +196,7 @@
 				usb3-0 {
 					nvidia,usb2-companion = <1>;
 					status = "okay";
+
 					port {
 						ss_typec_p0: endpoint {
 							remote-endpoint = <&ss_ucsi_ccg_p0>;
@@ -130,6 +207,7 @@
 				usb3-1 {
 					nvidia,usb2-companion = <0>;
 					status = "okay";
+
 					port {
 						ss_typec_p1: endpoint {
 							remote-endpoint = <&ss_ucsi_ccg_p1>;
@@ -211,6 +289,7 @@
 
 						port@0 {
 							reg = <0>;
+
 							hs_ucsi_ccg_p0: endpoint {
 								remote-endpoint = <&hs_typec_p0>;
 							};
@@ -218,6 +297,7 @@
 
 						port@1 {
 							reg = <1>;
+
 							ss_ucsi_ccg_p0: endpoint {
 								remote-endpoint = <&ss_typec_p0>;
 							};
@@ -237,6 +317,7 @@
 
 						port@0 {
 							reg = <0>;
+
 							hs_ucsi_ccg_p1: endpoint {
 								remote-endpoint = <&hs_typec_p1>;
 							};
@@ -244,6 +325,7 @@
 
 						port@1 {
 							reg = <1>;
+
 							ss_ucsi_ccg_p1: endpoint {
 								remote-endpoint = <&ss_typec_p1>;
 							};
@@ -333,8 +415,11 @@
 		};
 	};
 
-	pwm-fan {
+	fan: pwm-fan {
+		compatible = "pwm-fan";
 		cooling-levels = <66 215 255>;
+		pwms = <&pwm3 0 45334>;
+		#cooling-cells = <2>;
 	};
 
 	serial {
@@ -436,4 +521,31 @@
 			};
 		};
 	};
+
+	vdd_1v8_sys: regulator-vdd-1v8-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_1V8_SYS";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-always-on;
+	};
+
+	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_PCIE";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
+
+	vdd_12v_pcie: regulator-vdd-12v-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_12V_PCIE";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) GPIO_ACTIVE_LOW>;
+		regulator-boot-on;
+	};
 };

tegra234-p3737-0000.dtsi

@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/sound/rt5640.h>
-
-/ {
-	compatible = "nvidia,p3737-0000";
-
-	bus@0 {
-		aconnect@2900000 {
-			ahub@2900800 {
-				i2s@2901000 {
-					ports {
-						port@1 {
-							endpoint {
-								dai-format = "i2s";
-								remote-endpoint = <&rt5640_ep>;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		i2c@3160000 {
-			status = "okay";
-
-			eeprom@56 {
-				compatible = "atmel,24c02";
-				reg = <0x56>;
-
-				label = "system";
-				vcc-supply = <&vdd_1v8_sys>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		i2c@31e0000 {
-			status = "okay";
-
-			audio-codec@1c {
-				compatible = "realtek,rt5640";
-				reg = <0x1c>;
-				interrupt-parent = <&gpio>;
-				interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>;
-				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
-				clock-names = "mclk";
-				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
-				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
-				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
-				sound-name-prefix = "CVB-RT";
-
-				port {
-					rt5640_ep: endpoint {
-						remote-endpoint = <&i2s1_dap>;
-						mclk-fs = <256>;
-					};
-				};
-			};
-		};
-
-		pwm@3280000 {
-			status = "okay";
-		};
-
-		pwm@32c0000 {
-			status = "okay";
-		};
-
-		pwm@32f0000 {
-			status = "okay";
-		};
-	};
-
-	fan: pwm-fan {
-		compatible = "pwm-fan";
-		pwms = <&pwm3 0 45334>;
-		#cooling-cells = <2>;
-	};
-
-	vdd_1v8_sys: regulator-vdd-1v8-sys {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_1V8_SYS";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		regulator-always-on;
-	};
-};

tegra234-p3740-0002+p3701-0008.dts

@@ -3,8 +3,8 @@
 
 #include <dt-bindings/input/linux-event-codes.h>
 #include <dt-bindings/input/gpio-keys.h>
+#include <dt-bindings/sound/rt5640.h>
 #include "tegra234-p3701-0008.dtsi"
-#include "tegra234-p3740-0002.dtsi"
 
 / {
 	model = "NVIDIA IGX Orin Development Kit";
@@ -20,6 +20,32 @@
 	};
 
 	bus@0 {
+		aconnect@2900000 {
+			ahub@2900800 {
+				i2s@2901300 {
+					ports {
+						port@1 {
+							endpoint {
+								dai-format = "i2s";
+								remote-endpoint = <&rt5640_ep>;
+							};
+						};
+					};
+				};
+
+				i2s@2901500 {
+					ports {
+						port@1 {
+							endpoint {
+								bitclock-master;
+								frame-master;
+							};
+						};
+					};
+				};
+			};
+		};
+
 		serial@3100000 {
 			compatible = "nvidia,tegra194-hsuart";
 			reset-names = "serial";
@@ -45,6 +71,40 @@
 		i2c@31c0000 {
 			status = "okay";
 
+			rt5640: audio-codec@1c {
+				compatible = "realtek,rt5640";
+				reg = <0x1c>;
+				interrupt-parent = <&gpio>;
+				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
+				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
+				clock-names = "mclk";
+
+				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
+				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
+				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
+
+				sound-name-prefix = "CVB-RT";
+
+				port {
+					rt5640_ep: endpoint {
+						remote-endpoint = <&i2s4_dap>;
+						mclk-fs = <256>;
+					};
+				};
+			};
+
+			/* carrier board ID EEPROM */
+			eeprom@55 {
+				compatible = "atmel,24c02";
+				reg = <0x55>;
+
+				label = "system";
+				vcc-supply = <&vdd_1v8_ls>;
+				address-width = <8>;
+				pagesize = <8>;
+				size = <256>;
+				read-only;
+			};
 		};
 
 		i2c@31e0000 {
@@ -60,6 +120,115 @@
 			status = "okay";
 		};
 
+		padctl@3520000 {
+			status = "okay";
+
+			pads {
+				usb2 {
+					lanes {
+						usb2-0 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-1 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-2 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb2-3 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+					};
+				};
+
+				usb3 {
+					lanes {
+						usb3-0 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb3-1 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+
+						usb3-2 {
+							nvidia,function = "xusb";
+							status = "okay";
+						};
+					};
+				};
+			};
+
+			ports {
+				usb2-0 {
+					mode = "otg";
+					usb-role-switch;
+					status = "okay";
+				};
+
+				usb2-1 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-2 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb2-3 {
+					mode = "host";
+					status = "okay";
+				};
+
+				usb3-0 {
+					nvidia,usb2-companion = <2>;
+					status = "okay";
+				};
+
+				usb3-1 {
+					nvidia,usb2-companion = <0>;
+					status = "okay";
+				};
+
+				usb3-2 {
+					nvidia,usb2-companion = <1>;
+					status = "okay";
+				};
+			};
+		};
+
+		usb@3550000 {
+			status = "okay";
+
+			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
+			phy-names = "usb2-0", "usb3-0";
+		};
+
+		usb@3610000 {
+			status = "okay";
+
+			phys =	<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
+				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
+				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
+			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
+				"usb3-0", "usb3-1", "usb3-2";
+		};
+
 		fuse@3810000 {
 			status = "okay";
 		};
@@ -70,6 +239,37 @@
 
 		i2c@c250000 {
 			status = "okay";
+
+			power-sensor@41 {
+				compatible = "ti,ina3221";
+				reg = <0x41>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "CVB_ATX_12V";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "CVB_ATX_3V3";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "CVB_ATX_5V";
+					shunt-resistor-micro-ohms = <2000>;
+				};
+			};
+
+			power-sensor@44 {
+				compatible = "ti,ina219";
+				reg = <0x44>;
+				shunt-resistor = <2000>;
+			};
 		};
 
 		host1x@13e00000 {
@@ -235,4 +435,32 @@
 			  "CVB-RT DMIC1",		"CVB-RT MIC",
 			  "CVB-RT DMIC2",		"CVB-RT MIC";
 	};
+
+	vdd_3v3_dp: regulator-vdd-3v3-dp {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_DP";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vdd_3v3_sys>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
+		enable-active-high;
+		regulator-always-on;
+	};
+
+	vdd_3v3_sys: regulator-vdd-3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_SYS";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	vdd_3v3_wifi: regulator-vdd-3v3-wifi {
+		compatible = "regulator-fixed";
+		regulator-name = "VDD_3V3_WIFI";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
 };

tegra234-p3740-0002.dtsi

@@ -1,221 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-
-#include <dt-bindings/sound/rt5640.h>
-
-/ {
-	compatible = "nvidia,p3740-0002";
-
-	bus@0 {
-		aconnect@2900000 {
-			ahub@2900800 {
-				i2s@2901300 {
-					ports {
-						port@1 {
-							endpoint {
-								dai-format = "i2s";
-								remote-endpoint = <&rt5640_ep>;
-							};
-						};
-					};
-				};
-
-				i2s@2901500 {
-					ports {
-						port@1 {
-							endpoint {
-								bitclock-master;
-								frame-master;
-							};
-						};
-					};
-				};
-			};
-		};
-
-		i2c@31c0000 {
-			rt5640: audio-codec@1c {
-				compatible = "realtek,rt5640";
-				reg = <0x1c>;
-
-				clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>;
-				clock-names = "mclk";
-
-				realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>;
-				realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>;
-				realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>;
-
-				/* Codec IRQ output */
-				interrupt-parent = <&gpio>;
-				interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>;
-
-				#sound-dai-cells = <1>;
-				sound-name-prefix = "CVB-RT";
-
-				status = "okay";
-
-				port {
-					rt5640_ep: endpoint {
-						remote-endpoint = <&i2s4_dap>;
-						mclk-fs = <256>;
-					};
-				};
-			};
-
-			/* carrier board ID EEPROM */
-			eeprom@55 {
-				compatible = "atmel,24c02";
-				reg = <0x55>;
-
-				label = "system";
-				vcc-supply = <&vdd_1v8_ls>;
-				address-width = <8>;
-				pagesize = <8>;
-				size = <256>;
-				read-only;
-			};
-		};
-
-		padctl@3520000 {
-			vclamp-usb-supply = <&vdd_1v8_ao>;
-			avdd-usb-supply = <&vdd_3v3_ao>;
-			status = "okay";
-
-			pads {
-				usb2 {
-					lanes {
-						usb2-0 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-1 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-2 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb2-3 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-					};
-				};
-
-				usb3 {
-					lanes {
-						usb3-0 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb3-1 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-
-						usb3-2 {
-							nvidia,function = "xusb";
-							status = "okay";
-						};
-					};
-				};
-			};
-
-			ports {
-				usb2-0 {
-					mode = "otg";
-					usb-role-switch;
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-1 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-2 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb2-3 {
-					mode = "host";
-					status = "okay";
-					vbus-supply = <&vdd_5v0_sys>;
-				};
-
-				usb3-0 {
-					nvidia,usb2-companion = <2>;
-					status = "okay";
-				};
-
-				usb3-1 {
-					nvidia,usb2-companion = <0>;
-					status = "okay";
-				};
-
-				usb3-2 {
-					nvidia,usb2-companion = <1>;
-					status = "okay";
-				};
-			};
-		};
-
-		usb@3550000 {
-			status = "okay";
-
-			phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>;
-			phy-names = "usb2-0", "usb3-0";
-		};
-
-		usb@3610000 {
-			status = "okay";
-
-			phys =	<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-2}>,
-				<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-1}>,
-				<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>;
-			phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3",
-				"usb3-0", "usb3-1", "usb3-2";
-		};
-	};
-
-	vdd_3v3_dp: regulator-vdd-3v3-dp {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_DP";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				vin-supply = <&vdd_3v3_sys>;
-				gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>;
-				enable-active-high;
-				regulator-always-on;
-	};
-
-	vdd_3v3_sys: regulator-vdd-3v3-sys {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_SYS";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-	};
-
-	vdd_3v3_wifi: regulator-vdd-3v3-wifi {
-				compatible = "regulator-fixed";
-				regulator-name = "VDD_3V3_WIFI";
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
-				regulator-boot-on;
-				enable-active-high;
-	};
-};

tegra234-p3767.dtsi

@@ -83,6 +83,35 @@
 			avdd-usb-supply = <&vdd_3v3_ao>;
 		};
 
+		i2c@c240000 {
+			status = "okay";
+
+			power-sensor@40 {
+				compatible = "ti,ina3221";
+				reg = <0x40>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				input@0 {
+					reg = <0x0>;
+					label = "VDD_IN";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+
+				input@1 {
+					reg = <0x1>;
+					label = "VDD_CPU_GPU_CV";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+
+				input@2 {
+					reg = <0x2>;
+					label = "VDD_SOC";
+					shunt-resistor-micro-ohms = <5000>;
+				};
+			};
+		};
+
 		rtc@c2a0000 {
 			status = "okay";
 		};

tegra234-p3768-0000+p3767-0000.dts

@@ -1,111 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/linux-event-codes.h>
+#include "tegra234-p3768-0000+p3767.dtsi"
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
 
 / {
 	compatible = "nvidia,p3768-0000+p3767-0000", "nvidia,p3767-0000", "nvidia,tegra234";
 	model = "NVIDIA Jetson Orin NX Engineering Reference Developer Kit";
 
-	aliases {
-		serial1 = &uarta;
-		serial2 = &uarte;
-	};
-
 	bus@0 {
-		serial@3100000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		serial@3140000 {
-			compatible = "nvidia,tegra194-hsuart";
-			reset-names = "serial";
-			status = "okay";
-		};
-
-		pwm@32a0000 {
-			assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>;
-			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
-			status = "okay";
-		};
-
 		hda@3510000 {
 			nvidia,model = "NVIDIA Jetson Orin NX HDA";
 		};
-
-		padctl@3520000 {
-			status = "okay";
-		};
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		key-force-recovery {
-			label = "Force Recovery";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <BTN_1>;
-		};
-
-		key-power {
-			label = "Power";
-			gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_POWER>;
-			wakeup-event-action = <EV_ACT_ASSERTED>;
-			wakeup-source;
-		};
-
-		key-suspend {
-			label = "Suspend";
-			gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>;
-			linux,input-type = <EV_KEY>;
-			linux,code = <KEY_SLEEP>;
-		};
-	};
-
-	pwm-fan {
-		cooling-levels = <0 88 187 255>;
-	};
-
-	vdd_3v3_pcie: regulator-vdd-3v3-pcie {
-		compatible = "regulator-fixed";
-		regulator-name = "VDD_3V3_PCIE";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio_aon TEGRA234_AON_GPIO(AA, 5) GPIO_ACTIVE_HIGH>;
-		enable-active-high;
 	};
 
 	sound {
 		label = "NVIDIA Jetson Orin NX APE";
 	};
-
-	thermal-zones {
-		tj-thermal {
-			cooling-maps {
-				map-active-0 {
-					cooling-device = <&fan 0 1>;
-					trip = <&tj_trip_active0>;
-				};
-
-				map-active-1 {
-					cooling-device = <&fan 1 2>;
-					trip = <&tj_trip_active1>;
-				};
-
-				map-active-2 {
-					cooling-device = <&fan 2 3>;
-					trip = <&tj_trip_active2>;
-				};
-			};
-		};
-	};
 };

tegra234-p3768-0000+p3767-0005.dts

@@ -1,11 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 /dts-v1/;
 
-#include <dt-bindings/input/linux-event-codes.h>
+#include "tegra234-p3768-0000+p3767.dtsi"
-#include <dt-bindings/input/gpio-keys.h>
-
-#include "tegra234-p3767.dtsi"
-#include "tegra234-p3768-0000.dtsi"
 
 / {
 	compatible = "nvidia,p3768-0000+p3767-0005", "nvidia,p3767-0005", "nvidia,tegra234";
@@ -17,32 +13,7 @@
 		};
 	};
 
-	pwm-fan {
-		cooling-levels = <0 88 187 255>;
-	};
-
 	sound {
 		label = "NVIDIA Jetson Orin Nano APE";
 	};
-
-	thermal-zones {
-		tj-thermal {
-			cooling-maps {
-				map-active-0 {
-					cooling-device = <&fan 0 1>;
-					trip = <&tj_trip_active0>;
-				};
-
-				map-active-1 {
-					cooling-device = <&fan 1 2>;
-					trip = <&tj_trip_active1>;
-				};
-
-				map-active-2 {
-					cooling-device = <&fan 2 3>;
-					trip = <&tj_trip_active2>;
-				};
-			};
-		};
-	};
 };

tegra234-p3768-0000+p3767.dtsi

@@ -1,10 +1,16 @@
 // SPDX-License-Identifier: GPL-2.0
 
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/gpio-keys.h>
+
+#include "tegra234-p3767.dtsi"
+
 / {
-	compatible = "nvidia,p3768-0000";
 
 	aliases {
 		serial0 = &tcu;
+		serial1 = &uarta;
+		serial2 = &uarte;
 	};
 
 	chosen {
@@ -12,6 +18,18 @@
 	};
 
 	bus@0 {
+		serial@3100000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
+		serial@3140000 {
+			compatible = "nvidia,tegra194-hsuart";
+			reset-names = "serial";
+			status = "okay";
+		};
+
 		i2c@3160000 {
 			status = "okay";
 
@@ -168,6 +186,18 @@
 			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
 		};
 
+		pcie-ep@14160000 {/* C4 - End Point */
+			phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+					<&p2u_hsio_7>;
+			phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+			reset-gpios = <&gpio
+					TEGRA234_MAIN_GPIO(L, 1)
+					GPIO_ACTIVE_LOW>;
+			nvidia,refclk-select-gpios = <&gpio_aon
+							TEGRA234_AON_GPIO(AA, 4)
+							GPIO_ACTIVE_HIGH>;
+		};
+
 		/* C7 - M.2 Key-M */
 		pcie@141e0000 {
 			status = "okay";
@@ -210,6 +240,7 @@
 		compatible = "pwm-fan";
 		pwms = <&pwm3 0 45334>;
 		#cooling-cells = <2>;
+		cooling-levels = <0 88 187 255>;
 	};
 
 	vdd_1v8_sys: regulator-vdd-1v8-sys {
@@ -241,4 +272,25 @@
 	serial {
 		status = "okay";
 	};
+
+	thermal-zones {
+		tj-thermal {
+			cooling-maps {
+				map-active-0 {
+					cooling-device = <&fan 0 1>;
+					trip = <&tj_trip_active0>;
+				};
+
+				map-active-1 {
+					cooling-device = <&fan 1 2>;
+					trip = <&tj_trip_active1>;
+				};
+
+				map-active-2 {
+					cooling-device = <&fan 2 3>;
+					trip = <&tj_trip_active2>;
+				};
+			};
+		};
+	};
 };

tegra234.dtsi

@@ -2763,6 +2763,8 @@
 			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&bpmp TEGRA234_CLK_UARTA>;
 			resets = <&bpmp TEGRA234_RESET_UARTA>;
+			dmas = <&gpcdma 8>, <&gpcdma 8>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -3252,23 +3254,8 @@
 			      <0x0 0x03650000 0x0 0x10000>;
 			reg-names = "hcd", "fpci", "bar2";
 
-			interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-				     <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
-				     <&pmc 76 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 77 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 78 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 79 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 80 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 81 IRQ_TYPE_LEVEL_HIGH>,
-				     <&pmc 82 IRQ_TYPE_LEVEL_HIGH>;
-			/*
-                   wake0, wake1, wake2 are for USB3.0 ports
-                   wake3, wake4, wake5, wake6 are for USB2.0 ports
-			*/
-			interrupt-names = "xhci", "mbox",
-				  "wake0", "wake1", "wake2", "wake3",
-				  "wake4", "wake5", "wake6";
-
 
 			clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
 				 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
@@ -4855,6 +4842,37 @@
 			status = "disabled";
 		};
 
+		pcie-ep@14160000 {
+			compatible = "nvidia,tegra234-pcie-ep";
+			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+			reg = <0x00 0x14160000 0x0 0x00020000     /* appl registers (128K)      */
+				0x00 0x36040000 0x0 0x00040000    /* iATU_DMA reg space (256K)  */
+				0x00 0x36080000 0x0 0x00040000    /* DBI space (256K)           */
+				0x21 0x40000000 0x3 0x00000000>;  /* Address Space (12G)        */
+			reg-names = "appl", "atu_dma", "dbi", "addr_space";
+			num-lanes = <4>;
+			clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+			clock-names = "core";
+			resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+			       <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+			reset-names = "apb", "core";
+
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
+			interrupt-names = "intr";
+			nvidia,bpmp = <&bpmp 4>;
+			nvidia,enable-ext-refclk;
+			nvidia,aspm-cmrt-us = <60>;
+			nvidia,aspm-pwr-on-t-us = <20>;
+			nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
+				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
+			interconnect-names = "dma-mem", "write";
+			iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		pcie@14180000 {
 			compatible = "nvidia,tegra234-pcie";
 			power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;