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gpu: nvgpu: remove nvgpu_next files

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Remove all nvgpu_next files and move the code into corresponding
nvgpu files.

Merge nvgpu-next-*.yaml into nvgpu-.yaml files.

Jira NVGPU-4771

Change-Id: I595311be3c7bbb4f6314811e68712ff01763801e
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547557
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2021-06-19 10:17:51 +00:00
committed by mobile promotions
parent c7d43f5292
commit f9cac0c64d
126 changed files with 2351 additions and 4554 deletions
Download Patch File Download Diff File Expand all files Collapse all files

136
drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
View File

@@ -31,6 +31,10 @@
#include <nvgpu/acr.h>
#include <nvgpu/bug.h>
#include <nvgpu/soc.h>
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include <nvgpu/riscv.h>
#include <nvgpu/io.h>
#endif
#include "acr_bootstrap.h"
#include "acr_priv.h"
@@ -252,3 +256,135 @@ err_free_ucode:
acr_desc->acr_fw = NULL;
return err;
}
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */
#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */
static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_release_firmware(g, acr->acr_asc.manifest_fw);
nvgpu_release_firmware(g, acr->acr_asc.code_fw);
nvgpu_release_firmware(g, acr->acr_asc.data_fw);
}
static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
{
int err = 0;
acr->manifest_fw = nvgpu_request_firmware(g,
acr->acr_manifest_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->manifest_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_manifest_name, g->name);
return -ENOENT;
}
acr->code_fw = nvgpu_request_firmware(g,
acr->acr_code_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->code_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_code_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
return -ENOENT;
}
acr->data_fw = nvgpu_request_firmware(g,
acr->acr_data_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->data_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_data_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
nvgpu_release_firmware(g, acr->code_fw);
return -ENOENT;
}
return err;
}
static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn,
signed int timeoutms)
{
u32 reg = 0;
do {
reg = flcn->g->ops.falcon.get_brom_retcode(flcn);
if (flcn->g->ops.falcon.check_brom_passed(reg)) {
break;
}
if (timeoutms <= 0) {
return false;
}
nvgpu_msleep(10);
timeoutms -= 10;
} while (true);
return true;
}
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
{
int err = 0;
bool brom_complete = false;
u32 timeout = 0;
u64 acr_sysmem_desc_addr = 0LL;
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err !=0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
&acr->acr_asc.acr_falcon2_sysmem_desc);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn,
acr->acr_asc.manifest_fw,
acr->acr_asc.code_fw,
acr->acr_asc.data_fw,
acr_sysmem_desc_addr);
if (nvgpu_platform_is_silicon(g)) {
timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
brom_complete = nvgpu_acr_wait_for_riscv_brom_completion(
acr->acr_asc.acr_flcn, timeout);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
if (brom_complete == false) {
nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout);
err = -ETIMEDOUT;
} else {
nvgpu_info(g, "RISCV BROM passed");
}
/* wait for complete & halt */
if (nvgpu_platform_is_silicon(g)) {
timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
ga10b_riscv_release_firmware(g, acr);
return err;
}
#endif

9
drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
View File

@@ -24,12 +24,10 @@
#define ACR_BOOTSTRAP_H
#include "nvgpu_acr_interface.h"
#ifdef CONFIG_NVGPU_NON_FUSA
#include "common/acr/nvgpu_next_acr_bootstrap.h"
#endif
struct gk20a;
struct nvgpu_acr;
struct hs_acr;
struct flcn_acr_region_prop_v0 {
u32 start_addr;
@@ -136,4 +134,9 @@ int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc,
int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc);
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
#endif
#endif /* ACR_BOOTSTRAP_H */

167
drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c
View File

@@ -1,167 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/dma.h>
#include <nvgpu/timers.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/firmware.h>
#include <nvgpu/riscv.h>
#include <nvgpu/pmu.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/acr.h>
#include <nvgpu/bug.h>
#include <nvgpu/soc.h>
#include <nvgpu/io.h>
#include "common/acr/acr_bootstrap.h"
#include "common/acr/acr_priv.h"
#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */
#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */
static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_release_firmware(g, acr->acr_asc.manifest_fw);
nvgpu_release_firmware(g, acr->acr_asc.code_fw);
nvgpu_release_firmware(g, acr->acr_asc.data_fw);
}
static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
{
int err = 0;
acr->manifest_fw = nvgpu_request_firmware(g,
acr->acr_manifest_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->manifest_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_manifest_name, g->name);
return -ENOENT;
}
acr->code_fw = nvgpu_request_firmware(g,
acr->acr_code_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->code_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_code_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
return -ENOENT;
}
acr->data_fw = nvgpu_request_firmware(g,
acr->acr_data_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->data_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_data_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
nvgpu_release_firmware(g, acr->code_fw);
return -ENOENT;
}
return err;
}
static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn,
signed int timeoutms)
{
u32 reg = 0;
do {
reg = flcn->g->ops.falcon.get_brom_retcode(flcn);
if (flcn->g->ops.falcon.check_brom_passed(reg)) {
break;
}
if (timeoutms <= 0) {
return false;
}
nvgpu_msleep(10);
timeoutms -= 10;
} while (true);
return true;
}
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
{
int err = 0;
bool brom_complete = false;
u32 timeout = 0;
u64 acr_sysmem_desc_addr = 0LL;
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err !=0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
&acr->acr_asc.acr_falcon2_sysmem_desc);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn,
acr->acr_asc.manifest_fw,
acr->acr_asc.code_fw,
acr->acr_asc.data_fw,
acr_sysmem_desc_addr);
if (nvgpu_platform_is_silicon(g)) {
timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
brom_complete = nvgpu_acr_wait_for_riscv_brom_completion(
acr->acr_asc.acr_flcn, timeout);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
if (brom_complete == false) {
nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout);
err = -ETIMEDOUT;
} else {
nvgpu_info(g, "RISCV BROM passed");
}
/* wait for complete & halt */
if (nvgpu_platform_is_silicon(g)) {
timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
ga10b_riscv_release_firmware(g, acr);
return err;
}

32
drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h
View File

@@ -1,32 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ACR_BOOTSTRAP_H
#define NVGPU_NEXT_ACR_BOOTSTRAP_H
struct gk20a;
struct nvgpu_acr;
struct hs_acr;
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* NVGPU_NEXT_ACR_BOOTSTRAP_H */

69
drivers/gpu/nvgpu/common/cic/cic.c
View File

@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/kmem.h>
#include <nvgpu/lock.h>
#include <nvgpu/log.h>
#include <nvgpu/cic.h>
#include <nvgpu/nvgpu_err_info.h>
@@ -159,3 +160,71 @@ int nvgpu_cic_get_num_hw_modules(struct gk20a *g)
return g->cic->num_hw_modules;
}
#if defined(CONFIG_NVGPU_NON_FUSA)
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}
#endif

92
drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c
View File

@@ -1,92 +0,0 @@
/*
*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/lock.h>
#include <nvgpu/cic.h>
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}

24
drivers/gpu/nvgpu/common/fb/fb.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,3 +39,25 @@ int nvgpu_init_fb_support(struct gk20a *g)
}
return 0;
}
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_fb_vab_init_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.init != NULL) {
err = g->ops.fb.vab.init(g);
}
return err;
}
int nvgpu_fb_vab_teardown_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.teardown != NULL) {
err = g->ops.fb.vab.teardown(g);
}
return err;
}
#endif

44
drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c
View File

@@ -1,44 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/fb.h>
int nvgpu_fb_vab_init_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.init != NULL) {
err = g->ops.fb.vab.init(g);
}
return err;
}
int nvgpu_fb_vab_teardown_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.teardown != NULL) {
err = g->ops.fb.vab.teardown(g);
}
return err;
}

55
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -706,6 +706,61 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg)
return engines;
}
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev)
{
struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
/*
* Currently due to the nature of the nvgpu_next repo, this will still
* be called even on non-ga10b systems. Eventually this code will fold into
* the nvgpu-linux repo, at which point this logic will be present in
* nvgpu_engine_init_one_dev().
*
* In any event, the purpose of this is to make sure we _don't_ execute
* this code pre-ga10b. We can check for HALs that only exist on ga10x to
* short circuit.
*/
if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
return 0;
}
/*
* Init PBDMA info for this device; needs FIFO to be alive to do this.
* SW expects at least pbdma instance0 to be valid.
*
* See JIRA NVGPU-4980 for multiple pbdma support.
*/
g->ops.runlist.get_pbdma_info(g,
dev->next.rl_pri_base,
&dev_rw->next.pbdma_info);
if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
NVGPU_INVALID_PBDMA_ID) {
nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
dev->engine_id);
return -EINVAL;
}
dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u",
dev->inst_id, dev->runlist_id, dev->fault_id);
nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u",
dev->intr_id, dev->reset_id);
nvgpu_log(g, gpu_dbg_device, " engine_type %u",
dev->type);
nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x",
dev->reset_id, dev->next.rleng_id);
nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x",
dev->next.rl_pri_base);
return 0;
}
#endif
static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f,
const struct nvgpu_device *dev)
{

79
drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c
View File

@@ -1,79 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
#include <nvgpu/runlist.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h>
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev)
{
struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
/*
* Currently due to the nature of the nvgpu_next repo, this will still
* be called even on non-ga10b systems. Eventually this code will fold into
* the nvgpu-linux repo, at which point this logic will be present in
* nvgpu_engine_init_one_dev().
*
* In any event, the purpose of this is to make sure we _don't_ execute
* this code pre-ga10b. We can check for HALs that only exist on ga10x to
* short circuit.
*/
if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
return 0;
}
/*
* Init PBDMA info for this device; needs FIFO to be alive to do this.
* SW expects at least pbdma instance0 to be valid.
*
* See JIRA NVGPU-4980 for multiple pbdma support.
*/
g->ops.runlist.get_pbdma_info(g,
dev->next.rl_pri_base,
&dev_rw->next.pbdma_info);
if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
NVGPU_INVALID_PBDMA_ID) {
nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
dev->engine_id);
return -EINVAL;
}
dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u",
dev->inst_id, dev->runlist_id, dev->fault_id);
nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u",
dev->intr_id, dev->reset_id);
nvgpu_log(g, gpu_dbg_device, " engine_type %u",
dev->type);
nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x",
dev->reset_id, dev->next.rleng_id);
nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x",
dev->next.rl_pri_base);
return 0;
}

113
drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c
View File

@@ -1,113 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/runlist.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/gk20a.h>
static void nvgpu_runlist_init_engine_info(struct gk20a *g,
struct nvgpu_runlist *runlist,
const struct nvgpu_device *dev)
{
u32 i = 0U;
/*
* runlist_pri_base, chram_bar0_offset and pbdma_info
* will get over-written with same info, if multiple engines
* are present on same runlist. Required optimization will be
* done as part of JIRA NVGPU-4980
*/
runlist->nvgpu_next.runlist_pri_base =
dev->next.rl_pri_base;
runlist->nvgpu_next.chram_bar0_offset =
g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x",
runlist->id, runlist->nvgpu_next.runlist_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x",
runlist->id, runlist->nvgpu_next.chram_bar0_offset);
runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info;
for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
nvgpu_log(g, gpu_dbg_info,
"runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x",
runlist->id, i,
runlist->nvgpu_next.pbdma_info->pbdma_id[i], i,
runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]);
}
runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev;
}
static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
struct nvgpu_runlist *runlist)
{
u32 pbdma_mask = 0U;
u32 i;
u32 pbdma_id;
nvgpu_assert(runlist != NULL);
for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i];
if (pbdma_id != NVGPU_INVALID_PBDMA_ID)
pbdma_mask |= BIT32(pbdma_id);
}
return pbdma_mask;
}
void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
{
struct nvgpu_runlist *runlist;
const struct nvgpu_device *dev;
u32 i, j;
nvgpu_log_fn(g, " ");
if (g->is_virtual) {
return;
}
for (i = 0U; i < f->num_runlists; i++) {
runlist = &f->active_runlists[i];
nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i);
for (j = 0U; j < f->num_engines; j++) {
dev = f->active_engines[j];
if (dev->runlist_id == runlist->id) {
runlist->eng_bitmask |= BIT32(dev->engine_id);
nvgpu_runlist_init_engine_info(g, runlist, dev);
}
}
runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist);
nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask);
nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
}
nvgpu_log_fn(g, "done");
}

90
drivers/gpu/nvgpu/common/fifo/runlist.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/runlist.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/ptimer.h>
#include <nvgpu/bug.h>
#include <nvgpu/dma.h>
@@ -912,3 +913,92 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask)
}
}
}
#if defined(CONFIG_NVGPU_NON_FUSA)
static void nvgpu_runlist_init_engine_info(struct gk20a *g,
struct nvgpu_runlist *runlist,
const struct nvgpu_device *dev)
{
u32 i = 0U;
/*
* runlist_pri_base, chram_bar0_offset and pbdma_info
* will get over-written with same info, if multiple engines
* are present on same runlist. Required optimization will be
* done as part of JIRA NVGPU-4980
*/
runlist->nvgpu_next.runlist_pri_base =
dev->next.rl_pri_base;
runlist->nvgpu_next.chram_bar0_offset =
g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x",
runlist->id, runlist->nvgpu_next.runlist_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x",
runlist->id, runlist->nvgpu_next.chram_bar0_offset);
runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info;
for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
nvgpu_log(g, gpu_dbg_info,
"runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x",
runlist->id, i,
runlist->nvgpu_next.pbdma_info->pbdma_id[i], i,
runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]);
}
runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev;
}
static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
struct nvgpu_runlist *runlist)
{
u32 pbdma_mask = 0U;
u32 i;
u32 pbdma_id;
nvgpu_assert(runlist != NULL);
for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i];
if (pbdma_id != NVGPU_INVALID_PBDMA_ID)
pbdma_mask |= BIT32(pbdma_id);
}
return pbdma_mask;
}
void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
{
struct nvgpu_runlist *runlist;
const struct nvgpu_device *dev;
u32 i, j;
nvgpu_log_fn(g, " ");
if (g->is_virtual) {
return;
}
for (i = 0U; i < f->num_runlists; i++) {
runlist = &f->active_runlists[i];
nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i);
for (j = 0U; j < f->num_engines; j++) {
dev = f->active_engines[j];
if (dev->runlist_id == runlist->id) {
runlist->eng_bitmask |= BIT32(dev->engine_id);
nvgpu_runlist_init_engine_info(g, runlist, dev);
}
}
runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist);
nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask);
nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
}
nvgpu_log_fn(g, "done");
}
#endif

32
drivers/gpu/nvgpu/common/gr/fs_state.c
View File

@@ -194,3 +194,35 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
return err;
}
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 tpc_index, gpc_index;
u32 sm_id = 0;
u32 num_sm;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
err = g->ops.gr.config.init_sm_id_table(g, config);
if (err != 0) {
return err;
}
num_sm = nvgpu_gr_config_get_no_of_sm(config);
nvgpu_assert(num_sm > 0U);
for (sm_id = 0; sm_id < num_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(config, sm_id);
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
config, NULL, false);
}
return err;
}
#endif

60
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -561,8 +561,8 @@ static int gr_init_prepare_hw_impl(struct gk20a *g)
}
#if defined(CONFIG_NVGPU_NON_FUSA)
nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g);
nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g);
nvgpu_gr_init_reset_enable_hw_non_ctx_local(g);
nvgpu_gr_init_reset_enable_hw_non_ctx_global(g);
#endif
nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes");
@@ -1200,3 +1200,59 @@ u32 nvgpu_gr_get_tpc_num(struct gk20a *g, u32 addr)
}
return 0;
}
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr,
sw_non_ctx_local_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr,
sw_non_ctx_local_gfx_load->l[i].value);
}
}
#endif
return;
}
void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr,
sw_non_ctx_global_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr,
sw_non_ctx_global_gfx_load->l[i].value);
}
}
#endif
return;
}
#endif

57
drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c
View File

@@ -1,57 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/nvgpu_next_fs_state.h>
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 tpc_index, gpc_index;
u32 sm_id = 0;
u32 num_sm;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
err = g->ops.gr.config.init_sm_id_table(g, config);
if (err != 0) {
return err;
}
num_sm = nvgpu_gr_config_get_no_of_sm(config);
nvgpu_assert(num_sm > 0U);
for (sm_id = 0; sm_id < num_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(config, sm_id);
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
config, NULL, false);
}
return err;
}

81
drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c
View File

@@ -1,81 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/netlist.h>
#include <nvgpu/io.h>
#include <nvgpu/gr/nvgpu_next_gr.h>
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr,
sw_non_ctx_local_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr,
sw_non_ctx_local_gfx_load->l[i].value);
}
}
#endif
return;
}
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr,
sw_non_ctx_global_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr,
sw_non_ctx_global_gfx_load->l[i].value);
}
}
#endif
return;
}

92
drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c
View File

@@ -1,92 +0,0 @@
/*
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/lock.h>
#include <nvgpu/mc.h>
void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= MC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= MC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_mc_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= MC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_mc_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}

332
drivers/gpu/nvgpu/common/netlist/netlist.c
View File

@@ -31,9 +31,6 @@
#include <nvgpu/netlist.h>
#include <nvgpu/string.h>
#include <nvgpu/static_analysis.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "nvgpu/nvgpu_next_netlist.h"
#endif
#include "netlist_priv.h"
#include "netlist_defs.h"
@@ -1074,4 +1071,333 @@ void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index)
{
g->netlist_vars->regs_base_index = index;
}
#ifdef CONFIG_NVGPU_DEBUGGER
bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch (region_id) {
case NETLIST_REGIONID_CTXREG_SYS_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_compute);
break;
case NETLIST_REGIONID_CTXREG_GPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute);
break;
case NETLIST_REGIONID_CTXREG_TPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute);
break;
case NETLIST_REGIONID_CTXREG_PPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute);
break;
case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute);
break;
case NETLIST_REGIONID_CTXREG_LTS_BC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_bc);
break;
case NETLIST_REGIONID_CTXREG_LTS_UC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_uc);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_CTXREG_SYS_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx);
break;
case NETLIST_REGIONID_CTXREG_GPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_TPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_PPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx);
break;
case NETLIST_REGIONID_CTXREG_ETPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch(region_id) {
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l);
#ifdef CONFIG_NVGPU_GRAPHICS
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx;
}
u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
return count;
}
void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g)
{
nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d",
nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load;
}
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load;
}
#endif /* CONFIG_NVGPU_GRAPHICS */
#endif

55
drivers/gpu/nvgpu/common/netlist/netlist_priv.h
View File

@@ -25,10 +25,6 @@
#include <nvgpu/types.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "common/netlist/nvgpu_next_netlist_priv.h"
#endif
struct netlist_u32_list;
struct netlist_av_list;
struct netlist_av64_list;
@@ -78,10 +74,30 @@ struct netlist_aiv_list;
#define NETLIST_REGIONID_SW_BUNDLE64_INIT 34
#ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_NVPERF_PMCAU 35
#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36
#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38
#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40
#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42
#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_CTXREG_SYS_GFX 37
#define NETLIST_REGIONID_CTXREG_GPC_GFX 39
#define NETLIST_REGIONID_CTXREG_TPC_GFX 41
#define NETLIST_REGIONID_CTXREG_PPC_GFX 43
#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45
#endif /* CONFIG_NVGPU_GRAPHICS */
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51
#endif /* CONFIG_NVGPU_GRAPHICS */
#define NETLIST_REGIONID_NVPERF_SYS_CONTROL 52
#define NETLIST_REGIONID_NVPERF_FBP_CONTROL 53
#define NETLIST_REGIONID_NVPERF_GPC_CONTROL 54
#define NETLIST_REGIONID_NVPERF_PMA_CONTROL 55
#define NETLIST_REGIONID_CTXREG_LTS_BC 57
#define NETLIST_REGIONID_CTXREG_LTS_UC 58
#endif
struct netlist_region {
@@ -107,6 +123,37 @@ struct netlist_gr_ucode {
} gpccs, fecs;
};
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
struct nvgpu_next_netlist_vars {
struct netlist_av_list sw_non_ctx_local_compute_load;
struct netlist_av_list sw_non_ctx_global_compute_load;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list sw_non_ctx_local_gfx_load;
struct netlist_av_list sw_non_ctx_global_gfx_load;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#ifdef CONFIG_NVGPU_DEBUGGER
struct nvgpu_next_ctxsw_regs {
struct netlist_aiv_list sys_compute;
struct netlist_aiv_list gpc_compute;
struct netlist_aiv_list tpc_compute;
struct netlist_aiv_list ppc_compute;
struct netlist_aiv_list etpc_compute;
struct netlist_aiv_list lts_bc;
struct netlist_aiv_list lts_uc;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_aiv_list sys_gfx;
struct netlist_aiv_list gpc_gfx;
struct netlist_aiv_list tpc_gfx;
struct netlist_aiv_list ppc_gfx;
struct netlist_aiv_list etpc_gfx;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
struct nvgpu_netlist_vars {
bool dynamic;

383
drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c
View File

@@ -1,383 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
#include <nvgpu/netlist.h>
#include "common/netlist/netlist_priv.h"
/* Copied from common/netlist/netlist.c */
static int nvgpu_netlist_alloc_load_av_list(struct gk20a *g, u8 *src, u32 len,
struct netlist_av_list *av_list)
{
av_list->count = len / U32(sizeof(struct netlist_av));
if (nvgpu_netlist_alloc_av_list(g, av_list) == NULL) {
return -ENOMEM;
}
nvgpu_memcpy((u8 *)av_list->l, src, len);
return 0;
}
/* Copied from common/netlist/netlist.c */
static int nvgpu_netlist_alloc_load_aiv_list(struct gk20a *g, u8 *src, u32 len,
struct netlist_aiv_list *aiv_list)
{
aiv_list->count = len / U32(sizeof(struct netlist_aiv));
if (nvgpu_netlist_alloc_aiv_list(g, aiv_list) == NULL) {
return -ENOMEM;
}
nvgpu_memcpy((u8 *)aiv_list->l, src, len);
return 0;
}
#ifdef CONFIG_NVGPU_DEBUGGER
bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch (region_id) {
case NETLIST_REGIONID_CTXREG_SYS_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_compute);
break;
case NETLIST_REGIONID_CTXREG_GPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute);
break;
case NETLIST_REGIONID_CTXREG_TPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute);
break;
case NETLIST_REGIONID_CTXREG_PPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute);
break;
case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute);
break;
case NETLIST_REGIONID_CTXREG_LTS_BC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_bc);
break;
case NETLIST_REGIONID_CTXREG_LTS_UC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_uc);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_CTXREG_SYS_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx);
break;
case NETLIST_REGIONID_CTXREG_GPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_TPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_PPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx);
break;
case NETLIST_REGIONID_CTXREG_ETPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch(region_id) {
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l);
#ifdef CONFIG_NVGPU_GRAPHICS
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx;
}
u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
return count;
}
void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g)
{
nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d",
nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load;
}
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load;
}
#endif /* CONFIG_NVGPU_GRAPHICS */

92
drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h
View File

@@ -1,92 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_NETLIST_PRIV_H
#define NVGPU_NEXT_NETLIST_PRIV_H
/**
* @file
*
* Declare netlist_vars specific struct and defines.
*/
#include <nvgpu/types.h>
struct gk20a;
struct netlist_av_list;
struct netlist_aiv_list;
#ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36
#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38
#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40
#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42
#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_CTXREG_SYS_GFX 37
#define NETLIST_REGIONID_CTXREG_GPC_GFX 39
#define NETLIST_REGIONID_CTXREG_TPC_GFX 41
#define NETLIST_REGIONID_CTXREG_PPC_GFX 43
#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45
#endif /* CONFIG_NVGPU_GRAPHICS */
#endif /* CONFIG_NVGPU_DEBUGGER */
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51
#endif /* CONFIG_NVGPU_GRAPHICS */
#ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_CTXREG_LTS_BC 57
#define NETLIST_REGIONID_CTXREG_LTS_UC 58
#endif /* CONFIG_DEBUGGER */
struct nvgpu_next_netlist_vars {
struct netlist_av_list sw_non_ctx_local_compute_load;
struct netlist_av_list sw_non_ctx_global_compute_load;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list sw_non_ctx_local_gfx_load;
struct netlist_av_list sw_non_ctx_global_gfx_load;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#ifdef CONFIG_NVGPU_DEBUGGER
struct nvgpu_next_ctxsw_regs {
struct netlist_aiv_list sys_compute;
struct netlist_aiv_list gpc_compute;
struct netlist_aiv_list tpc_compute;
struct netlist_aiv_list ppc_compute;
struct netlist_aiv_list etpc_compute;
struct netlist_aiv_list lts_bc;
struct netlist_aiv_list lts_uc;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_aiv_list sys_gfx;
struct netlist_aiv_list gpc_gfx;
struct netlist_aiv_list tpc_gfx;
struct netlist_aiv_list ppc_gfx;
struct netlist_aiv_list etpc_gfx;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* NVGPU_NEXT_NETLIST_PRIV_H */

38
drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c
View File

@@ -1,38 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include "nvgpu_next_profiler.h"
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g)
{
if (g->ops.perf.reset_hs_streaming_credits != NULL) {
/* Reset high speed streaming credits to 0. */
g->ops.perf.reset_hs_streaming_credits(g);
}
if (g->ops.perf.enable_hs_streaming != NULL) {
/* Disable high speed streaming */
g->ops.perf.enable_hs_streaming(g, false);
}
}

28
drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_PROFILER_H
#define NVGPU_NEXT_PROFILER_H
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g);
#endif /* NVGPU_NEXT_PROFILER_H */

15
drivers/gpu/nvgpu/common/profiler/profiler.c
View File

@@ -1157,3 +1157,18 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof
offset = offset & (stride - 1U);
return allowlist_offset_search(g, offset_allowlist, count, offset);
}
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g)
{
if (g->ops.perf.reset_hs_streaming_credits != NULL) {
/* Reset high speed streaming credits to 0. */
g->ops.perf.reset_hs_streaming_credits(g);
}
if (g->ops.perf.enable_hs_streaming != NULL) {
/* Disable high speed streaming */
g->ops.perf.enable_hs_streaming(g, false);
}
}
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */

61
drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c
View File

@@ -1,61 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/utils.h>
#include <nvgpu/hw_sim.h>
#include <nvgpu/sim.h>
#include <nvgpu/string.h>
static void nvgpu_next_sim_esc_readl(struct gk20a *g,
const char *path, u32 index, u32 *data)
{
int err;
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(
nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
err = issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
nvgpu_safe_add_u32(data_offset,
sim_escape_read_hdr_size())),
sizeof(u32));
} else {
*data = 0xffffffff;
WARN(1, "issue_rpc_and_wait failed err=%d", err);
}
}
void nvgpu_next_init_sim_support(struct gk20a *g)
{
if (g->sim) {
g->sim->esc_readl = nvgpu_next_sim_esc_readl;
}
}

445
drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c
View File

@@ -1,445 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/sim.h>
#include <nvgpu/netlist.h>
#include "nvgpu/nvgpu_next_sim.h"
int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g)
{
u32 i;
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_local_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_compute_load failed");
}
for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_local_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_global_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_compute_load failed");
}
for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_global_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
return 0;
}
void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g)
{
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_compute_load->l);
nvgpu_kfree(g, sw_non_ctx_global_compute_load->l);
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l);
nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g)
{
u32 i;
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0,
&sys_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_compute_ctxsw_regs failed");
}
for (i = 0; i < sys_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE",
i, &l[i].value);
}
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0,
&gpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_compute_ctxsw_regs failed");
}
for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE",
i, &l[i].value);
}
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0,
&tpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_compute_ctxsw_regs failed");
}
for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE",
i, &l[i].value);
}
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0,
&ppc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_compute_ctxsw_regs failed");
}
for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE",
i, &l[i].value);
}
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0,
&etpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_compute_ctxsw_regs failed");
}
for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE",
i, &l[i].value);
}
/*
* TODO: https://jirasw.nvidia.com/browse/NVGPU-5761
*/
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0,
&lts_ctxsw_regs->count);
nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) {
nvgpu_info(g, "lts_ctxsw_regs failed");
}
for (i = 0U; i < lts_ctxsw_regs->count; i++) {
struct netlist_aiv *l = lts_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE",
i, &l[i].value);
nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr,
l[i].index, l[i].value);
}
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0,
&sys_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_gfx_ctxsw_regs failed");
}
for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE",
i, &l[i].value);
}
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0,
&gpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE",
i, &l[i].value);
}
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0,
&tpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE",
i, &l[i].value);
}
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0,
&ppc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_gfx_ctxsw_regs failed");
}
for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE",
i, &l[i].value);
}
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0,
&etpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE",
i, &l[i].value);
}
return 0;
}
void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g)
{
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
nvgpu_kfree(g, sys_compute_ctxsw_regs->l);
nvgpu_kfree(g, gpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, tpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, ppc_compute_ctxsw_regs->l);
nvgpu_kfree(g, etpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, lts_ctxsw_regs->l);
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
nvgpu_kfree(g, sys_gfx_ctxsw_regs->l);
nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */

37
drivers/gpu/nvgpu/common/sim/sim.c
View File

@@ -301,3 +301,40 @@ int nvgpu_init_sim_support(struct gk20a *g)
g->sim->esc_readl = nvgpu_sim_esc_readl;
return 0;
}
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
static void nvgpu_next_sim_esc_readl(struct gk20a *g,
const char *path, u32 index, u32 *data)
{
int err;
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(
nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
err = issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
nvgpu_safe_add_u32(data_offset,
sim_escape_read_hdr_size())),
sizeof(u32));
} else {
*data = 0xffffffff;
WARN(1, "issue_rpc_and_wait failed err=%d", err);
}
}
void nvgpu_next_init_sim_support(struct gk20a *g)
{
if (g->sim) {
g->sim->esc_readl = nvgpu_next_sim_esc_readl;
}
}
#endif

424
drivers/gpu/nvgpu/common/sim/sim_netlist.c
View File

@@ -24,9 +24,6 @@
#include <nvgpu/sim.h>
#include <nvgpu/netlist.h>
#include <nvgpu/log.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "nvgpu/nvgpu_next_sim.h"
#endif
int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
{
@@ -818,3 +815,424 @@ fail:
return err;
}
#if defined(CONFIG_NVGPU_NON_FUSA)
int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g)
{
u32 i;
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_local_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_compute_load failed");
}
for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_local_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_global_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_compute_load failed");
}
for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_global_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
return 0;
}
void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g)
{
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_compute_load->l);
nvgpu_kfree(g, sw_non_ctx_global_compute_load->l);
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l);
nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g)
{
u32 i;
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0,
&sys_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_compute_ctxsw_regs failed");
}
for (i = 0; i < sys_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE",
i, &l[i].value);
}
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0,
&gpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_compute_ctxsw_regs failed");
}
for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE",
i, &l[i].value);
}
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0,
&tpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_compute_ctxsw_regs failed");
}
for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE",
i, &l[i].value);
}
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0,
&ppc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_compute_ctxsw_regs failed");
}
for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE",
i, &l[i].value);
}
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0,
&etpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_compute_ctxsw_regs failed");
}
for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE",
i, &l[i].value);
}
/*
* TODO: https://jirasw.nvidia.com/browse/NVGPU-5761
*/
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0,
&lts_ctxsw_regs->count);
nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) {
nvgpu_info(g, "lts_ctxsw_regs failed");
}
for (i = 0U; i < lts_ctxsw_regs->count; i++) {
struct netlist_aiv *l = lts_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE",
i, &l[i].value);
nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr,
l[i].index, l[i].value);
}
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0,
&sys_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_gfx_ctxsw_regs failed");
}
for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE",
i, &l[i].value);
}
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0,
&gpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE",
i, &l[i].value);
}
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0,
&tpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE",
i, &l[i].value);
}
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0,
&ppc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_gfx_ctxsw_regs failed");
}
for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE",
i, &l[i].value);
}
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0,
&etpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE",
i, &l[i].value);
}
return 0;
}
void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g)
{
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
nvgpu_kfree(g, sys_compute_ctxsw_regs->l);
nvgpu_kfree(g, gpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, tpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, ppc_compute_ctxsw_regs->l);
nvgpu_kfree(g, etpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, lts_ctxsw_regs->l);
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
nvgpu_kfree(g, sys_gfx_ctxsw_regs->l);
nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif