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gpu: nvgpu: remove nvgpu_next files

Browse Source 
Remove all nvgpu_next files and move the code into corresponding
nvgpu files.

Merge nvgpu-next-*.yaml into nvgpu-.yaml files.

Jira NVGPU-4771

Change-Id: I595311be3c7bbb4f6314811e68712ff01763801e
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547557
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2021-06-19 10:17:51 +00:00
committed by mobile promotions
parent c7d43f5292
commit f9cac0c64d
126 changed files with 2351 additions and 4554 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
arch/nvgpu-common.yaml
View File

@@ -26,12 +26,15 @@ bios:
common/vbios/bios_sw_gv100.h, common/vbios/bios_sw_gv100.h,
common/vbios/bios_sw_tu104.c, common/vbios/bios_sw_tu104.c,
common/vbios/bios_sw_tu104.h, common/vbios/bios_sw_tu104.h,
common/vbios/bios_sw_ga100.c,
common/vbios/bios_sw_ga100.h,
common/vbios/nvlink_bios.c, common/vbios/nvlink_bios.c,
include/nvgpu/bios.h, include/nvgpu/bios.h,
include/nvgpu/nvlink_bios.h, include/nvgpu/nvlink_bios.h,
include/nvgpu/gops/bios.h, include/nvgpu/gops/bios.h,
include/nvgpu/gops/xve.h ] include/nvgpu/gops/xve.h ]
ce: ce:
safe: yes safe: yes
owner: Thomas F owner: Thomas F
@@ -269,7 +272,9 @@ acr_fusa:
common/acr/acr_sw_gv11b.h, common/acr/acr_sw_gv11b.h,
common/acr/nvgpu_acr_interface.h, common/acr/nvgpu_acr_interface.h,
include/nvgpu/gops/acr.h, include/nvgpu/gops/acr.h,
include/nvgpu/acr.h ] include/nvgpu/acr.h,
include/nvgpu/riscv.h,
common/riscv/riscv.c ]
acr: acr:
safe: no safe: no
@@ -281,7 +286,11 @@ acr:
common/acr/acr_sw_gm20b.c, common/acr/acr_sw_gm20b.c,
common/acr/acr_sw_gm20b.h, common/acr/acr_sw_gm20b.h,
common/acr/acr_sw_tu104.c, common/acr/acr_sw_tu104.c,
common/acr/acr_sw_tu104.h ] common/acr/acr_sw_tu104.h,
common/acr/acr_sw_ga10b.c,
common/acr/acr_sw_ga10b.h,
common/acr/acr_sw_ga100.c,
common/acr/acr_sw_ga100.h ]
sbr: sbr:
safe: yes safe: yes
@@ -348,6 +357,8 @@ falcon:
gpu: dgpu gpu: dgpu
sources: [ common/falcon/falcon_sw_tu104.c, sources: [ common/falcon/falcon_sw_tu104.c,
common/falcon/falcon_sw_tu104.h, common/falcon/falcon_sw_tu104.h,
common/falcon/falcon_sw_ga10b.c,
common/falcon/falcon_sw_ga10b.h,
include/nvgpu/gops/gsp.h, include/nvgpu/gops/gsp.h,
include/nvgpu/gops/nvdec.h ] include/nvgpu/gops/nvdec.h ]
deps: [ ] deps: [ ]
@@ -834,6 +845,8 @@ pmu:
common/pmu/perfmon/pmu_perfmon_sw_gm20b.h, common/pmu/perfmon/pmu_perfmon_sw_gm20b.h,
common/pmu/perfmon/pmu_perfmon_sw_gv11b.c, common/pmu/perfmon/pmu_perfmon_sw_gv11b.c,
common/pmu/perfmon/pmu_perfmon_sw_gv11b.h, common/pmu/perfmon/pmu_perfmon_sw_gv11b.h,
common/pmu/perfmon/pmu_perfmon_sw_ga10b.c,
common/pmu/perfmon/pmu_perfmon_sw_ga10b.h,
include/nvgpu/pmu/pmu_perfmon.h ] include/nvgpu/pmu/pmu_perfmon.h ]
clk: clk:
@@ -900,6 +913,8 @@ pmu:
common/pmu/pg/pg_sw_gp10b.h, common/pmu/pg/pg_sw_gp10b.h,
common/pmu/pg/pg_sw_gv11b.c, common/pmu/pg/pg_sw_gv11b.c,
common/pmu/pg/pg_sw_gv11b.h, common/pmu/pg/pg_sw_gv11b.h,
common/pmu/pg/pg_sw_ga10b.c,
common/pmu/pg/pg_sw_ga10b.h,
common/pmu/pg/pmu_aelpg.c, common/pmu/pg/pmu_aelpg.c,
common/pmu/pg/pmu_pg.c, common/pmu/pg/pmu_pg.c,
common/pmu/pg/pmu_pg.h, common/pmu/pg/pmu_pg.h,

73
arch/nvgpu-gpu_hw.yaml
View File

@@ -1,4 +1,4 @@
# Copyright (c) 2019, NVIDIA CORPORATION. All Rights Reserved. # Copyright (c) 2019-2021, NVIDIA CORPORATION. All Rights Reserved.
# #
# Define meta elements and units for describing GPU HW interactions in # Define meta elements and units for describing GPU HW interactions in
# nvgpu. # nvgpu.
@@ -221,4 +221,73 @@ headers:
include/nvgpu/hw/tu104/hw_trim_tu104.h, include/nvgpu/hw/tu104/hw_trim_tu104.h,
include/nvgpu/hw/tu104/hw_usermode_tu104.h, include/nvgpu/hw/tu104/hw_usermode_tu104.h,
include/nvgpu/hw/tu104/hw_xp_tu104.h, include/nvgpu/hw/tu104/hw_xp_tu104.h,
include/nvgpu/hw/tu104/hw_xve_tu104.h ] include/nvgpu/hw/tu104/hw_xve_tu104.h,
include/nvgpu/hw/ga100/hw_bus_ga100.h,
include/nvgpu/hw/ga100/hw_ce_ga100.h,
include/nvgpu/hw/ga100/hw_ctrl_ga100.h,
include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h,
include/nvgpu/hw/ga100/hw_falcon_ga100.h,
include/nvgpu/hw/ga100/hw_fb_ga100.h,
include/nvgpu/hw/ga100/hw_flush_ga100.h,
include/nvgpu/hw/ga100/hw_func_ga100.h,
include/nvgpu/hw/ga100/hw_fuse_ga100.h,
include/nvgpu/hw/ga100/hw_gc6_ga100.h,
include/nvgpu/hw/ga100/hw_gmmu_ga100.h,
include/nvgpu/hw/ga100/hw_gr_ga100.h,
include/nvgpu/hw/ga100/hw_ltc_ga100.h,
include/nvgpu/hw/ga100/hw_mc_ga100.h,
include/nvgpu/hw/ga100/hw_pbdma_ga100.h,
include/nvgpu/hw/ga100/hw_perf_ga100.h,
include/nvgpu/hw/ga100/hw_pgsp_ga100.h,
include/nvgpu/hw/ga100/hw_pram_ga100.h,
include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h,
include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h,
include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h,
include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h,
include/nvgpu/hw/ga100/hw_pri_sys_ga100.h,
include/nvgpu/hw/ga100/hw_proj_ga100.h,
include/nvgpu/hw/ga100/hw_psec_ga100.h,
include/nvgpu/hw/ga100/hw_pwr_ga100.h,
include/nvgpu/hw/ga100/hw_ram_ga100.h,
include/nvgpu/hw/ga100/hw_runlist_ga100.h,
include/nvgpu/hw/ga100/hw_smcarb_ga100.h,
include/nvgpu/hw/ga100/hw_timer_ga100.h,
include/nvgpu/hw/ga100/hw_top_ga100.h,
include/nvgpu/hw/ga100/hw_pnvdec_ga100.h,
include/nvgpu/hw/ga100/hw_therm_ga100.h,
include/nvgpu/hw/ga100/hw_trim_ga100.h,
include/nvgpu/hw/ga100/hw_xp_ga100.h,
include/nvgpu/hw/ga100/hw_xve_ga100.h,
include/nvgpu/hw/ga100/hw_fbpa_ga100.h,
include/nvgpu/hw/ga10b/hw_bus_ga10b.h,
include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ce_ga10b.h,
include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h,
include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h,
include/nvgpu/hw/ga10b/hw_falcon_ga10b.h,
include/nvgpu/hw/ga10b/hw_fb_ga10b.h,
include/nvgpu/hw/ga10b/hw_flush_ga10b.h,
include/nvgpu/hw/ga10b/hw_func_ga10b.h,
include/nvgpu/hw/ga10b/hw_fuse_ga10b.h,
include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h,
include/nvgpu/hw/ga10b/hw_gr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ltc_ga10b.h,
include/nvgpu/hw/ga10b/hw_mc_ga10b.h,
include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h,
include/nvgpu/hw/ga10b/hw_perf_ga10b.h,
include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h,
include/nvgpu/hw/ga10b/hw_pram_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h,
include/nvgpu/hw/ga10b/hw_proj_ga10b.h,
include/nvgpu/hw/ga10b/hw_priscv_ga10b.h,
include/nvgpu/hw/ga10b/hw_pwr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ram_ga10b.h,
include/nvgpu/hw/ga10b/hw_runlist_ga10b.h,
include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h,
include/nvgpu/hw/ga10b/hw_therm_ga10b.h,
include/nvgpu/hw/ga10b/hw_timer_ga10b.h,
include/nvgpu/hw/ga10b/hw_top_ga10b.h ]

319
arch/nvgpu-hal-new.yaml
View File

@@ -18,7 +18,11 @@ bus:
owner: Terje B owner: Terje B
sources: [ hal/bus/bus_gk20a.c, sources: [ hal/bus/bus_gk20a.c,
hal/bus/bus_gv100.c, hal/bus/bus_gv100.h, hal/bus/bus_gv100.c, hal/bus/bus_gv100.h,
hal/bus/bus_tu104.c, hal/bus/bus_tu104.h ] hal/bus/bus_tu104.c, hal/bus/bus_tu104.h,
hal/bus/bus_ga10b.c,
hal/bus/bus_ga10b.h,
hal/bus/bus_ga100.c,
hal/bus/bus_ga100.h ]
ltc: ltc:
owner: Seshendra G owner: Seshendra G
@@ -30,14 +34,19 @@ ltc:
hal/ltc/ltc_gp10b_fusa.c, hal/ltc/ltc_gp10b_fusa.c,
hal/ltc/ltc_gp10b.h, hal/ltc/ltc_gp10b.h,
hal/ltc/ltc_gv11b_fusa.c, hal/ltc/ltc_gv11b_fusa.c,
hal/ltc/ltc_gv11b.h ] hal/ltc/ltc_gv11b.h,
hal/ltc/ltc_ga10b.h,
hal/ltc/ltc_ga10b_fusa.c ]
ltc: ltc:
safe: no safe: no
sources: [ hal/ltc/ltc_gm20b.c, sources: [ hal/ltc/ltc_gm20b.c,
hal/ltc/ltc_gm20b_dbg.c, hal/ltc/ltc_gm20b_dbg.c,
hal/ltc/ltc_gp10b.c, hal/ltc/ltc_gp10b.c,
hal/ltc/ltc_tu104.c, hal/ltc/ltc_tu104.c,
hal/ltc/ltc_tu104.h ] hal/ltc/ltc_tu104.h,
hal/ltc/ltc_ga10b.c ]
intr_fusa: intr_fusa:
safe: yes safe: yes
sources: [ hal/ltc/intr/ltc_intr_gp10b_fusa.c, sources: [ hal/ltc/intr/ltc_intr_gp10b_fusa.c,
@@ -48,7 +57,9 @@ ltc:
safe: no safe: no
sources: [ hal/ltc/intr/ltc_intr_gm20b.c, sources: [ hal/ltc/intr/ltc_intr_gm20b.c,
hal/ltc/intr/ltc_intr_gm20b.h, hal/ltc/intr/ltc_intr_gm20b.h,
hal/ltc/intr/ltc_intr_gp10b.c ] hal/ltc/intr/ltc_intr_gp10b.c,
hal/ltc/intr/ltc_intr_ga10b.h,
hal/ltc/intr/ltc_intr_ga10b_fusa.c ]
init_fusa: init_fusa:
safe: yes safe: yes
@@ -68,6 +79,14 @@ init:
hal/init/hal_gp10b.h, hal/init/hal_gp10b.h,
hal/init/hal_tu104.c, hal/init/hal_tu104.c,
hal/init/hal_tu104.h, hal/init/hal_tu104.h,
hal/init/hal_ga100.c,
hal/init/hal_ga100.h,
hal/init/hal_ga10b.c,
hal/init/hal_ga10b.h,
hal/init/hal_ga100_litter.c,
hal/init/hal_ga100_litter.h,
hal/init/hal_ga10b_litter.c,
hal/init/hal_ga10b_litter.h,
hal/init/hal_gm20b_litter.c, hal/init/hal_gm20b_litter.c,
hal/init/hal_gm20b_litter.h, hal/init/hal_gm20b_litter.h,
hal/init/hal_gp10b_litter.c, hal/init/hal_gp10b_litter.c,
@@ -82,7 +101,11 @@ priv_ring_fusa:
hal/priv_ring/priv_ring_gm20b_fusa.c, hal/priv_ring/priv_ring_gm20b_fusa.c,
hal/priv_ring/priv_ring_gm20b.h, hal/priv_ring/priv_ring_gm20b.h,
hal/priv_ring/priv_ring_gp10b_fusa.c, hal/priv_ring/priv_ring_gp10b_fusa.c,
hal/priv_ring/priv_ring_gp10b.h ] hal/priv_ring/priv_ring_gp10b.h,
hal/priv_ring/priv_ring_ga10b_fusa.c,
hal/priv_ring/priv_ring_ga10b.h,
hal/priv_ring/priv_ring_ga100_fusa.c,
hal/priv_ring/priv_ring_ga100.h ]
priv_ring: priv_ring:
safe: no safe: no
@@ -95,7 +118,9 @@ ptimer_fusa:
safe: yes safe: yes
owner: Terje B owner: Terje B
sources: [ hal/ptimer/ptimer_gk20a_fusa.c, sources: [ hal/ptimer/ptimer_gk20a_fusa.c,
hal/ptimer/ptimer_gk20a.h ] hal/ptimer/ptimer_gk20a.h,
hal/ptimer/ptimer_ga10b_fusa.c,
hal/ptimer/ptimer_ga10b.h ]
ptimer: ptimer:
safe: no safe: no
@@ -120,7 +145,11 @@ cg:
hal/power_features/cg/gp10b_gating_reglist.c, hal/power_features/cg/gp10b_gating_reglist.c,
hal/power_features/cg/gp10b_gating_reglist.h, hal/power_features/cg/gp10b_gating_reglist.h,
hal/power_features/cg/tu104_gating_reglist.c, hal/power_features/cg/tu104_gating_reglist.c,
hal/power_features/cg/tu104_gating_reglist.h ] hal/power_features/cg/tu104_gating_reglist.h,
hal/power_features/cg/ga10b_gating_reglist.c,
hal/power_features/cg/ga10b_gating_reglist.h,
hal/power_features/cg/ga100_gating_reglist.c,
hal/power_features/cg/ga100_gating_reglist.h ]
rc: rc:
safe: no safe: no
@@ -141,7 +170,9 @@ clk:
owner: Ramesh M owner: Ramesh M
gpu: dgpu gpu: dgpu
sources: [ hal/clk/clk_tu104.c, sources: [ hal/clk/clk_tu104.c,
hal/clk/clk_tu104.h ] hal/clk/clk_tu104.h,
hal/clk/clk_ga100.c,
hal/clk/clk_ga100.h ]
clk_mon: clk_mon:
safe: yes safe: yes
@@ -168,14 +199,19 @@ fifo:
sources: [ hal/fifo/userd_gk20a.c, sources: [ hal/fifo/userd_gk20a.c,
hal/fifo/userd_gk20a.h, hal/fifo/userd_gk20a.h,
hal/fifo/userd_gv11b.c, hal/fifo/userd_gv11b.c,
hal/fifo/userd_gv11b.h ] hal/fifo/userd_gv11b.h,
hal/fifo/userd_ga10b.c,
hal/fifo/userd_ga10b.h ]
ramfc_fusa: ramfc_fusa:
safe: yes safe: yes
sources: [ hal/fifo/ramin_gk20a_fusa.c, sources: [ hal/fifo/ramin_gk20a_fusa.c,
hal/fifo/ramfc_gp10b_fusa.c, hal/fifo/ramfc_gp10b_fusa.c,
hal/fifo/ramfc_gp10b.h, hal/fifo/ramfc_gp10b.h,
hal/fifo/ramfc_gv11b_fusa.c, hal/fifo/ramfc_gv11b_fusa.c,
hal/fifo/ramfc_gv11b.h ] hal/fifo/ramfc_gv11b.h,
hal/fifo/ramfc_ga10b_fusa.c,
hal/fifo/ramfc_ga10b.h ]
ramfc: ramfc:
safe: no safe: no
@@ -190,7 +226,9 @@ fifo:
sources: [ hal/fifo/ramin_gv11b.h, sources: [ hal/fifo/ramin_gv11b.h,
hal/fifo/ramin_gm20b.h, hal/fifo/ramin_gm20b.h,
hal/fifo/ramin_gv11b_fusa.c, hal/fifo/ramin_gv11b_fusa.c,
hal/fifo/ramin_gm20b_fusa.c ] hal/fifo/ramin_gm20b_fusa.c,
hal/fifo/ramin_ga10b_fusa.c,
hal/fifo/ramin_ga10b.h ]
ramin: ramin:
safe: no safe: no
@@ -210,7 +248,12 @@ fifo:
hal/fifo/runlist_fifo_gv11b_fusa.c, hal/fifo/runlist_fifo_gv11b_fusa.c,
hal/fifo/runlist_fifo_gv11b.h, hal/fifo/runlist_fifo_gv11b.h,
hal/fifo/runlist_ram_gv11b_fusa.c, hal/fifo/runlist_ram_gv11b_fusa.c,
hal/fifo/runlist_ram_gv11b.h ] hal/fifo/runlist_ram_gv11b.h,
hal/fifo/runlist_fifo_ga10b.h,
hal/fifo/runlist_fifo_ga10b.c,
hal/fifo/runlist_fifo_ga10b_fusa.c,
hal/fifo/runlist_fifo_ga100.h,
hal/fifo/runlist_fifo_ga100_fusa.c ]
runlist: runlist:
safe: no safe: no
@@ -221,7 +264,9 @@ fifo:
hal/fifo/runlist_ram_gk20a.c, hal/fifo/runlist_ram_gk20a.c,
hal/fifo/runlist_ram_gk20a.h, hal/fifo/runlist_ram_gk20a.h,
hal/fifo/runlist_ram_tu104.c, hal/fifo/runlist_ram_tu104.c,
hal/fifo/runlist_ram_tu104.h ] hal/fifo/runlist_ram_tu104.h,
hal/fifo/runlist_ga10b.h,
hal/fifo/runlist_ga10b_fusa.c ]
channel_fusa: channel_fusa:
safe: yes safe: yes
@@ -230,7 +275,12 @@ fifo:
hal/fifo/channel_gm20b_fusa.c, hal/fifo/channel_gm20b_fusa.c,
hal/fifo/channel_gm20b.h, hal/fifo/channel_gm20b.h,
hal/fifo/channel_gv11b_fusa.c, hal/fifo/channel_gv11b_fusa.c,
hal/fifo/channel_gv11b.h ] hal/fifo/channel_gv11b.h,
hal/fifo/channel_ga10b_fusa.c,
hal/fifo/channel_ga10b.h,
hal/fifo/channel_ga100_fusa.c,
hal/fifo/channel_ga100.h ]
channel: channel:
safe: no safe: no
sources: [ hal/fifo/channel_gk20a.c, sources: [ hal/fifo/channel_gk20a.c,
@@ -246,7 +296,9 @@ fifo:
tsg: tsg:
safe: no safe: no
sources: [ hal/fifo/tsg_gk20a.c ] sources: [ hal/fifo/tsg_gk20a.c,
hal/fifo/tsg_ga10b.h,
hal/fifo/tsg_ga10b.c ]
fifo_fusa: fifo_fusa:
safe: yes safe: yes
@@ -259,7 +311,14 @@ fifo:
hal/fifo/fifo_gk20a_fusa.c, hal/fifo/fifo_gk20a_fusa.c,
hal/fifo/fifo_gk20a.h, hal/fifo/fifo_gk20a.h,
hal/fifo/fifo_gv11b_fusa.c, hal/fifo/fifo_gv11b_fusa.c,
hal/fifo/fifo_gv11b.h ] hal/fifo/fifo_gv11b.h,
hal/fifo/fifo_ga10b_fusa.c,
hal/fifo/fifo_intr_ga10b_fusa.c,
hal/fifo/ctxsw_timeout_ga10b_fusa.c,
hal/fifo/ctxsw_timeout_ga10b.h,
hal/fifo/fifo_intr_ga10b.h,
hal/fifo/fifo_ga10b.h ]
fifo: fifo:
safe: no safe: no
sources: [ hal/fifo/fifo_intr_gk20a.c, sources: [ hal/fifo/fifo_intr_gk20a.c,
@@ -282,7 +341,10 @@ fifo:
sources: [ hal/fifo/engine_status_gm20b_fusa.c, sources: [ hal/fifo/engine_status_gm20b_fusa.c,
hal/fifo/engine_status_gm20b.h, hal/fifo/engine_status_gm20b.h,
hal/fifo/engine_status_gv100_fusa.c, hal/fifo/engine_status_gv100_fusa.c,
hal/fifo/engine_status_gv100.h ] hal/fifo/engine_status_gv100.h,
hal/fifo/engine_status_ga10b_fusa.c,
hal/fifo/engine_status_ga10b.h ]
engine_status: engine_status:
safe: no safe: no
sources: [ hal/fifo/engine_status_gm20b.c ] sources: [ hal/fifo/engine_status_gm20b.c ]
@@ -299,10 +361,19 @@ fifo:
sources: [ hal/fifo/engines_gm20b.c, sources: [ hal/fifo/engines_gm20b.c,
hal/fifo/engines_gm20b.h ] hal/fifo/engines_gm20b.h ]
pbdma_status_fusa:
safe: no
sources: [ hal/fifo/pbdma_status_ga10b_fusa.c,
hal/fifo/pbdma_status_ga10b.h ]
pbdma_status: pbdma_status:
safe: yes safe: yes
sources: [ hal/fifo/pbdma_status_gm20b_fusa.c, sources: [ hal/fifo/pbdma_status_gm20b_fusa.c,
hal/fifo/pbdma_status_gm20b.h ] hal/fifo/pbdma_status_gm20b.h,
hal/fifo/pbdma_ga10b_fusa.c,
hal/fifo/pbdma_ga10b.h,
hal/fifo/pbdma_ga100_fusa.c,
hal/fifo/pbdma_ga100.h ]
pbdma_fusa: pbdma_fusa:
safe: yes safe: yes
@@ -318,12 +389,15 @@ fifo:
sources: [ hal/fifo/pbdma_gm20b.c, sources: [ hal/fifo/pbdma_gm20b.c,
hal/fifo/pbdma_gp10b.c, hal/fifo/pbdma_gp10b.c,
hal/fifo/pbdma_tu104.c, hal/fifo/pbdma_tu104.c,
hal/fifo/pbdma_tu104.h ] hal/fifo/pbdma_tu104.h,
hal/fifo/pbdma_ga10b.c ]
preempt_fusa: preempt_fusa:
safe: yes safe: yes
sources: [ hal/fifo/preempt_gv11b_fusa.c, sources: [ hal/fifo/preempt_gv11b_fusa.c,
hal/fifo/preempt_gv11b.h ] hal/fifo/preempt_gv11b.h,
hal/fifo/preempt_ga10b_fusa.c,
hal/fifo/preempt_ga10b.h ]
preempt: preempt:
safe: no safe: no
@@ -333,13 +407,21 @@ fifo:
usermode_fusa: usermode_fusa:
safe: yes safe: yes
sources: [ hal/fifo/usermode_gv11b_fusa.c, sources: [ hal/fifo/usermode_gv11b_fusa.c,
hal/fifo/usermode_gv11b.h ] hal/fifo/usermode_gv11b.h,
hal/fifo/usermode_ga10b_fusa.c,
hal/fifo/usermode_ga10b.h ]
usermode: usermode:
safe: no safe: no
sources: [ hal/fifo/usermode_tu104.c, sources: [ hal/fifo/usermode_tu104.c,
hal/fifo/usermode_tu104.h ] hal/fifo/usermode_tu104.h ]
utils_fusa:
safe: no
sources: [ hal/fifo/fifo_utils_ga10b_fusa.c,
hal/fifo/fifo_utils_ga10b.h ]
fuse_fusa: fuse_fusa:
safe: yes safe: yes
owner: Seema K owner: Seema K
@@ -355,12 +437,18 @@ fuse:
hal/fuse/fuse_gp106.c, hal/fuse/fuse_gp106.c,
hal/fuse/fuse_gp106.h, hal/fuse/fuse_gp106.h,
hal/fuse/fuse_tu104.c, hal/fuse/fuse_tu104.c,
hal/fuse/fuse_tu104.h ] hal/fuse/fuse_tu104.h,
hal/fuse/fuse_ga10b.h,
hal/fuse/fuse_ga100.h,
hal/fuse/fuse_ga10b.c,
hal/fuse/fuse_ga100.c ]
gsp: gsp:
safe: no safe: no
sources: [ hal/gsp/gsp_tu104.c, sources: [ hal/gsp/gsp_tu104.c,
hal/gsp/gsp_tu104.h ] hal/gsp/gsp_tu104.h,
hal/gsp/gsp_ga10b.h,
hal/gsp/gsp_ga10b.c ]
mm: mm:
safe: yes safe: yes
@@ -375,7 +463,10 @@ mm:
hal/mm/gmmu/gmmu_gp10b_fusa.c, hal/mm/gmmu/gmmu_gp10b_fusa.c,
hal/mm/gmmu/gmmu_gp10b.h, hal/mm/gmmu/gmmu_gp10b.h,
hal/mm/gmmu/gmmu_gv11b_fusa.c, hal/mm/gmmu/gmmu_gv11b_fusa.c,
hal/mm/gmmu/gmmu_gv11b.h ] hal/mm/gmmu/gmmu_gv11b.h,
hal/mm/gmmu/gmmu_ga10b_fusa.c,
hal/mm/gmmu/gmmu_ga10b.h ]
gmmu: gmmu:
safe: no safe: no
sources: [ hal/mm/gmmu/gmmu_gk20a.c, sources: [ hal/mm/gmmu/gmmu_gk20a.c,
@@ -389,10 +480,14 @@ mm:
cache: cache:
safe: no safe: no
sources: [ hal/mm/cache/flush_gk20a.c ] sources: [ hal/mm/cache/flush_gk20a.c ]
mmu_fault: mmu_fault:
safe: yes safe: yes
sources: [ hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c, sources: [ hal/mm/mmu_fault/mmu_fault_gv11b_fusa.c,
hal/mm/mmu_fault/mmu_fault_gv11b.h ] hal/mm/mmu_fault/mmu_fault_gv11b.h,
hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c,
hal/mm/mmu_fault/mmu_fault_ga10b.h ]
mm_fusa: mm_fusa:
safe: yes safe: yes
sources: [ hal/mm/mm_gp10b_fusa.c, sources: [ hal/mm/mm_gp10b_fusa.c,
@@ -435,7 +530,9 @@ therm_fusa:
safe: yes safe: yes
owner: Seshendra G owner: Seshendra G
sources: [ hal/therm/therm_gv11b_fusa.c, sources: [ hal/therm/therm_gv11b_fusa.c,
hal/therm/therm_gv11b.h ] hal/therm/therm_gv11b.h,
hal/therm/therm_ga10b_fusa.c,
hal/therm/therm_ga10b.h ]
therm: therm:
safe: no safe: no
@@ -457,7 +554,11 @@ cbc:
hal/cbc/cbc_gv11b.c, hal/cbc/cbc_gv11b.c,
hal/cbc/cbc_gv11b.h, hal/cbc/cbc_gv11b.h,
hal/cbc/cbc_tu104.c, hal/cbc/cbc_tu104.c,
hal/cbc/cbc_tu104.h ] hal/cbc/cbc_tu104.h,
hal/cbc/cbc_ga10b.c,
hal/cbc/cbc_ga10b.h,
hal/cbc/cbc_ga100.c,
hal/cbc/cbc_ga100.h ]
ce_fusa: ce_fusa:
safe: yes safe: yes
@@ -465,7 +566,9 @@ ce_fusa:
sources: [ hal/ce/ce_gp10b_fusa.c, sources: [ hal/ce/ce_gp10b_fusa.c,
hal/ce/ce_gp10b.h, hal/ce/ce_gp10b.h,
hal/ce/ce_gv11b_fusa.c, hal/ce/ce_gv11b_fusa.c,
hal/ce/ce_gv11b.h ] hal/ce/ce_gv11b.h,
hal/ce/ce_ga10b_fusa.c,
hal/ce/ce_ga10b.h ]
ce: ce:
safe: no safe: no
@@ -482,12 +585,17 @@ gr:
ecc_fusa: ecc_fusa:
safe: yes safe: yes
sources: [hal/gr/ecc/ecc_gv11b_fusa.c, sources: [hal/gr/ecc/ecc_gv11b_fusa.c,
hal/gr/ecc/ecc_gv11b.h ] hal/gr/ecc/ecc_gv11b.h,
hal/gr/ecc/ecc_ga10b_fusa.c,
hal/gr/ecc/ecc_ga10b.h ]
ecc: ecc:
safe: no safe: no
sources: [hal/gr/ecc/ecc_gv11b.c, sources: [hal/gr/ecc/ecc_gv11b.c,
hal/gr/ecc/ecc_gp10b.c, hal/gr/ecc/ecc_gp10b.c,
hal/gr/ecc/ecc_gp10b.h ] hal/gr/ecc/ecc_gp10b.h,
hal/gr/ecc/ecc_ga10b.c ]
ctxsw_prog_fusa: ctxsw_prog_fusa:
safe: yes safe: yes
sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c, sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b_fusa.c,
@@ -495,13 +603,23 @@ gr:
hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c, hal/gr/ctxsw_prog/ctxsw_prog_gp10b_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h, hal/gr/ctxsw_prog/ctxsw_prog_gp10b.h,
hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c, hal/gr/ctxsw_prog/ctxsw_prog_gv11b_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h ] hal/gr/ctxsw_prog/ctxsw_prog_gv11b.h,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h,
hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100.h]
ctxsw_prog: ctxsw_prog:
safe: no safe: no
sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c, sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c,
hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c, hal/gr/ctxsw_prog/ctxsw_prog_gm20b_dbg.c,
hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c, hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c,
hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c] hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c ]
config_fusa: config_fusa:
safe: yes safe: yes
sources: [ hal/gr/config/gr_config_gm20b_fusa.c, sources: [ hal/gr/config/gr_config_gm20b_fusa.c,
@@ -520,7 +638,12 @@ gr:
hal/gr/init/gr_init_gp10b_fusa.c, hal/gr/init/gr_init_gp10b_fusa.c,
hal/gr/init/gr_init_gp10b.h, hal/gr/init/gr_init_gp10b.h,
hal/gr/init/gr_init_gv11b_fusa.c, hal/gr/init/gr_init_gv11b_fusa.c,
hal/gr/init/gr_init_gv11b.h ] hal/gr/init/gr_init_gv11b.h,
hal/gr/init/gr_init_ga10b_fusa.c,
hal/gr/init/gr_init_ga100_fusa.c,
hal/gr/init/gr_init_ga100.h,
hal/gr/init/gr_init_ga10b.h ]
init: init:
safe: no safe: no
sources: [ hal/gr/init/gr_init_gm20b.c, sources: [ hal/gr/init/gr_init_gm20b.c,
@@ -529,7 +652,12 @@ gr:
hal/gr/init/gr_init_gv100.h, hal/gr/init/gr_init_gv100.h,
hal/gr/init/gr_init_gv11b.c, hal/gr/init/gr_init_gv11b.c,
hal/gr/init/gr_init_tu104.c, hal/gr/init/gr_init_tu104.c,
hal/gr/init/gr_init_tu104.h ] hal/gr/init/gr_init_tu104.h,
hal/gr/init/gr_init_ga10b.c,
hal/gr/init/gr_init_ga10b.h,
hal/gr/init/gr_init_ga100.c,
hal/gr/init/gr_init_ga100.h ]
intr_fusa: intr_fusa:
safe: yes safe: yes
sources: [ hal/gr/intr/gr_intr_gm20b_fusa.c, sources: [ hal/gr/intr/gr_intr_gm20b_fusa.c,
@@ -537,7 +665,12 @@ gr:
hal/gr/intr/gr_intr_gp10b_fusa.c, hal/gr/intr/gr_intr_gp10b_fusa.c,
hal/gr/intr/gr_intr_gp10b.h, hal/gr/intr/gr_intr_gp10b.h,
hal/gr/intr/gr_intr_gv11b_fusa.c, hal/gr/intr/gr_intr_gv11b_fusa.c,
hal/gr/intr/gr_intr_gv11b.h ] hal/gr/intr/gr_intr_gv11b.h,
hal/gr/intr/gr_intr_ga10b_fusa.c,
hal/gr/intr/gr_intr_ga10b.h,
hal/gr/intr/gr_intr_ga100_fusa.c,
hal/gr/intr/gr_intr_ga100.h ]
intr: intr:
safe: no safe: no
sources: [ hal/gr/intr/gr_intr_gm20b.c, sources: [ hal/gr/intr/gr_intr_gm20b.c,
@@ -551,12 +684,19 @@ gr:
hal/gr/falcon/gr_falcon_gp10b_fusa.c, hal/gr/falcon/gr_falcon_gp10b_fusa.c,
hal/gr/falcon/gr_falcon_gp10b.h, hal/gr/falcon/gr_falcon_gp10b.h,
hal/gr/falcon/gr_falcon_gv11b_fusa.c, hal/gr/falcon/gr_falcon_gv11b_fusa.c,
hal/gr/falcon/gr_falcon_gv11b.h ] hal/gr/falcon/gr_falcon_gv11b.h,
hal/gr/falcon/gr_falcon_ga10b_fusa.c,
hal/gr/falcon/gr_falcon_ga10b.h ]
falcon: falcon:
safe: no safe: no
sources: [ hal/gr/falcon/gr_falcon_gm20b.c, sources: [ hal/gr/falcon/gr_falcon_gm20b.c,
hal/gr/falcon/gr_falcon_tu104.c, hal/gr/falcon/gr_falcon_tu104.c,
hal/gr/falcon/gr_falcon_tu104.h ] hal/gr/falcon/gr_falcon_tu104.h,
hal/gr/falcon/gr_falcon_ga10b.c,
hal/gr/falcon/gr_falcon_ga100.c,
hal/gr/falcon/gr_falcon_ga100.h ]
fecs_trace: fecs_trace:
safe: no safe: no
sources: [ hal/gr/fecs_trace/fecs_trace_gm20b.c, sources: [ hal/gr/fecs_trace/fecs_trace_gm20b.c,
@@ -575,7 +715,10 @@ gr:
hal/gr/zbc/zbc_gp10b.c, hal/gr/zbc/zbc_gp10b.c,
hal/gr/zbc/zbc_gp10b.h, hal/gr/zbc/zbc_gp10b.h,
hal/gr/zbc/zbc_gv11b.c, hal/gr/zbc/zbc_gv11b.c,
hal/gr/zbc/zbc_gv11b.h ] hal/gr/zbc/zbc_gv11b.h,
hal/gr/zbc/zbc_ga10b.c,
hal/gr/zbc/zbc_ga10b.h ]
zcull: zcull:
safe: no safe: no
sources: [ hal/gr/zcull/zcull_gm20b.c, sources: [ hal/gr/zcull/zcull_gm20b.c,
@@ -592,7 +735,13 @@ gr:
hal/gr/gr/gr_tu104.c, hal/gr/gr/gr_tu104.h, hal/gr/gr/gr_tu104.c, hal/gr/gr/gr_tu104.h,
include/nvgpu/gr/warpstate.h, include/nvgpu/gr/warpstate.h,
hal/gr/gr/gr_pri_gk20a.h, hal/gr/gr/gr_pri_gk20a.h,
hal/gr/gr/gr_pri_gv11b.h ] hal/gr/gr/gr_pri_gv11b.h,
hal/gr/gr/gr_ga10b.c,
hal/gr/gr/gr_ga10b.h,
hal/gr/gr/gr_ga100.c,
hal/gr/gr/gr_ga100.h,
hal/gr/gr/gr_pri_ga10b.h ]
regops: regops:
safe: no safe: no
@@ -608,13 +757,23 @@ regops:
hal/regops/allowlist_gv11b.c, hal/regops/allowlist_gv11b.c,
hal/regops/allowlist_gv11b.h, hal/regops/allowlist_gv11b.h,
hal/regops/allowlist_tu104.c, hal/regops/allowlist_tu104.c,
hal/regops/allowlist_tu104.h ] hal/regops/allowlist_tu104.h,
hal/regops/regops_ga10b.c,
hal/regops/regops_ga100.c,
hal/regops/regops_ga10b.h,
hal/regops/regops_ga100.h,
hal/regops/allowlist_ga10b.c,
hal/regops/allowlist_ga10b.h,
hal/regops/allowlist_ga100.c,
hal/regops/allowlist_ga100.h ]
falcon_fusa: falcon_fusa:
safe: yes safe: yes
owner: Sagar K owner: Sagar K
sources: [ hal/falcon/falcon_gk20a_fusa.c, sources: [ hal/falcon/falcon_gk20a_fusa.c,
hal/falcon/falcon_gk20a.h ] hal/falcon/falcon_gk20a.h,
hal/falcon/falcon_ga10b_fusa.c,
hal/falcon/falcon_ga10b.h ]
falcon: falcon:
safe: no safe: no
@@ -629,7 +788,11 @@ mc_fusa:
hal/mc/mc_gp10b_fusa.c, hal/mc/mc_gp10b_fusa.c,
hal/mc/mc_gp10b.h, hal/mc/mc_gp10b.h,
hal/mc/mc_gv11b_fusa.c, hal/mc/mc_gv11b_fusa.c,
hal/mc/mc_gv11b.h ] hal/mc/mc_gv11b.h,
hal/mc/mc_intr_ga10b_fusa.c,
hal/mc/mc_intr_ga10b.h,
hal/mc/mc_ga10b_fusa.c,
hal/mc/mc_ga10b.h ]
mc: mc:
safe: no safe: no
@@ -651,7 +814,17 @@ fb_fusa:
hal/fb/ecc/fb_ecc_gv11b.h, hal/fb/ecc/fb_ecc_gv11b_fusa.c, hal/fb/ecc/fb_ecc_gv11b.h, hal/fb/ecc/fb_ecc_gv11b_fusa.c,
hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c, hal/fb/intr/fb_intr_gv11b.h, hal/fb/intr/fb_intr_gv11b_fusa.c,
hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c, hal/fb/fb_mmu_fault_gv11b.h, hal/fb/fb_mmu_fault_gv11b_fusa.c,
hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b_fusa.c ] hal/fb/intr/fb_intr_ecc_gv11b.h, hal/fb/intr/fb_intr_ecc_gv11b_fusa.c,
hal/fb/fb_ga10b.h,
hal/fb/fb_ga10b_fusa.c,
hal/fb/ecc/fb_ecc_ga10b.h,
hal/fb/ecc/fb_ecc_ga10b_fusa.c,
hal/fb/intr/fb_intr_ga10b.h,
hal/fb/intr/fb_intr_ga10b_fusa.c,
hal/fb/fb_mmu_fault_ga10b.h,
hal/fb/fb_mmu_fault_ga10b_fusa.c,
hal/fb/intr/fb_intr_ecc_ga10b.h,
hal/fb/intr/fb_intr_ecc_ga10b_fusa.c ]
fb: fb:
safe: no safe: no
@@ -665,7 +838,12 @@ fb:
hal/fb/intr/fb_intr_gv100.h, hal/fb/intr/fb_intr_gv100.c, hal/fb/intr/fb_intr_gv100.h, hal/fb/intr/fb_intr_gv100.c,
hal/fb/fb_mmu_fault_tu104.h, hal/fb/fb_mmu_fault_tu104.c, hal/fb/fb_mmu_fault_tu104.h, hal/fb/fb_mmu_fault_tu104.c,
hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h, hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h,
hal/fb/intr/fb_intr_ecc_gv11b.c ] hal/fb/intr/fb_intr_ecc_gv11b.c,
hal/fb/fb_ga10b.c,
hal/fb/fb_ga100.h,
hal/fb/fb_ga100.c,
hal/fb/vab/vab_ga10b.c,
hal/fb/vab/vab_ga10b.h ]
pmu_fusa: pmu_fusa:
safe: yes safe: yes
@@ -685,7 +863,11 @@ pmu:
hal/pmu/pmu_gp10b.h, hal/pmu/pmu_gp10b.h,
hal/pmu/pmu_gv11b.c, hal/pmu/pmu_gv11b.c,
hal/pmu/pmu_tu104.c, hal/pmu/pmu_tu104.c,
hal/pmu/pmu_tu104.h ] hal/pmu/pmu_tu104.h,
hal/pmu/pmu_ga10b.h,
hal/pmu/pmu_ga10b.c,
hal/pmu/pmu_ga100.h,
hal/pmu/pmu_ga100.c ]
nvlink: nvlink:
safe: yes safe: yes
@@ -718,7 +900,9 @@ netlist_fusa:
gpu: both gpu: both
sources: [ include/nvgpu/gops/netlist.h, sources: [ include/nvgpu/gops/netlist.h,
hal/netlist/netlist_gv11b_fusa.c, hal/netlist/netlist_gv11b_fusa.c,
hal/netlist/netlist_gv11b.h ] hal/netlist/netlist_gv11b.h,
hal/netlist/netlist_ga10b_fusa.c,
hal/netlist/netlist_ga10b.h ]
netlist: netlist:
safe: no safe: no
@@ -731,14 +915,18 @@ netlist:
hal/netlist/netlist_gv100.c, hal/netlist/netlist_gv100.c,
hal/netlist/netlist_gv100.h, hal/netlist/netlist_gv100.h,
hal/netlist/netlist_tu104.c, hal/netlist/netlist_tu104.c,
hal/netlist/netlist_tu104.h ] hal/netlist/netlist_tu104.h,
hal/netlist/netlist_ga100.c,
hal/netlist/netlist_ga100.h ]
nvdec: nvdec:
safe: no safe: no
sources: [ hal/nvdec/nvdec_gp106.c, sources: [ hal/nvdec/nvdec_gp106.c,
hal/nvdec/nvdec_gp106.h, hal/nvdec/nvdec_gp106.h,
hal/nvdec/nvdec_tu104.c, hal/nvdec/nvdec_tu104.c,
hal/nvdec/nvdec_tu104.h ] hal/nvdec/nvdec_tu104.h,
hal/nvdec/nvdec_ga100.c,
hal/nvdec/nvdec_ga100.h ]
perf: perf:
safe: no safe: no
@@ -748,7 +936,11 @@ perf:
hal/perf/perf_gv11b.c, hal/perf/perf_gv11b.c,
hal/perf/perf_gv11b.h, hal/perf/perf_gv11b.h,
hal/perf/perf_tu104.c, hal/perf/perf_tu104.c,
hal/perf/perf_tu104.h ] hal/perf/perf_tu104.h,
hal/perf/perf_ga10b.c,
hal/perf/perf_ga10b.h,
hal/perf/perf_ga100.c,
hal/perf/perf_ga100.h ]
pramin: pramin:
safe: yes safe: yes
@@ -776,14 +968,21 @@ class:
sources: [ hal/class/class_gm20b.c, sources: [ hal/class/class_gm20b.c,
hal/class/class_gp10b.c, hal/class/class_gp10b.c,
hal/class/class_tu104.c, hal/class/class_tu104.c,
hal/class/class_tu104.h ] hal/class/class_tu104.h,
hal/class/class_ga10b.h,
hal/class/class_ga10b.c,
hal/class/class_ga100.h,
hal/class/class_ga100.c ]
func: func:
safe: yes safe: yes
owner: Terje B owner: Terje B
gpu: dgpu gpu: dgpu
sources: [ hal/func/func_tu104.c, sources: [ hal/func/func_tu104.c,
hal/func/func_tu104.h ] hal/func/func_tu104.h,
hal/func/func_ga10b.c,
hal/func/func_ga10b.h ]
top_fusa: top_fusa:
safe: yes safe: yes
@@ -803,7 +1002,9 @@ top:
hal/top/top_gp106.h, hal/top/top_gp106.h,
hal/top/top_gp10b.c, hal/top/top_gp10b.c,
hal/top/top_gv100.c, hal/top/top_gv100.c,
hal/top/top_gv100.h ] hal/top/top_gv100.h,
hal/top/top_ga10b.h,
hal/top/top_ga10b_fusa.c ]
bios: bios:
safe: yes safe: yes
@@ -834,3 +1035,17 @@ cic:
sources: [ hal/cic/cic_gv11b_fusa.c, sources: [ hal/cic/cic_gv11b_fusa.c,
hal/cic/cic_lut_gv11b_fusa.c, hal/cic/cic_lut_gv11b_fusa.c,
hal/cic/cic_gv11b.h ] hal/cic/cic_gv11b.h ]
misc:
safe: no
owner: Vedashree V
sources: [ nvgpu_next_gpuid.h ]
grmgr:
safe: no
owner: Lakshmanan M
sources: [ hal/grmgr/grmgr_ga10b.c,
hal/grmgr/grmgr_ga10b.h,
hal/grmgr/grmgr_ga100.c,
hal/grmgr/grmgr_ga100.h,]

4
arch/nvgpu-hal-vgpu.yaml
View File

@@ -9,7 +9,9 @@ init:
sources: [ hal/vgpu/init/init_hal_vgpu.c, sources: [ hal/vgpu/init/init_hal_vgpu.c,
hal/vgpu/init/init_hal_vgpu.h, hal/vgpu/init/init_hal_vgpu.h,
hal/vgpu/init/vgpu_hal_gv11b.c, hal/vgpu/init/vgpu_hal_gv11b.c,
hal/vgpu/init/vgpu_hal_gv11b.h ] hal/vgpu/init/vgpu_hal_gv11b.h,
hal/vgpu/init/vgpu_hal_ga10b.c,
hal/vgpu/init/vgpu_hal_ga10b.h ]
fifo: fifo:
safe : no safe : no

5
arch/nvgpu-linux.yaml
View File

@@ -183,7 +183,9 @@ platform:
os/linux/platform_gk20a_tegra.h, os/linux/platform_gk20a_tegra.h,
os/linux/platform_gp10b.h, os/linux/platform_gp10b.h,
os/linux/platform_gp10b_tegra.c, os/linux/platform_gp10b_tegra.c,
os/linux/platform_gv11b_tegra.c ] os/linux/platform_gv11b_tegra.c,
os/linux/platform_ga10b_tegra.c,
os/linux/nvlink/hal/ga10b_mssnvlink.c ]
rwsem: rwsem:
sources: [ os/linux/rwsem.c ] sources: [ os/linux/rwsem.c ]
@@ -216,6 +218,7 @@ vgpu:
sources: [ os/linux/vgpu/fecs_trace_vgpu_linux.c, sources: [ os/linux/vgpu/fecs_trace_vgpu_linux.c,
os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c, os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c,
os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.h, os/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.h,
os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c,
os/linux/vgpu/platform_vgpu_tegra.c, os/linux/vgpu/platform_vgpu_tegra.c,
os/linux/vgpu/platform_vgpu_tegra.h, os/linux/vgpu/platform_vgpu_tegra.h,
os/linux/vgpu/sysfs_vgpu.c, os/linux/vgpu/sysfs_vgpu.c,

180
arch/nvgpu-next-common.yaml
View File

@@ -1,180 +0,0 @@
#
# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# Common elements and units in nvgpu.
#
##
## Common elements.
##
nvgpu_next_fifo:
safe: no
owner: Seshendra G
children:
engines:
safe: no
sources: [ include/nvgpu/nvgpu_next_engines.h,
common/fifo/nvgpu_next_engines.c ]
runlist:
safe: no
sources: [ include/nvgpu/nvgpu_next_runlist.h,
common/fifo/nvgpu_next_runlist.c ]
pbdma:
safe: no
sources: [ include/nvgpu/nvgpu_next_pbdma.h ]
fifo:
safe: no
sources: [ include/nvgpu/nvgpu_next_gops_fifo.h ]
nvgpu_next_sim:
safe: no
owner: Vedashree V
sources: [ include/nvgpu/nvgpu_next_sim.h,
common/sim/nvgpu_next_sim_netlist.c,
common/sim/nvgpu_next_sim.c ]
nvgpu_next_netlist:
safe: no
owner: Vedashree V
sources: [ include/nvgpu/nvgpu_next_gops_fifo.h,
include/nvgpu/nvgpu_next_netlist.h,
common/netlist/nvgpu_next_netlist_priv.h,
common/netlist/nvgpu_next_netlist.c ]
nvgpu_next_gr:
safe: no
owner: Vedashree V
sources: [ include/nvgpu/nvgpu_next_gops_gr.h,
include/nvgpu/gr/nvgpu_next_gr.h,
include/nvgpu/gr/nvgpu_next_fs_state.h,
include/nvgpu/gr/nvgpu_next_gr_ecc.h,
include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h,
common/gr/nvgpu_next_fs_state.c,
common/gr/nvgpu_next_gr.c ]
nvgpu_next_bios:
safe: no
owner: Thomas F
sources: [ common/vbios/bios_sw_ga100.c,
common/vbios/bios_sw_ga100.h ]
nvgpu_next_device:
safe: yes
owner: Alex W
sources: [ include/nvgpu/nvgpu_next_device.h ]
nvgpu_next_ltc:
safe: no
owner: Antony
sources: [ include/nvgpu/nvgpu_next_gops_ltc.h,
include/nvgpu/nvgpu_next_gops_ltc_intr.h ]
nvgpu_next_ce:
safe: no
owner: Antony
sources: [ include/nvgpu/nvgpu_next_gops_ce.h ]
nvgpu_next_grmgr:
safe: no
owner: Lakshmanan M
sources: [ include/nvgpu/nvgpu_next_gops_grmgr.h ]
nvgpu_next_priv_ring:
safe: no
owner: Lakshmanan M
sources: [ include/nvgpu/nvgpu_next_gops_priv_ring.h ]
nvgpu_next_pmu_perfmon:
safe: no
owner: Ramesh M
sources: [ common/pmu/perfmon/pmu_perfmon_sw_ga10b.c,
common/pmu/perfmon/pmu_perfmon_sw_ga10b.h ]
nvgpu_next_mc:
safe: yes
owner: Antony Clince Alex
sources: [ common/mc/nvgpu_next_mc.c,
include/nvgpu/nvgpu_next_mc.h ]
nvgpu_next_cic:
safe: yes
owner: Tejal Kudav
sources: [ include/nvgpu/nvgpu_next_cic.h,
common/cic/nvgpu_next_cic.c ]
nvgpu_next_pmu_pg:
safe: no
owner: Ramesh M
sources: [ common/pmu/pg/pg_sw_ga10b.c,
common/pmu/pg/pg_sw_ga10b.h ]
nvgpu_next_err:
safe: yes
owner: Antony Clince Alex
sources: [ include/nvgpu/nvgpu_next_err.h ]
nvgpu_next_acr_fusa:
safe: no
owner: Deepak G
sources: [ common/acr/nvgpu_next_acr_bootstrap.c,
common/acr/nvgpu_next_acr_bootstrap.h,
include/nvgpu/riscv.h,
common/riscv/riscv.c ]
nvgpu_next_acr:
safe: no
owner: Deepak G
sources: [ common/acr/acr_sw_ga10b.c,
common/acr/acr_sw_ga10b.h,
common/acr/acr_sw_ga100.c,
common/acr/acr_sw_ga100.h ]
nvgpu_next_falcon:
safe: no
owner: Deepak G
sources: [ common/falcon/falcon_sw_ga10b.c,
common/falcon/falcon_sw_ga10b.h ]
nvgpu_next_litter:
safe: no
owner: Antony
sources: [ include/nvgpu/nvgpu_next_litter.h ]
nvgpu_next_profiler:
safe: no
owner: Antony
sources: [ common/profiler/nvgpu_next_profiler.h,
common/profiler/nvgpu_next_profiler.c ]
nvgpu_next_fb:
safe: no
owner: Vedashree V
sources: [ common/fb/nvgpu_next_fb.c ]
nvgpu_next_utils:
safe: no
owner: Vedashree V
sources: [ include/nvgpu/nvgpu_next_errata.h ]

98
arch/nvgpu-next-gpu_hw.yaml
View File

@@ -1,98 +0,0 @@
#
# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# Define meta elements and units for describing GPU HW interactions in
# nvgpu.
#
nvgpu_next_headers:
safe: no
owner: Seshendra G
sources: [ include/nvgpu/hw/ga100/hw_bus_ga100.h,
include/nvgpu/hw/ga100/hw_ce_ga100.h,
include/nvgpu/hw/ga100/hw_ctrl_ga100.h,
include/nvgpu/hw/ga100/hw_ctxsw_prog_ga100.h,
include/nvgpu/hw/ga100/hw_falcon_ga100.h,
include/nvgpu/hw/ga100/hw_fb_ga100.h,
include/nvgpu/hw/ga100/hw_flush_ga100.h,
include/nvgpu/hw/ga100/hw_func_ga100.h,
include/nvgpu/hw/ga100/hw_fuse_ga100.h,
include/nvgpu/hw/ga100/hw_gc6_ga100.h,
include/nvgpu/hw/ga100/hw_gmmu_ga100.h,
include/nvgpu/hw/ga100/hw_gr_ga100.h,
include/nvgpu/hw/ga100/hw_ltc_ga100.h,
include/nvgpu/hw/ga100/hw_mc_ga100.h,
include/nvgpu/hw/ga100/hw_pbdma_ga100.h,
include/nvgpu/hw/ga100/hw_perf_ga100.h,
include/nvgpu/hw/ga100/hw_pgsp_ga100.h,
include/nvgpu/hw/ga100/hw_pram_ga100.h,
include/nvgpu/hw/ga100/hw_pri_fbp_ga100.h,
include/nvgpu/hw/ga100/hw_pri_gpc_ga100.h,
include/nvgpu/hw/ga100/hw_pri_ringmaster_ga100.h,
include/nvgpu/hw/ga100/hw_pri_ringstation_sys_ga100.h,
include/nvgpu/hw/ga100/hw_pri_sys_ga100.h,
include/nvgpu/hw/ga100/hw_proj_ga100.h,
include/nvgpu/hw/ga100/hw_psec_ga100.h,
include/nvgpu/hw/ga100/hw_pwr_ga100.h,
include/nvgpu/hw/ga100/hw_ram_ga100.h,
include/nvgpu/hw/ga100/hw_runlist_ga100.h,
include/nvgpu/hw/ga100/hw_smcarb_ga100.h,
include/nvgpu/hw/ga100/hw_timer_ga100.h,
include/nvgpu/hw/ga100/hw_top_ga100.h,
include/nvgpu/hw/ga100/hw_pnvdec_ga100.h,
include/nvgpu/hw/ga100/hw_therm_ga100.h,
include/nvgpu/hw/ga100/hw_trim_ga100.h,
include/nvgpu/hw/ga100/hw_xp_ga100.h,
include/nvgpu/hw/ga100/hw_xve_ga100.h,
include/nvgpu/hw/ga100/hw_fbpa_ga100.h,
include/nvgpu/hw/ga10b/hw_bus_ga10b.h,
include/nvgpu/hw/ga10b/hw_ccsr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ce_ga10b.h,
include/nvgpu/hw/ga10b/hw_ctrl_ga10b.h,
include/nvgpu/hw/ga10b/hw_ctxsw_prog_ga10b.h,
include/nvgpu/hw/ga10b/hw_falcon_ga10b.h,
include/nvgpu/hw/ga10b/hw_fb_ga10b.h,
include/nvgpu/hw/ga10b/hw_flush_ga10b.h,
include/nvgpu/hw/ga10b/hw_func_ga10b.h,
include/nvgpu/hw/ga10b/hw_fuse_ga10b.h,
include/nvgpu/hw/ga10b/hw_gmmu_ga10b.h,
include/nvgpu/hw/ga10b/hw_gr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ltc_ga10b.h,
include/nvgpu/hw/ga10b/hw_mc_ga10b.h,
include/nvgpu/hw/ga10b/hw_pbdma_ga10b.h,
include/nvgpu/hw/ga10b/hw_perf_ga10b.h,
include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h,
include/nvgpu/hw/ga10b/hw_pram_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_fbp_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_gpc_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_ringmaster_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_ringstation_sys_ga10b.h,
include/nvgpu/hw/ga10b/hw_pri_sys_ga10b.h,
include/nvgpu/hw/ga10b/hw_proj_ga10b.h,
include/nvgpu/hw/ga10b/hw_priscv_ga10b.h,
include/nvgpu/hw/ga10b/hw_pwr_ga10b.h,
include/nvgpu/hw/ga10b/hw_ram_ga10b.h,
include/nvgpu/hw/ga10b/hw_runlist_ga10b.h,
include/nvgpu/hw/ga10b/hw_smcarb_ga10b.h,
include/nvgpu/hw/ga10b/hw_therm_ga10b.h,
include/nvgpu/hw/ga10b/hw_timer_ga10b.h,
include/nvgpu/hw/ga10b/hw_top_ga10b.h ]

30
arch/nvgpu-next-hal-vgpu.yaml
View File

@@ -1,30 +0,0 @@
#
# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# VGPU HAL units.
#
vgpu-next-init:
safe: no
owner: Aparna D
sources: [ hal/vgpu/init/vgpu_hal_ga10b.c,
hal/vgpu/init/vgpu_hal_ga10b.h ]

427
arch/nvgpu-next-hal.yaml
View File

@@ -1,427 +0,0 @@
#
# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# HAL units. These are the units that have access to HW.
#
nvgpu_next_init:
safe: no
owner: Seshendra G
sources: [ hal/init/hal_ga100.c,
hal/init/hal_ga100.h,
hal/init/hal_ga10b.c,
hal/init/hal_ga10b.h,
hal/init/hal_ga100_litter.c,
hal/init/hal_ga100_litter.h,
hal/init/hal_ga10b_litter.c,
hal/init/hal_ga10b_litter.h ]
nvgpu_next_class:
safe: no
owner: Seshendra G
sources: [ hal/class/class_ga10b.h,
hal/class/class_ga10b.c,
hal/class/class_ga100.h,
hal/class/class_ga100.c,
include/nvgpu/nvgpu_next_class.h ]
nvgpu_next_top:
safe: no
owner: Seshendra G
sources: [ hal/top/top_ga10b.h,
hal/top/top_ga10b_fusa.c ]
nvgpu_next_fuse:
safe: no
owner: Seshendra G
sources: [ include/nvgpu/nvgpu_next_gops_fuse.h,
include/nvgpu/nvgpu_next_fuse.h,
hal/fuse/fuse_ga10b.h,
hal/fuse/fuse_ga100.h,
hal/fuse/fuse_ga10b.c,
hal/fuse/fuse_ga100.c ]
nvgpu_next_clk:
safe: no
sources: [ hal/clk/clk_ga100.c,
hal/clk/clk_ga100.h ]
nvgpu_next_fifo:
safe: no
owner: Seshendra G
children:
runlist:
safe: no
sources: [ include/nvgpu/nvgpu_next_gops_runlist.h,
hal/fifo/runlist_ga10b.h,
hal/fifo/runlist_ga10b_fusa.c ]
runlist_fusa:
safe: no
sources: [ hal/fifo/runlist_fifo_ga10b.h,
hal/fifo/runlist_fifo_ga10b.c,
hal/fifo/runlist_fifo_ga10b_fusa.c,
hal/fifo/runlist_fifo_ga100.h,
hal/fifo/runlist_fifo_ga100_fusa.c ]
fifo_fusa:
safe: no
sources: [ hal/fifo/fifo_ga10b_fusa.c,
hal/fifo/fifo_intr_ga10b_fusa.c,
hal/fifo/ctxsw_timeout_ga10b_fusa.c,
hal/fifo/ctxsw_timeout_ga10b.h,
hal/fifo/fifo_intr_ga10b.h,
hal/fifo/fifo_ga10b.h ]
channel_fusa:
safe: no
sources: [ hal/fifo/channel_ga10b_fusa.c,
hal/fifo/channel_ga10b.h,
hal/fifo/channel_ga100_fusa.c,
hal/fifo/channel_ga100.h ]
tsg:
safe: no
sources: [ hal/fifo/tsg_ga10b.h,
hal/fifo/tsg_ga10b.c ]
engine_status_fusa:
safe: no
sources: [ include/nvgpu/nvgpu_next_engine_status.h,
hal/fifo/engine_status_ga10b_fusa.c,
hal/fifo/engine_status_ga10b.h ]
ramfc_fusa:
safe: no
sources: [ hal/fifo/ramfc_ga10b_fusa.c,
hal/fifo/ramfc_ga10b.h ]
pbdma_status_fusa:
safe: no
sources: [ hal/fifo/pbdma_status_ga10b_fusa.c,
hal/fifo/pbdma_status_ga10b.h ]
pbdma_fusa:
safe: no
sources: [ hal/fifo/pbdma_ga10b_fusa.c,
hal/fifo/pbdma_ga10b.h,
hal/fifo/pbdma_ga100_fusa.c,
hal/fifo/pbdma_ga100.h,
include/nvgpu/nvgpu_next_gops_pbdma.h ]
preempt_fusa:
safe: no
sources: [ hal/fifo/preempt_ga10b_fusa.c,
hal/fifo/preempt_ga10b.h ]
pbdma:
safe: no
sources: [ hal/fifo/pbdma_ga10b.c ]
ramin_fusa:
safe: no
sources: [ hal/fifo/ramin_ga10b_fusa.c,
hal/fifo/ramin_ga10b.h ]
usermode_fusa:
safe: no
sources: [ hal/fifo/usermode_ga10b_fusa.c,
hal/fifo/usermode_ga10b.h ]
userd:
safe: no
sources: [ hal/fifo/userd_ga10b.c,
hal/fifo/userd_ga10b.h ]
utils_fusa:
safe: no
sources: [ hal/fifo/fifo_utils_ga10b_fusa.c,
hal/fifo/fifo_utils_ga10b.h ]
nvgpu_next_mm:
safe: no
owner: Seema K
children:
mm:
safe: no
sources: [ include/nvgpu/nvgpu_next_mm.h ]
mmu_fault:
safe: no
sources: [ hal/mm/mmu_fault/mmu_fault_ga10b_fusa.c,
hal/mm/mmu_fault/mmu_fault_ga10b.h ]
gmmu_fusa:
safe: no
sources: [ hal/mm/gmmu/gmmu_ga10b_fusa.c,
hal/mm/gmmu/gmmu_ga10b.h ]
nvgpu_next_gr:
safe: no
owner: Seema K
children:
ctxsw_prog_fusa:
safe: no
sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b.h,
hal/gr/ctxsw_prog/ctxsw_prog_ga100_fusa.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100.h]
ctxsw_prog:
safe: no
sources: [ hal/gr/ctxsw_prog/ctxsw_prog_ga10b.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga10b_dbg.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100.c,
hal/gr/ctxsw_prog/ctxsw_prog_ga100_dbg.c ]
init_fusa:
safe: no
sources: [ include/nvgpu/nvgpu_next_gops_gr_init.h,
hal/gr/init/gr_init_ga10b_fusa.c,
hal/gr/init/gr_init_ga100_fusa.c,
hal/gr/init/gr_init_ga100.h,
hal/gr/init/gr_init_ga10b.h ]
init:
safe: no
sources: [ hal/gr/init/gr_init_ga10b.c,
hal/gr/init/gr_init_ga10b.h,
hal/gr/init/gr_init_ga100.c,
hal/gr/init/gr_init_ga100.h ]
intr_fusa:
safe: no
sources: [ include/nvgpu/nvgpu_next_gops_gr_intr.h,
hal/gr/intr/gr_intr_ga10b_fusa.c,
hal/gr/intr/gr_intr_ga10b.h,
hal/gr/intr/gr_intr_ga100_fusa.c,
hal/gr/intr/gr_intr_ga100.h ]
gr:
safe: no
sources: [ hal/gr/gr/gr_ga10b.c,
hal/gr/gr/gr_ga10b.h,
hal/gr/gr/gr_ga100.c,
hal/gr/gr/gr_ga100.h,
hal/gr/gr/gr_pri_ga10b.h ]
falcon_fusa:
safe: no
sources: [ hal/gr/falcon/gr_falcon_ga10b_fusa.c,
hal/gr/falcon/gr_falcon_ga10b.h ]
falcon:
safe: no
sources: [ hal/gr/falcon/gr_falcon_ga10b.c,
hal/gr/falcon/gr_falcon_ga100.c,
hal/gr/falcon/gr_falcon_ga100.h ]
zbc:
safe: no
sources: [ hal/gr/zbc/zbc_ga10b.c,
hal/gr/zbc/zbc_ga10b.h ]
ecc_fusa:
safe: no
sources: [ hal/gr/ecc/ecc_ga10b_fusa.c,
hal/gr/ecc/ecc_ga10b.h ]
ecc:
safe: no
sources: [ hal/gr/ecc/ecc_ga10b.c ,
hal/gr/ecc/ecc_ga10b.h ]
nvgpu_next_ltc:
safe: no
owner: Vedashree V
children:
ltc:
safe: no
sources: [ hal/ltc/ltc_ga10b.c ]
ltc_fusa:
safe: no
sources: [ hal/ltc/ltc_ga10b.h,
hal/ltc/ltc_ga10b_fusa.c ]
ltc_intr:
safe: no
sources: [ hal/ltc/intr/ltc_intr_ga10b.h,
hal/ltc/intr/ltc_intr_ga10b_fusa.c ]
nvgpu_next_mc_fusa:
safe: no
owner: Seema K
sources: [ hal/mc/mc_intr_ga10b_fusa.c,
include/nvgpu/nvgpu_next_mc.h,
hal/mc/mc_intr_ga10b.h,
include/nvgpu/nvgpu_next_gops_mc.h,
hal/mc/mc_ga10b_fusa.c,
hal/mc/mc_ga10b.h ]
nvgpu_next_cbc:
safe: no
owner: Vedashree V
sources: [ hal/cbc/cbc_ga10b.c,
hal/cbc/cbc_ga10b.h,
hal/cbc/cbc_ga100.c,
hal/cbc/cbc_ga100.h ]
nvgpu_next_fb:
safe: no
owner: Vedashree V
sources: [ hal/fb/fb_ga10b.c,
hal/fb/fb_ga100.h,
hal/fb/fb_ga100.c,
hal/fb/vab/vab_ga10b.c,
hal/fb/vab/vab_ga10b.h,
include/nvgpu/nvgpu_next_fb.h,
include/nvgpu/nvgpu_next_gops_fb_vab.h ]
nvgpu_next_fb_fusa:
safe: no
owner: Seshendra G
sources: [ include/nvgpu/nvgpu_next_ecc.h,
hal/fb/fb_ga10b.h,
hal/fb/fb_ga10b_fusa.c,
include/nvgpu/nvgpu_next_gops_fb.h,
hal/fb/ecc/fb_ecc_ga10b.h,
hal/fb/ecc/fb_ecc_ga10b_fusa.c,
hal/fb/intr/fb_intr_ga10b.h,
hal/fb/intr/fb_intr_ga10b_fusa.c,
hal/fb/fb_mmu_fault_ga10b.h,
hal/fb/fb_mmu_fault_ga10b_fusa.c,
hal/fb/intr/fb_intr_ecc_ga10b.h,
hal/fb/intr/fb_intr_ecc_ga10b_fusa.c ]
nvgpu_next_netlist:
safe: no
owner: Seshendra G
sources: [ hal/netlist/netlist_ga10b_fusa.c,
hal/netlist/netlist_ga10b.h,
hal/netlist/netlist_ga100.c,
hal/netlist/netlist_ga100.h ]
nvgpu_next_bus:
safe: no
owner: Seshendra G
sources: [ hal/bus/bus_ga10b.c,
hal/bus/bus_ga10b.h,
hal/bus/bus_ga100.c,
hal/bus/bus_ga100.h ]
nvgpu_next_regops:
safe: no
owner: Seshendra G
sources: [ hal/regops/regops_ga10b.c,
hal/regops/regops_ga100.c,
hal/regops/regops_ga10b.h,
hal/regops/regops_ga100.h,
hal/regops/allowlist_ga10b.c,
hal/regops/allowlist_ga10b.h,
hal/regops/allowlist_ga100.c,
hal/regops/allowlist_ga100.h ]
nvgpu_next_falcon_fusa:
safe: no
owner: Divya S
sources: [ hal/falcon/falcon_ga10b_fusa.c,
hal/falcon/falcon_ga10b.h ]
nvgpu_next_pmu:
safe: no
owner: Mahantesh K
sources: [ hal/pmu/pmu_ga10b.h,
hal/pmu/pmu_ga10b.c,
hal/pmu/pmu_ga100.h,
hal/pmu/pmu_ga100.c ]
nvgpu_next_gsp:
safe: no
owner: Deepak G
sources: [ hal/gsp/gsp_ga10b.h,
hal/gsp/gsp_ga10b.c ]
nvgpu_next_priv_ring_fusa:
safe: no
owner: Seema K
sources: [ hal/priv_ring/priv_ring_ga10b_fusa.c,
hal/priv_ring/priv_ring_ga10b.h,
hal/priv_ring/priv_ring_ga100_fusa.c,
hal/priv_ring/priv_ring_ga100.h ]
nvgpu_next_ptimer_fusa:
safe: no
owner: Seema K
sources: [ hal/ptimer/ptimer_ga10b_fusa.c,
hal/ptimer/ptimer_ga10b.h ]
nvgpu_next_perf:
safe: no
owner: Seshendra G
sources: [ hal/perf/perf_ga10b.c,
hal/perf/perf_ga10b.h,
hal/perf/perf_ga100.c,
hal/perf/perf_ga100.h,
include/nvgpu/nvgpu_next_gops_perf.h ]
nvgpu_next_cg:
safe: no
owner: Antony
sources: [ include/nvgpu/nvgpu_next_gops_cg.h,
hal/power_features/cg/ga10b_gating_reglist.c,
hal/power_features/cg/ga10b_gating_reglist.h,
hal/power_features/cg/ga100_gating_reglist.c,
hal/power_features/cg/ga100_gating_reglist.h ]
nvgpu_next_therm_fusa:
safe: no
owner: Antony
sources: [ hal/therm/therm_ga10b_fusa.c,
hal/therm/therm_ga10b.h ]
nvgpu_next_ce_fusa:
safe: no
owner: Antony
sources: [ hal/ce/ce_ga10b_fusa.c,
hal/ce/ce_ga10b.h ]
nvgpu_next_misc:
safe: no
owner: Vedashree V
sources: [ nvgpu_next_gpuid.h ]
nvgpu_next_nvdec:
safe: no
owner: Mahantesh K
sources: [ hal/nvdec/nvdec_ga100.c,
hal/nvdec/nvdec_ga100.h ]
nvgpu_next_grmgr:
safe: no
owner: Lakshmanan M
sources: [ hal/grmgr/grmgr_ga10b.c,
hal/grmgr/grmgr_ga10b.h,
hal/grmgr/grmgr_ga100.c,
hal/grmgr/grmgr_ga100.h,]
nvgpu_next_func:
safe: no
owner: Vedashree V
sources: [ hal/func/func_ga10b.c,
hal/func/func_ga10b.h ]

41
arch/nvgpu-next-linux.yaml
View File

@@ -1,41 +0,0 @@
#
# Copyright (c) 2020-2021, NVIDIA CORPORATION. All Rights Reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
# to deal in the Software without restriction, including without limitation
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
# and/or sell copies of the Software, and to permit persons to whom the
# Software is furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
# DEALINGS IN THE SOFTWARE.
#
# Linux elements and units in nvgpu.
#
# The safe: tag is ommited through out since all Linux units are by definition
# not safe.
#
# I also have not put a huge amount of thought into this since none of this
# code is "safe" code. Nor are we planning on spending a lot of effort to
# clean this up. At least not yet.
nvgpu_next_platform:
sources: [ os/linux/platform_ga10b_tegra.c,
os/linux/nvlink/hal/ga10b_mssnvlink.c ]
vgpu-next:
sources: [ os/linux/vgpu/ga10b/platform_ga10b_vgpu_tegra.c ]
nvgpu_next_ioctl:
sources: [ os/linux/nvgpu_next_ioctl_prof.c,
os/linux/nvgpu_next_ioctl_prof.h ]

10
arch/nvgpu.yaml
View File

@@ -14,13 +14,13 @@ nvgpu:
common: common:
safe: no safe: no
children: children:
!include nvgpu-common.yaml nvgpu-next-common.yaml !include nvgpu-common.yaml
# HAL units - Hardware Abstraction Layer. # HAL units - Hardware Abstraction Layer.
hal: hal:
safe: no safe: no
children: children:
!include nvgpu-hal-new.yaml nvgpu-next-hal.yaml !include nvgpu-hal-new.yaml
# The QNX OS layer implementation units. # The QNX OS layer implementation units.
qnx: qnx:
@@ -32,7 +32,7 @@ nvgpu:
linux: linux:
safe: no safe: no
children: children:
!include nvgpu-linux.yaml nvgpu-next-linux.yaml !include nvgpu-linux.yaml
# POSIX units for implementing the OS layer for unit testing. # POSIX units for implementing the OS layer for unit testing.
posix: posix:
@@ -58,7 +58,7 @@ nvgpu:
hal-vgpu: hal-vgpu:
safe: yes safe: yes
children: children:
!include nvgpu-hal-vgpu.yaml nvgpu-next-hal-vgpu.yaml !include nvgpu-hal-vgpu.yaml
# A meta-element for the GPU HW. A good example of this is the HW headers. # A meta-element for the GPU HW. A good example of this is the HW headers.
# This is not code we write in nvgpu, but we import it from the GPU HW # This is not code we write in nvgpu, but we import it from the GPU HW
@@ -66,4 +66,4 @@ nvgpu:
gpu_hw: gpu_hw:
safe: no safe: no
children: children:
!include nvgpu-gpu_hw.yaml nvgpu-next-gpu_hw.yaml !include nvgpu-gpu_hw.yaml

14
drivers/gpu/nvgpu/Makefile
View File

@@ -790,23 +790,12 @@ endif
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),y) ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),y)
nvgpu-y += \ nvgpu-y += \
common/fifo/nvgpu_next_engines.o \
common/fifo/nvgpu_next_runlist.o \
common/acr/nvgpu_next_acr_bootstrap.o \
common/falcon/falcon_sw_ga10b.o \ common/falcon/falcon_sw_ga10b.o \
common/fb/nvgpu_next_fb.o \
common/riscv/riscv.o \ common/riscv/riscv.o \
common/acr/acr_sw_ga10b.o \ common/acr/acr_sw_ga10b.o \
common/acr/acr_sw_ga100.o \ common/acr/acr_sw_ga100.o \
common/sim/nvgpu_next_sim.o \
common/gr/nvgpu_next_gr.o \
common/gr/nvgpu_next_fs_state.o \
common/netlist/nvgpu_next_netlist.o \
common/sim/nvgpu_next_sim_netlist.o \
common/pmu/perfmon/pmu_perfmon_sw_ga10b.o \ common/pmu/perfmon/pmu_perfmon_sw_ga10b.o \
common/cic/nvgpu_next_cic.o \ common/pmu/pg/pg_sw_ga10b.o
common/pmu/pg/pg_sw_ga10b.o \
common/profiler/nvgpu_next_profiler.o
nvgpu-y += \ nvgpu-y += \
hal/init/hal_ga10b.o \ hal/init/hal_ga10b.o \
@@ -929,5 +918,4 @@ endif
nvgpu-y += \ nvgpu-y += \
os/linux/platform_ga10b_tegra.o \ os/linux/platform_ga10b_tegra.o \
os/linux/nvgpu_next_ioctl_prof.o \
os/linux/nvlink/hal/ga10b_mssnvlink.o os/linux/nvlink/hal/ga10b_mssnvlink.o

11
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -712,23 +712,12 @@ endif
ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1) ifeq ($(CONFIG_NVGPU_HAL_NON_FUSA),1)
srcs += \ srcs += \
common/fifo/nvgpu_next_engines.c \
common/acr/nvgpu_next_acr_bootstrap.c \
common/riscv/riscv.c \ common/riscv/riscv.c \
common/acr/acr_sw_ga10b.c \ common/acr/acr_sw_ga10b.c \
common/acr/acr_sw_ga100.c \ common/acr/acr_sw_ga100.c \
common/fb/nvgpu_next_fb.c \
common/fifo/nvgpu_next_runlist.c \
common/gr/nvgpu_next_gr.c \
common/gr/nvgpu_next_fs_state.c \
common/netlist/nvgpu_next_netlist.c \
common/sim/nvgpu_next_sim.c \
common/sim/nvgpu_next_sim_netlist.c \
common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \ common/pmu/perfmon/pmu_perfmon_sw_ga10b.c \
common/cic/nvgpu_next_cic.c \
common/pmu/pg/pg_sw_ga10b.c \ common/pmu/pg/pg_sw_ga10b.c \
common/falcon/falcon_sw_ga10b.c \ common/falcon/falcon_sw_ga10b.c \
common/profiler/nvgpu_next_profiler.c
srcs += hal/init/hal_ga10b.c \ srcs += hal/init/hal_ga10b.c \
hal/init/hal_ga10b_litter.c \ hal/init/hal_ga10b_litter.c \

136
drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
View File

@@ -31,6 +31,10 @@
#include <nvgpu/acr.h> #include <nvgpu/acr.h>
#include <nvgpu/bug.h> #include <nvgpu/bug.h>
#include <nvgpu/soc.h> #include <nvgpu/soc.h>
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include <nvgpu/riscv.h>
#include <nvgpu/io.h>
#endif
#include "acr_bootstrap.h" #include "acr_bootstrap.h"
#include "acr_priv.h" #include "acr_priv.h"
@@ -252,3 +256,135 @@ err_free_ucode:
acr_desc->acr_fw = NULL; acr_desc->acr_fw = NULL;
return err; return err;
} }
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */
#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */
static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_release_firmware(g, acr->acr_asc.manifest_fw);
nvgpu_release_firmware(g, acr->acr_asc.code_fw);
nvgpu_release_firmware(g, acr->acr_asc.data_fw);
}
static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
{
int err = 0;
acr->manifest_fw = nvgpu_request_firmware(g,
acr->acr_manifest_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->manifest_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_manifest_name, g->name);
return -ENOENT;
}
acr->code_fw = nvgpu_request_firmware(g,
acr->acr_code_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->code_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_code_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
return -ENOENT;
}
acr->data_fw = nvgpu_request_firmware(g,
acr->acr_data_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->data_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_data_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
nvgpu_release_firmware(g, acr->code_fw);
return -ENOENT;
}
return err;
}
static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn,
signed int timeoutms)
{
u32 reg = 0;
do {
reg = flcn->g->ops.falcon.get_brom_retcode(flcn);
if (flcn->g->ops.falcon.check_brom_passed(reg)) {
break;
}
if (timeoutms <= 0) {
return false;
}
nvgpu_msleep(10);
timeoutms -= 10;
} while (true);
return true;
}
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
{
int err = 0;
bool brom_complete = false;
u32 timeout = 0;
u64 acr_sysmem_desc_addr = 0LL;
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err !=0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
&acr->acr_asc.acr_falcon2_sysmem_desc);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn,
acr->acr_asc.manifest_fw,
acr->acr_asc.code_fw,
acr->acr_asc.data_fw,
acr_sysmem_desc_addr);
if (nvgpu_platform_is_silicon(g)) {
timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
brom_complete = nvgpu_acr_wait_for_riscv_brom_completion(
acr->acr_asc.acr_flcn, timeout);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
if (brom_complete == false) {
nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout);
err = -ETIMEDOUT;
} else {
nvgpu_info(g, "RISCV BROM passed");
}
/* wait for complete & halt */
if (nvgpu_platform_is_silicon(g)) {
timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
ga10b_riscv_release_firmware(g, acr);
return err;
}
#endif

9
drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
View File

@@ -24,12 +24,10 @@
#define ACR_BOOTSTRAP_H #define ACR_BOOTSTRAP_H
#include "nvgpu_acr_interface.h" #include "nvgpu_acr_interface.h"
#ifdef CONFIG_NVGPU_NON_FUSA
#include "common/acr/nvgpu_next_acr_bootstrap.h"
#endif
struct gk20a; struct gk20a;
struct nvgpu_acr; struct nvgpu_acr;
struct hs_acr;
struct flcn_acr_region_prop_v0 { struct flcn_acr_region_prop_v0 {
u32 start_addr; u32 start_addr;
@@ -136,4 +134,9 @@ int nvgpu_acr_wait_for_completion(struct gk20a *g, struct hs_acr *acr_desc,
int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr, int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
struct hs_acr *acr_desc); struct hs_acr *acr_desc);
#if defined(CONFIG_NVGPU_FALCON_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
#endif
#endif /* ACR_BOOTSTRAP_H */ #endif /* ACR_BOOTSTRAP_H */

167
drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.c
View File

@@ -1,167 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/dma.h>
#include <nvgpu/timers.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/firmware.h>
#include <nvgpu/riscv.h>
#include <nvgpu/pmu.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/acr.h>
#include <nvgpu/bug.h>
#include <nvgpu/soc.h>
#include <nvgpu/io.h>
#include "common/acr/acr_bootstrap.h"
#include "common/acr/acr_priv.h"
#define RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS 10000 /*in msec */
#define RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS 100 /*in msec */
static void ga10b_riscv_release_firmware(struct gk20a *g, struct nvgpu_acr *acr)
{
nvgpu_release_firmware(g, acr->acr_asc.manifest_fw);
nvgpu_release_firmware(g, acr->acr_asc.code_fw);
nvgpu_release_firmware(g, acr->acr_asc.data_fw);
}
static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
{
int err = 0;
acr->manifest_fw = nvgpu_request_firmware(g,
acr->acr_manifest_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->manifest_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_manifest_name, g->name);
return -ENOENT;
}
acr->code_fw = nvgpu_request_firmware(g,
acr->acr_code_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->code_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_code_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
return -ENOENT;
}
acr->data_fw = nvgpu_request_firmware(g,
acr->acr_data_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN);
if (acr->data_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_data_name, g->name);
nvgpu_release_firmware(g, acr->manifest_fw);
nvgpu_release_firmware(g, acr->code_fw);
return -ENOENT;
}
return err;
}
static bool nvgpu_acr_wait_for_riscv_brom_completion(struct nvgpu_falcon *flcn,
signed int timeoutms)
{
u32 reg = 0;
do {
reg = flcn->g->ops.falcon.get_brom_retcode(flcn);
if (flcn->g->ops.falcon.check_brom_passed(reg)) {
break;
}
if (timeoutms <= 0) {
return false;
}
nvgpu_msleep(10);
timeoutms -= 10;
} while (true);
return true;
}
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr)
{
int err = 0;
bool brom_complete = false;
u32 timeout = 0;
u64 acr_sysmem_desc_addr = 0LL;
err = ga10b_load_riscv_acr_ucodes(g, &acr->acr_asc);
if (err !=0) {
nvgpu_err(g, "RISCV ucode loading failed");
return -EINVAL;
}
err = acr->patch_wpr_info_to_ucode(g, acr, &acr->acr_asc, false);
if (err != 0) {
nvgpu_err(g, "RISCV ucode patch wpr info failed");
return err;
}
acr_sysmem_desc_addr = nvgpu_mem_get_addr(g,
&acr->acr_asc.acr_falcon2_sysmem_desc);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
nvgpu_riscv_hs_ucode_load_bootstrap(acr->acr_asc.acr_flcn,
acr->acr_asc.manifest_fw,
acr->acr_asc.code_fw,
acr->acr_asc.data_fw,
acr_sysmem_desc_addr);
if (nvgpu_platform_is_silicon(g)) {
timeout = RISCV_BR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = RISCV_BR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
brom_complete = nvgpu_acr_wait_for_riscv_brom_completion(
acr->acr_asc.acr_flcn, timeout);
nvgpu_riscv_dump_brom_stats(acr->acr_asc.acr_flcn);
if (brom_complete == false) {
nvgpu_err(g, "RISCV BROM timed out, limit: %d ms", timeout);
err = -ETIMEDOUT;
} else {
nvgpu_info(g, "RISCV BROM passed");
}
/* wait for complete & halt */
if (nvgpu_platform_is_silicon(g)) {
timeout = ACR_COMPLETION_TIMEOUT_SILICON_MS;
} else {
timeout = ACR_COMPLETION_TIMEOUT_NON_SILICON_MS;
}
err = nvgpu_acr_wait_for_completion(g, &acr->acr_asc, timeout);
ga10b_riscv_release_firmware(g, acr);
return err;
}

32
drivers/gpu/nvgpu/common/acr/nvgpu_next_acr_bootstrap.h
View File

@@ -1,32 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ACR_BOOTSTRAP_H
#define NVGPU_NEXT_ACR_BOOTSTRAP_H
struct gk20a;
struct nvgpu_acr;
struct hs_acr;
int nvgpu_acr_bootstrap_hs_ucode_riscv(struct gk20a *g, struct nvgpu_acr *acr);
#endif /* NVGPU_NEXT_ACR_BOOTSTRAP_H */

69
drivers/gpu/nvgpu/common/cic/cic.c
View File

@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/kmem.h> #include <nvgpu/kmem.h>
#include <nvgpu/lock.h>
#include <nvgpu/log.h> #include <nvgpu/log.h>
#include <nvgpu/cic.h> #include <nvgpu/cic.h>
#include <nvgpu/nvgpu_err_info.h> #include <nvgpu/nvgpu_err_info.h>
@@ -159,3 +160,71 @@ int nvgpu_cic_get_num_hw_modules(struct gk20a *g)
return g->cic->num_hw_modules; return g->cic->num_hw_modules;
} }
#if defined(CONFIG_NVGPU_NON_FUSA)
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}
#endif

92
drivers/gpu/nvgpu/common/cic/nvgpu_next_cic.c
View File

@@ -1,92 +0,0 @@
/*
*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/lock.h>
#include <nvgpu/cic.h>
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= NVGPU_CIC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= NVGPU_CIC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_cic_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}

24
drivers/gpu/nvgpu/common/fb/fb.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -39,3 +39,25 @@ int nvgpu_init_fb_support(struct gk20a *g)
} }
return 0; return 0;
} }
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_fb_vab_init_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.init != NULL) {
err = g->ops.fb.vab.init(g);
}
return err;
}
int nvgpu_fb_vab_teardown_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.teardown != NULL) {
err = g->ops.fb.vab.teardown(g);
}
return err;
}
#endif

44
drivers/gpu/nvgpu/common/fb/nvgpu_next_fb.c
View File

@@ -1,44 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/fb.h>
int nvgpu_fb_vab_init_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.init != NULL) {
err = g->ops.fb.vab.init(g);
}
return err;
}
int nvgpu_fb_vab_teardown_hal(struct gk20a *g)
{
int err = 0;
if (g->ops.fb.vab.teardown != NULL) {
err = g->ops.fb.vab.teardown(g);
}
return err;
}

55
drivers/gpu/nvgpu/common/fifo/engines.c
View File

@@ -706,6 +706,61 @@ u32 nvgpu_engine_get_mask_on_id(struct gk20a *g, u32 id, bool is_tsg)
return engines; return engines;
} }
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev)
{
struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
/*
* Currently due to the nature of the nvgpu_next repo, this will still
* be called even on non-ga10b systems. Eventually this code will fold into
* the nvgpu-linux repo, at which point this logic will be present in
* nvgpu_engine_init_one_dev().
*
* In any event, the purpose of this is to make sure we _don't_ execute
* this code pre-ga10b. We can check for HALs that only exist on ga10x to
* short circuit.
*/
if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
return 0;
}
/*
* Init PBDMA info for this device; needs FIFO to be alive to do this.
* SW expects at least pbdma instance0 to be valid.
*
* See JIRA NVGPU-4980 for multiple pbdma support.
*/
g->ops.runlist.get_pbdma_info(g,
dev->next.rl_pri_base,
&dev_rw->next.pbdma_info);
if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
NVGPU_INVALID_PBDMA_ID) {
nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
dev->engine_id);
return -EINVAL;
}
dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u",
dev->inst_id, dev->runlist_id, dev->fault_id);
nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u",
dev->intr_id, dev->reset_id);
nvgpu_log(g, gpu_dbg_device, " engine_type %u",
dev->type);
nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x",
dev->reset_id, dev->next.rleng_id);
nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x",
dev->next.rl_pri_base);
return 0;
}
#endif
static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f, static int nvgpu_engine_init_one_dev(struct nvgpu_fifo *f,
const struct nvgpu_device *dev) const struct nvgpu_device *dev)
{ {

79
drivers/gpu/nvgpu/common/fifo/nvgpu_next_engines.c
View File

@@ -1,79 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/device.h>
#include <nvgpu/engines.h>
#include <nvgpu/runlist.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h>
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev)
{
struct nvgpu_device *dev_rw = (struct nvgpu_device *)dev;
/*
* Currently due to the nature of the nvgpu_next repo, this will still
* be called even on non-ga10b systems. Eventually this code will fold into
* the nvgpu-linux repo, at which point this logic will be present in
* nvgpu_engine_init_one_dev().
*
* In any event, the purpose of this is to make sure we _don't_ execute
* this code pre-ga10b. We can check for HALs that only exist on ga10x to
* short circuit.
*/
if (g->ops.runlist.get_engine_id_from_rleng_id == NULL) {
return 0;
}
/*
* Init PBDMA info for this device; needs FIFO to be alive to do this.
* SW expects at least pbdma instance0 to be valid.
*
* See JIRA NVGPU-4980 for multiple pbdma support.
*/
g->ops.runlist.get_pbdma_info(g,
dev->next.rl_pri_base,
&dev_rw->next.pbdma_info);
if (dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0] ==
NVGPU_INVALID_PBDMA_ID) {
nvgpu_err(g, "busted pbdma info: no pbdma for engine id:%d",
dev->engine_id);
return -EINVAL;
}
dev_rw->pbdma_id = dev->next.pbdma_info.pbdma_id[ENGINE_PBDMA_INSTANCE0];
nvgpu_log(g, gpu_dbg_device, "Parsed engine: ID: %u", dev->engine_id);
nvgpu_log(g, gpu_dbg_device, " inst_id %u, runlist_id: %u, fault id %u",
dev->inst_id, dev->runlist_id, dev->fault_id);
nvgpu_log(g, gpu_dbg_device, " intr_id %u, reset_id %u",
dev->intr_id, dev->reset_id);
nvgpu_log(g, gpu_dbg_device, " engine_type %u",
dev->type);
nvgpu_log(g, gpu_dbg_device, " reset_id 0x%08x, rleng_id 0x%x",
dev->reset_id, dev->next.rleng_id);
nvgpu_log(g, gpu_dbg_device, " runlist_pri_base 0x%x",
dev->next.rl_pri_base);
return 0;
}

113
drivers/gpu/nvgpu/common/fifo/nvgpu_next_runlist.c
View File

@@ -1,113 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/engines.h>
#include <nvgpu/device.h>
#include <nvgpu/runlist.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/gk20a.h>
static void nvgpu_runlist_init_engine_info(struct gk20a *g,
struct nvgpu_runlist *runlist,
const struct nvgpu_device *dev)
{
u32 i = 0U;
/*
* runlist_pri_base, chram_bar0_offset and pbdma_info
* will get over-written with same info, if multiple engines
* are present on same runlist. Required optimization will be
* done as part of JIRA NVGPU-4980
*/
runlist->nvgpu_next.runlist_pri_base =
dev->next.rl_pri_base;
runlist->nvgpu_next.chram_bar0_offset =
g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x",
runlist->id, runlist->nvgpu_next.runlist_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x",
runlist->id, runlist->nvgpu_next.chram_bar0_offset);
runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info;
for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
nvgpu_log(g, gpu_dbg_info,
"runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x",
runlist->id, i,
runlist->nvgpu_next.pbdma_info->pbdma_id[i], i,
runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]);
}
runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev;
}
static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
struct nvgpu_runlist *runlist)
{
u32 pbdma_mask = 0U;
u32 i;
u32 pbdma_id;
nvgpu_assert(runlist != NULL);
for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i];
if (pbdma_id != NVGPU_INVALID_PBDMA_ID)
pbdma_mask |= BIT32(pbdma_id);
}
return pbdma_mask;
}
void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
{
struct nvgpu_runlist *runlist;
const struct nvgpu_device *dev;
u32 i, j;
nvgpu_log_fn(g, " ");
if (g->is_virtual) {
return;
}
for (i = 0U; i < f->num_runlists; i++) {
runlist = &f->active_runlists[i];
nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i);
for (j = 0U; j < f->num_engines; j++) {
dev = f->active_engines[j];
if (dev->runlist_id == runlist->id) {
runlist->eng_bitmask |= BIT32(dev->engine_id);
nvgpu_runlist_init_engine_info(g, runlist, dev);
}
}
runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist);
nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask);
nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
}
nvgpu_log_fn(g, "done");
}

90
drivers/gpu/nvgpu/common/fifo/runlist.c
View File

@@ -26,6 +26,7 @@
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/device.h> #include <nvgpu/device.h>
#include <nvgpu/runlist.h> #include <nvgpu/runlist.h>
#include <nvgpu/pbdma.h>
#include <nvgpu/ptimer.h> #include <nvgpu/ptimer.h>
#include <nvgpu/bug.h> #include <nvgpu/bug.h>
#include <nvgpu/dma.h> #include <nvgpu/dma.h>
@@ -912,3 +913,92 @@ void nvgpu_runlist_unlock_runlists(struct gk20a *g, u32 runlists_mask)
} }
} }
} }
#if defined(CONFIG_NVGPU_NON_FUSA)
static void nvgpu_runlist_init_engine_info(struct gk20a *g,
struct nvgpu_runlist *runlist,
const struct nvgpu_device *dev)
{
u32 i = 0U;
/*
* runlist_pri_base, chram_bar0_offset and pbdma_info
* will get over-written with same info, if multiple engines
* are present on same runlist. Required optimization will be
* done as part of JIRA NVGPU-4980
*/
runlist->nvgpu_next.runlist_pri_base =
dev->next.rl_pri_base;
runlist->nvgpu_next.chram_bar0_offset =
g->ops.runlist.get_chram_bar0_offset(g, dev->next.rl_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: runlist_pri_base 0x%x",
runlist->id, runlist->nvgpu_next.runlist_pri_base);
nvgpu_log(g, gpu_dbg_info, "runlist[%d]: chram_bar0_offset 0x%x",
runlist->id, runlist->nvgpu_next.chram_bar0_offset);
runlist->nvgpu_next.pbdma_info = &dev->next.pbdma_info;
for (i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
nvgpu_log(g, gpu_dbg_info,
"runlist[%d]: pbdma_id[%d] %d pbdma_pri_base[%d] 0x%x",
runlist->id, i,
runlist->nvgpu_next.pbdma_info->pbdma_id[i], i,
runlist->nvgpu_next.pbdma_info->pbdma_pri_base[i]);
}
runlist->nvgpu_next.rl_dev_list[dev->next.rleng_id] = dev;
}
static u32 nvgpu_runlist_get_pbdma_mask(struct gk20a *g,
struct nvgpu_runlist *runlist)
{
u32 pbdma_mask = 0U;
u32 i;
u32 pbdma_id;
nvgpu_assert(runlist != NULL);
for ( i = 0U; i < PBDMA_PER_RUNLIST_SIZE; i++) {
pbdma_id = runlist->nvgpu_next.pbdma_info->pbdma_id[i];
if (pbdma_id != NVGPU_INVALID_PBDMA_ID)
pbdma_mask |= BIT32(pbdma_id);
}
return pbdma_mask;
}
void nvgpu_next_runlist_init_enginfo(struct gk20a *g, struct nvgpu_fifo *f)
{
struct nvgpu_runlist *runlist;
const struct nvgpu_device *dev;
u32 i, j;
nvgpu_log_fn(g, " ");
if (g->is_virtual) {
return;
}
for (i = 0U; i < f->num_runlists; i++) {
runlist = &f->active_runlists[i];
nvgpu_log(g, gpu_dbg_info, "Configuring runlist %u (%u)", runlist->id, i);
for (j = 0U; j < f->num_engines; j++) {
dev = f->active_engines[j];
if (dev->runlist_id == runlist->id) {
runlist->eng_bitmask |= BIT32(dev->engine_id);
nvgpu_runlist_init_engine_info(g, runlist, dev);
}
}
runlist->pbdma_bitmask = nvgpu_runlist_get_pbdma_mask(g, runlist);
nvgpu_log(g, gpu_dbg_info, " Active engine bitmask: 0x%x", runlist->eng_bitmask);
nvgpu_log(g, gpu_dbg_info, " PBDMA bitmask: 0x%x", runlist->pbdma_bitmask);
}
nvgpu_log_fn(g, "done");
}
#endif

32
drivers/gpu/nvgpu/common/gr/fs_state.c
View File

@@ -194,3 +194,35 @@ int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config)
return err; return err;
} }
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 tpc_index, gpc_index;
u32 sm_id = 0;
u32 num_sm;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
err = g->ops.gr.config.init_sm_id_table(g, config);
if (err != 0) {
return err;
}
num_sm = nvgpu_gr_config_get_no_of_sm(config);
nvgpu_assert(num_sm > 0U);
for (sm_id = 0; sm_id < num_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(config, sm_id);
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
config, NULL, false);
}
return err;
}
#endif

60
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -561,8 +561,8 @@ static int gr_init_prepare_hw_impl(struct gk20a *g)
} }
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(g); nvgpu_gr_init_reset_enable_hw_non_ctx_local(g);
nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(g); nvgpu_gr_init_reset_enable_hw_non_ctx_global(g);
#endif #endif
nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes"); nvgpu_log_info(g, "end: netlist: sw_non_ctx_load: register writes");
@@ -1200,3 +1200,59 @@ u32 nvgpu_gr_get_tpc_num(struct gk20a *g, u32 addr)
} }
return 0; return 0;
} }
#ifdef CONFIG_NVGPU_NON_FUSA
void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr,
sw_non_ctx_local_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr,
sw_non_ctx_local_gfx_load->l[i].value);
}
}
#endif
return;
}
void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr,
sw_non_ctx_global_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr,
sw_non_ctx_global_gfx_load->l[i].value);
}
}
#endif
return;
}
#endif

57
drivers/gpu/nvgpu/common/gr/nvgpu_next_fs_state.c
View File

@@ -1,57 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/nvgpu_next_fs_state.h>
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config)
{
u32 tpc_index, gpc_index;
u32 sm_id = 0;
u32 num_sm;
int err = 0;
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gr, " ");
err = g->ops.gr.config.init_sm_id_table(g, config);
if (err != 0) {
return err;
}
num_sm = nvgpu_gr_config_get_no_of_sm(config);
nvgpu_assert(num_sm > 0U);
for (sm_id = 0; sm_id < num_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(config, sm_id);
tpc_index = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
gpc_index = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
g->ops.gr.init.sm_id_numbering(g, gpc_index, tpc_index, sm_id,
config, NULL, false);
}
return err;
}

81
drivers/gpu/nvgpu/common/gr/nvgpu_next_gr.c
View File

@@ -1,81 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/netlist.h>
#include <nvgpu/io.h>
#include <nvgpu/gr/nvgpu_next_gr.h>
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_local_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_compute_load->l[i].addr,
sw_non_ctx_local_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_local_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_local_gfx_load->l[i].addr,
sw_non_ctx_local_gfx_load->l[i].value);
}
}
#endif
return;
}
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g)
{
u32 i = 0U;
struct netlist_av_list *sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
#endif
for (i = 0U; i < sw_non_ctx_global_compute_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_compute_load->l[i].addr,
sw_non_ctx_global_compute_load->l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
for (i = 0U; i < sw_non_ctx_global_gfx_load->count; i++) {
nvgpu_writel(g, sw_non_ctx_global_gfx_load->l[i].addr,
sw_non_ctx_global_gfx_load->l[i].value);
}
}
#endif
return;
}

92
drivers/gpu/nvgpu/common/mc/nvgpu_next_mc.c
View File

@@ -1,92 +0,0 @@
/*
*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/lock.h>
#include <nvgpu/mc.h>
void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= MC_INTR_VECTORID_SIZE_MAX);
nvgpu_log(g, gpu_dbg_intr, "UNIT=%d, nvecs=%d", unit, num_entries);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
nvgpu_log(g, gpu_dbg_intr, " vec[%d] = %d", i,
*(vectorid + i));
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
if (unit >= MC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
return info_valid;
}
bool nvgpu_mc_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask)
{
if (unit >= MC_INTR_UNIT_MAX) {
nvgpu_err(g, "invalid unit(%d)", unit);
return false;
}
if (nvgpu_mc_intr_is_unit_info_valid(g, unit) != true) {
if (g->ops.mc.intr_get_unit_info(g, unit) != true) {
nvgpu_err(g, "failed to fetch info for unit(%d)", unit);
return false;
}
}
*subtree = g->mc.nvgpu_next.intr_unit_info[unit].subtree;
*subtree_mask = g->mc.nvgpu_next.intr_unit_info[unit].subtree_mask;
nvgpu_log(g, gpu_dbg_intr, "subtree(%d) subtree_mask(%llx)",
*subtree, *subtree_mask);
return true;
}

332
drivers/gpu/nvgpu/common/netlist/netlist.c
View File

@@ -31,9 +31,6 @@
#include <nvgpu/netlist.h> #include <nvgpu/netlist.h>
#include <nvgpu/string.h> #include <nvgpu/string.h>
#include <nvgpu/static_analysis.h> #include <nvgpu/static_analysis.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "nvgpu/nvgpu_next_netlist.h"
#endif
#include "netlist_priv.h" #include "netlist_priv.h"
#include "netlist_defs.h" #include "netlist_defs.h"
@@ -1074,4 +1071,333 @@ void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index)
{ {
g->netlist_vars->regs_base_index = index; g->netlist_vars->regs_base_index = index;
} }
#ifdef CONFIG_NVGPU_DEBUGGER
bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch (region_id) {
case NETLIST_REGIONID_CTXREG_SYS_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_compute);
break;
case NETLIST_REGIONID_CTXREG_GPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute);
break;
case NETLIST_REGIONID_CTXREG_TPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute);
break;
case NETLIST_REGIONID_CTXREG_PPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute);
break;
case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute);
break;
case NETLIST_REGIONID_CTXREG_LTS_BC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_bc);
break;
case NETLIST_REGIONID_CTXREG_LTS_UC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_uc);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_CTXREG_SYS_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx);
break;
case NETLIST_REGIONID_CTXREG_GPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_TPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_PPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx);
break;
case NETLIST_REGIONID_CTXREG_ETPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch(region_id) {
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l);
#ifdef CONFIG_NVGPU_GRAPHICS
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx;
}
u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
return count;
}
void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g)
{
nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d",
nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load;
}
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load;
}
#endif /* CONFIG_NVGPU_GRAPHICS */
#endif #endif

55
drivers/gpu/nvgpu/common/netlist/netlist_priv.h
View File

@@ -25,10 +25,6 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "common/netlist/nvgpu_next_netlist_priv.h"
#endif
struct netlist_u32_list; struct netlist_u32_list;
struct netlist_av_list; struct netlist_av_list;
struct netlist_av64_list; struct netlist_av64_list;
@@ -78,10 +74,30 @@ struct netlist_aiv_list;
#define NETLIST_REGIONID_SW_BUNDLE64_INIT 34 #define NETLIST_REGIONID_SW_BUNDLE64_INIT 34
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_NVPERF_PMCAU 35 #define NETLIST_REGIONID_NVPERF_PMCAU 35
#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36
#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38
#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40
#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42
#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_CTXREG_SYS_GFX 37
#define NETLIST_REGIONID_CTXREG_GPC_GFX 39
#define NETLIST_REGIONID_CTXREG_TPC_GFX 41
#define NETLIST_REGIONID_CTXREG_PPC_GFX 43
#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45
#endif /* CONFIG_NVGPU_GRAPHICS */
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51
#endif /* CONFIG_NVGPU_GRAPHICS */
#define NETLIST_REGIONID_NVPERF_SYS_CONTROL 52 #define NETLIST_REGIONID_NVPERF_SYS_CONTROL 52
#define NETLIST_REGIONID_NVPERF_FBP_CONTROL 53 #define NETLIST_REGIONID_NVPERF_FBP_CONTROL 53
#define NETLIST_REGIONID_NVPERF_GPC_CONTROL 54 #define NETLIST_REGIONID_NVPERF_GPC_CONTROL 54
#define NETLIST_REGIONID_NVPERF_PMA_CONTROL 55 #define NETLIST_REGIONID_NVPERF_PMA_CONTROL 55
#define NETLIST_REGIONID_CTXREG_LTS_BC 57
#define NETLIST_REGIONID_CTXREG_LTS_UC 58
#endif #endif
struct netlist_region { struct netlist_region {
@@ -107,6 +123,37 @@ struct netlist_gr_ucode {
} gpccs, fecs; } gpccs, fecs;
}; };
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
struct nvgpu_next_netlist_vars {
struct netlist_av_list sw_non_ctx_local_compute_load;
struct netlist_av_list sw_non_ctx_global_compute_load;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list sw_non_ctx_local_gfx_load;
struct netlist_av_list sw_non_ctx_global_gfx_load;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#ifdef CONFIG_NVGPU_DEBUGGER
struct nvgpu_next_ctxsw_regs {
struct netlist_aiv_list sys_compute;
struct netlist_aiv_list gpc_compute;
struct netlist_aiv_list tpc_compute;
struct netlist_aiv_list ppc_compute;
struct netlist_aiv_list etpc_compute;
struct netlist_aiv_list lts_bc;
struct netlist_aiv_list lts_uc;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_aiv_list sys_gfx;
struct netlist_aiv_list gpc_gfx;
struct netlist_aiv_list tpc_gfx;
struct netlist_aiv_list ppc_gfx;
struct netlist_aiv_list etpc_gfx;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
struct nvgpu_netlist_vars { struct nvgpu_netlist_vars {
bool dynamic; bool dynamic;

383
drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist.c
View File

@@ -1,383 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/string.h>
#include <nvgpu/netlist.h>
#include "common/netlist/netlist_priv.h"
/* Copied from common/netlist/netlist.c */
static int nvgpu_netlist_alloc_load_av_list(struct gk20a *g, u8 *src, u32 len,
struct netlist_av_list *av_list)
{
av_list->count = len / U32(sizeof(struct netlist_av));
if (nvgpu_netlist_alloc_av_list(g, av_list) == NULL) {
return -ENOMEM;
}
nvgpu_memcpy((u8 *)av_list->l, src, len);
return 0;
}
/* Copied from common/netlist/netlist.c */
static int nvgpu_netlist_alloc_load_aiv_list(struct gk20a *g, u8 *src, u32 len,
struct netlist_aiv_list *aiv_list)
{
aiv_list->count = len / U32(sizeof(struct netlist_aiv));
if (nvgpu_netlist_alloc_aiv_list(g, aiv_list) == NULL) {
return -ENOMEM;
}
nvgpu_memcpy((u8 *)aiv_list->l, src, len);
return 0;
}
#ifdef CONFIG_NVGPU_DEBUGGER
bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch (region_id) {
case NETLIST_REGIONID_CTXREG_SYS_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_compute);
break;
case NETLIST_REGIONID_CTXREG_GPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute);
break;
case NETLIST_REGIONID_CTXREG_TPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute);
break;
case NETLIST_REGIONID_CTXREG_PPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute);
break;
case NETLIST_REGIONID_CTXREG_ETPC_COMPUTE:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_COMPUTE");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute);
break;
case NETLIST_REGIONID_CTXREG_LTS_BC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_BC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_bc);
break;
case NETLIST_REGIONID_CTXREG_LTS_UC:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_LTS_UC");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.lts_uc);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_CTXREG_SYS_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_SYS_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx);
break;
case NETLIST_REGIONID_CTXREG_GPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_GPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_TPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_TPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx);
break;
case NETLIST_REGIONID_CTXREG_PPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_PPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx);
break;
case NETLIST_REGIONID_CTXREG_ETPC_GFX:
nvgpu_log_info(g, "NETLIST_REGIONID_CTXREG_ETPC_GFX");
err = nvgpu_netlist_alloc_load_aiv_list(g, src, size,
&netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_bc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.lts_uc.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx.l);
nvgpu_kfree(g, netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx.l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code)
{
int err = 0;
bool handled = true;
switch(region_id) {
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load);
break;
default:
handled = false;
break;
}
if ((handled == false) && (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG))) {
handled = true;
switch (region_id) {
#ifdef CONFIG_NVGPU_GRAPHICS
case NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load);
break;
case NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD:
nvgpu_log_info(g, "NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD");
err = nvgpu_netlist_alloc_load_av_list(g, src, size,
&netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load);
break;
#endif
default:
handled = false;
break;
}
}
*err_code = err;
return handled;
}
void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g)
{
struct nvgpu_netlist_vars *netlist_vars = g->netlist_vars;
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load.l);
#ifdef CONFIG_NVGPU_GRAPHICS
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load.l);
nvgpu_kfree(g, netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load.l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_compute;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.lts_bc;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.sys_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.gpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.tpc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.ppc_gfx;
}
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
struct gk20a *g)
{
return &g->netlist_vars->ctxsw_regs.nvgpu_next.etpc_gfx;
}
u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
return count;
}
u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g)
{
u32 count = nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count;
count = nvgpu_safe_add_u32(count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
return count;
}
void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g)
{
nvgpu_log_info(g, "GRCTX_REG_LIST_SYS_(COMPUTE/GRAPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_GPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_TPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_PPC_(COMPUTE/GRAHPICS)_COUNT :%d %d",
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_ETPC_(COMPUTE/GRAPHICS)_COUNT :%d %d",
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g)->count,
nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g)->count);
nvgpu_log_info(g, "GRCTX_REG_LIST_LTS_BC_COUNT :%d",
nvgpu_next_netlist_get_lts_ctxsw_regs(g)->count);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_compute_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_compute_load;
}
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_local_gfx_load;
}
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
struct gk20a *g)
{
return &g->netlist_vars->nvgpu_next.sw_non_ctx_global_gfx_load;
}
#endif /* CONFIG_NVGPU_GRAPHICS */

92
drivers/gpu/nvgpu/common/netlist/nvgpu_next_netlist_priv.h
View File

@@ -1,92 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_NETLIST_PRIV_H
#define NVGPU_NEXT_NETLIST_PRIV_H
/**
* @file
*
* Declare netlist_vars specific struct and defines.
*/
#include <nvgpu/types.h>
struct gk20a;
struct netlist_av_list;
struct netlist_aiv_list;
#ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_CTXREG_SYS_COMPUTE 36
#define NETLIST_REGIONID_CTXREG_GPC_COMPUTE 38
#define NETLIST_REGIONID_CTXREG_TPC_COMPUTE 40
#define NETLIST_REGIONID_CTXREG_PPC_COMPUTE 42
#define NETLIST_REGIONID_CTXREG_ETPC_COMPUTE 44
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_CTXREG_SYS_GFX 37
#define NETLIST_REGIONID_CTXREG_GPC_GFX 39
#define NETLIST_REGIONID_CTXREG_TPC_GFX 41
#define NETLIST_REGIONID_CTXREG_PPC_GFX 43
#define NETLIST_REGIONID_CTXREG_ETPC_GFX 45
#endif /* CONFIG_NVGPU_GRAPHICS */
#endif /* CONFIG_NVGPU_DEBUGGER */
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_COMPUTE_LOAD 48
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_COMPUTE_LOAD 50
#ifdef CONFIG_NVGPU_GRAPHICS
#define NETLIST_REGIONID_SW_NON_CTX_LOCAL_GFX_LOAD 49
#define NETLIST_REGIONID_SW_NON_CTX_GLOBAL_GFX_LOAD 51
#endif /* CONFIG_NVGPU_GRAPHICS */
#ifdef CONFIG_NVGPU_DEBUGGER
#define NETLIST_REGIONID_CTXREG_LTS_BC 57
#define NETLIST_REGIONID_CTXREG_LTS_UC 58
#endif /* CONFIG_DEBUGGER */
struct nvgpu_next_netlist_vars {
struct netlist_av_list sw_non_ctx_local_compute_load;
struct netlist_av_list sw_non_ctx_global_compute_load;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list sw_non_ctx_local_gfx_load;
struct netlist_av_list sw_non_ctx_global_gfx_load;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#ifdef CONFIG_NVGPU_DEBUGGER
struct nvgpu_next_ctxsw_regs {
struct netlist_aiv_list sys_compute;
struct netlist_aiv_list gpc_compute;
struct netlist_aiv_list tpc_compute;
struct netlist_aiv_list ppc_compute;
struct netlist_aiv_list etpc_compute;
struct netlist_aiv_list lts_bc;
struct netlist_aiv_list lts_uc;
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_aiv_list sys_gfx;
struct netlist_aiv_list gpc_gfx;
struct netlist_aiv_list tpc_gfx;
struct netlist_aiv_list ppc_gfx;
struct netlist_aiv_list etpc_gfx;
#endif /* CONFIG_NVGPU_GRAPHICS */
};
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* NVGPU_NEXT_NETLIST_PRIV_H */

38
drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.c
View File

@@ -1,38 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include "nvgpu_next_profiler.h"
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g)
{
if (g->ops.perf.reset_hs_streaming_credits != NULL) {
/* Reset high speed streaming credits to 0. */
g->ops.perf.reset_hs_streaming_credits(g);
}
if (g->ops.perf.enable_hs_streaming != NULL) {
/* Disable high speed streaming */
g->ops.perf.enable_hs_streaming(g, false);
}
}

28
drivers/gpu/nvgpu/common/profiler/nvgpu_next_profiler.h
View File

@@ -1,28 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_PROFILER_H
#define NVGPU_NEXT_PROFILER_H
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g);
#endif /* NVGPU_NEXT_PROFILER_H */

15
drivers/gpu/nvgpu/common/profiler/profiler.c
View File

@@ -1157,3 +1157,18 @@ bool nvgpu_profiler_validate_regops_allowlist(struct nvgpu_profiler_object *prof
offset = offset & (stride - 1U); offset = offset & (stride - 1U);
return allowlist_offset_search(g, offset_allowlist, count, offset); return allowlist_offset_search(g, offset_allowlist, count, offset);
} }
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void nvgpu_next_profiler_hs_stream_quiesce(struct gk20a *g)
{
if (g->ops.perf.reset_hs_streaming_credits != NULL) {
/* Reset high speed streaming credits to 0. */
g->ops.perf.reset_hs_streaming_credits(g);
}
if (g->ops.perf.enable_hs_streaming != NULL) {
/* Disable high speed streaming */
g->ops.perf.enable_hs_streaming(g, false);
}
}
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */

61
drivers/gpu/nvgpu/common/sim/nvgpu_next_sim.c
View File

@@ -1,61 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/utils.h>
#include <nvgpu/hw_sim.h>
#include <nvgpu/sim.h>
#include <nvgpu/string.h>
static void nvgpu_next_sim_esc_readl(struct gk20a *g,
const char *path, u32 index, u32 *data)
{
int err;
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(
nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
err = issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
nvgpu_safe_add_u32(data_offset,
sim_escape_read_hdr_size())),
sizeof(u32));
} else {
*data = 0xffffffff;
WARN(1, "issue_rpc_and_wait failed err=%d", err);
}
}
void nvgpu_next_init_sim_support(struct gk20a *g)
{
if (g->sim) {
g->sim->esc_readl = nvgpu_next_sim_esc_readl;
}
}

445
drivers/gpu/nvgpu/common/sim/nvgpu_next_sim_netlist.c
View File

@@ -1,445 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/gk20a.h>
#include <nvgpu/sim.h>
#include <nvgpu/netlist.h>
#include "nvgpu/nvgpu_next_sim.h"
int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g)
{
u32 i;
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_local_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_compute_load failed");
}
for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_local_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_global_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_compute_load failed");
}
for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_global_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
return 0;
}
void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g)
{
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_compute_load->l);
nvgpu_kfree(g, sw_non_ctx_global_compute_load->l);
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l);
nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g)
{
u32 i;
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0,
&sys_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_compute_ctxsw_regs failed");
}
for (i = 0; i < sys_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE",
i, &l[i].value);
}
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0,
&gpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_compute_ctxsw_regs failed");
}
for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE",
i, &l[i].value);
}
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0,
&tpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_compute_ctxsw_regs failed");
}
for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE",
i, &l[i].value);
}
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0,
&ppc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_compute_ctxsw_regs failed");
}
for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE",
i, &l[i].value);
}
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0,
&etpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_compute_ctxsw_regs failed");
}
for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE",
i, &l[i].value);
}
/*
* TODO: https://jirasw.nvidia.com/browse/NVGPU-5761
*/
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0,
&lts_ctxsw_regs->count);
nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) {
nvgpu_info(g, "lts_ctxsw_regs failed");
}
for (i = 0U; i < lts_ctxsw_regs->count; i++) {
struct netlist_aiv *l = lts_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE",
i, &l[i].value);
nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr,
l[i].index, l[i].value);
}
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0,
&sys_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_gfx_ctxsw_regs failed");
}
for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE",
i, &l[i].value);
}
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0,
&gpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE",
i, &l[i].value);
}
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0,
&tpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE",
i, &l[i].value);
}
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0,
&ppc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_gfx_ctxsw_regs failed");
}
for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE",
i, &l[i].value);
}
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0,
&etpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE",
i, &l[i].value);
}
return 0;
}
void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g)
{
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
nvgpu_kfree(g, sys_compute_ctxsw_regs->l);
nvgpu_kfree(g, gpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, tpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, ppc_compute_ctxsw_regs->l);
nvgpu_kfree(g, etpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, lts_ctxsw_regs->l);
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
nvgpu_kfree(g, sys_gfx_ctxsw_regs->l);
nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */

37
drivers/gpu/nvgpu/common/sim/sim.c
View File

@@ -301,3 +301,40 @@ int nvgpu_init_sim_support(struct gk20a *g)
g->sim->esc_readl = nvgpu_sim_esc_readl; g->sim->esc_readl = nvgpu_sim_esc_readl;
return 0; return 0;
} }
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
static void nvgpu_next_sim_esc_readl(struct gk20a *g,
const char *path, u32 index, u32 *data)
{
int err;
u32 data_offset;
sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
sim_escape_read_hdr_size());
*sim_msg_param(g, 0) = index;
*sim_msg_param(g, 4) = sizeof(u32);
data_offset = round_up(
nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
*sim_msg_param(g, 8) = data_offset;
strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
err = issue_rpc_and_wait(g);
if (err == 0) {
nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
nvgpu_safe_add_u32(data_offset,
sim_escape_read_hdr_size())),
sizeof(u32));
} else {
*data = 0xffffffff;
WARN(1, "issue_rpc_and_wait failed err=%d", err);
}
}
void nvgpu_next_init_sim_support(struct gk20a *g)
{
if (g->sim) {
g->sim->esc_readl = nvgpu_next_sim_esc_readl;
}
}
#endif

424
drivers/gpu/nvgpu/common/sim/sim_netlist.c
View File

@@ -24,9 +24,6 @@
#include <nvgpu/sim.h> #include <nvgpu/sim.h>
#include <nvgpu/netlist.h> #include <nvgpu/netlist.h>
#include <nvgpu/log.h> #include <nvgpu/log.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "nvgpu/nvgpu_next_sim.h"
#endif
int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g) int nvgpu_init_sim_netlist_ctx_vars(struct gk20a *g)
{ {
@@ -818,3 +815,424 @@ fail:
return err; return err;
} }
#if defined(CONFIG_NVGPU_NON_FUSA)
int nvgpu_next_init_sim_netlist_ctx_vars(struct gk20a *g)
{
u32 i;
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_local_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_compute_load failed");
}
for (i = 0; i < sw_non_ctx_local_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_local_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_local_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_local_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_local_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_local_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_LOCAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG_SIZE", 0,
&sw_non_ctx_global_compute_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_compute_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_compute_load failed");
}
for (i = 0; i < sw_non_ctx_global_compute_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_compute_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_COMPUTE_REG:VALUE",
i, &l[i].value);
}
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG_SIZE", 0,
&sw_non_ctx_global_gfx_load->count);
if (nvgpu_netlist_alloc_av_list(g, sw_non_ctx_global_gfx_load) ==
NULL) {
nvgpu_info(g, "sw_non_ctx_global_gfx_load failed");
}
for (i = 0; i < sw_non_ctx_global_gfx_load->count; i++) {
struct netlist_av *l = sw_non_ctx_global_gfx_load->l;
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:REG",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_NONCTXSW_GLOBAL_GRAPHICS_REG:VALUE",
i, &l[i].value);
}
#endif
return 0;
}
void nvgpu_next_init_sim_netlist_ctx_vars_free(struct gk20a *g)
{
struct netlist_av_list *sw_non_ctx_local_compute_load;
struct netlist_av_list *sw_non_ctx_local_gfx_load;
struct netlist_av_list *sw_non_ctx_global_compute_load;
struct netlist_av_list *sw_non_ctx_global_gfx_load;
sw_non_ctx_local_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(g);
sw_non_ctx_global_compute_load =
nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_compute_load->l);
nvgpu_kfree(g, sw_non_ctx_global_compute_load->l);
#ifdef CONFIG_NVGPU_GRAPHICS
sw_non_ctx_local_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(g);
sw_non_ctx_global_gfx_load =
nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(g);
nvgpu_kfree(g, sw_non_ctx_local_gfx_load->l);
nvgpu_kfree(g, sw_non_ctx_global_gfx_load->l);
#endif
}
#ifdef CONFIG_NVGPU_DEBUGGER
int nvgpu_next_init_sim_netlist_ctxsw_regs(struct gk20a *g)
{
u32 i;
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE_COUNT", 0,
&sys_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_compute_ctxsw_regs failed");
}
for (i = 0; i < sys_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COMPUTE:VALUE",
i, &l[i].value);
}
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE_COUNT", 0,
&gpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_compute_ctxsw_regs failed");
}
for (i = 0; i < gpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COMPUTE:VALUE",
i, &l[i].value);
}
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE_COUNT", 0,
&tpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_compute_ctxsw_regs failed");
}
for (i = 0; i < tpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COMPUTE:VALUE",
i, &l[i].value);
}
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE_COUNT", 0,
&ppc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_compute_ctxsw_regs failed");
}
for (i = 0; i < ppc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COMPUTE:VALUE",
i, &l[i].value);
}
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE_COUNT", 0,
&etpc_compute_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_compute_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_compute_ctxsw_regs failed");
}
for (i = 0; i < etpc_compute_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_compute_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COMPUTE:VALUE",
i, &l[i].value);
}
/*
* TODO: https://jirasw.nvidia.com/browse/NVGPU-5761
*/
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC_COUNT", 0,
&lts_ctxsw_regs->count);
nvgpu_log_info(g, "total: %d lts registers", lts_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, lts_ctxsw_regs) == NULL) {
nvgpu_info(g, "lts_ctxsw_regs failed");
}
for (i = 0U; i < lts_ctxsw_regs->count; i++) {
struct netlist_aiv *l = lts_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_LTS_BC:VALUE",
i, &l[i].value);
nvgpu_log_info(g, "entry(%d) a(0x%x) i(%d) v(0x%x)", i, l[i].addr,
l[i].index, l[i].value);
}
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS_COUNT", 0,
&sys_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, sys_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "sys_gfx_ctxsw_regs failed");
}
for (i = 0; i < sys_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = sys_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_GRAPHICS:VALUE",
i, &l[i].value);
}
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS_COUNT", 0,
&gpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, gpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "gpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < gpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = gpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_GRAPHICS:VALUE",
i, &l[i].value);
}
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS_COUNT", 0,
&tpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, tpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "tpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < tpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = tpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_GRAPHICS:VALUE",
i, &l[i].value);
}
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS_COUNT", 0,
&ppc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, ppc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "ppc_gfx_ctxsw_regs failed");
}
for (i = 0; i < ppc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = ppc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_GRAPHICS:VALUE",
i, &l[i].value);
}
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
/* query sizes and counts */
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS_COUNT", 0,
&etpc_gfx_ctxsw_regs->count);
if (nvgpu_netlist_alloc_aiv_list(g, etpc_gfx_ctxsw_regs) == NULL) {
nvgpu_info(g, "etpc_gfx_ctxsw_regs failed");
}
for (i = 0; i < etpc_gfx_ctxsw_regs->count; i++) {
struct netlist_aiv *l = etpc_gfx_ctxsw_regs->l;
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:ADDR",
i, &l[i].addr);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:INDEX",
i, &l[i].index);
g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_GRAPHICS:VALUE",
i, &l[i].value);
}
return 0;
}
void nvgpu_next_init_sim_netlist_ctxsw_regs_free(struct gk20a *g)
{
struct netlist_aiv_list *sys_compute_ctxsw_regs;
struct netlist_aiv_list *gpc_compute_ctxsw_regs;
struct netlist_aiv_list *tpc_compute_ctxsw_regs;
struct netlist_aiv_list *ppc_compute_ctxsw_regs;
struct netlist_aiv_list *etpc_compute_ctxsw_regs;
struct netlist_aiv_list *lts_ctxsw_regs;
struct netlist_aiv_list *sys_gfx_ctxsw_regs;
struct netlist_aiv_list *gpc_gfx_ctxsw_regs;
struct netlist_aiv_list *tpc_gfx_ctxsw_regs;
struct netlist_aiv_list *ppc_gfx_ctxsw_regs;
struct netlist_aiv_list *etpc_gfx_ctxsw_regs;
sys_compute_ctxsw_regs =
nvgpu_next_netlist_get_sys_compute_ctxsw_regs(g);
gpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(g);
tpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(g);
ppc_compute_ctxsw_regs =
nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(g);
etpc_compute_ctxsw_regs =
nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(g);
lts_ctxsw_regs = nvgpu_next_netlist_get_lts_ctxsw_regs(g);
nvgpu_kfree(g, sys_compute_ctxsw_regs->l);
nvgpu_kfree(g, gpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, tpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, ppc_compute_ctxsw_regs->l);
nvgpu_kfree(g, etpc_compute_ctxsw_regs->l);
nvgpu_kfree(g, lts_ctxsw_regs->l);
sys_gfx_ctxsw_regs = nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(g);
gpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(g);
tpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(g);
ppc_gfx_ctxsw_regs = nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(g);
etpc_gfx_ctxsw_regs = nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(g);
nvgpu_kfree(g, sys_gfx_ctxsw_regs->l);
nvgpu_kfree(g, gpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, tpc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, ppc_gfx_ctxsw_regs->l);
nvgpu_kfree(g, etpc_gfx_ctxsw_regs->l);
}
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif

3
drivers/gpu/nvgpu/hal/class/class_ga100.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -21,7 +21,6 @@
*/ */
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/barrier.h> #include <nvgpu/barrier.h>
#include "hal/class/class_ga10b.h" #include "hal/class/class_ga10b.h"

3
drivers/gpu/nvgpu/hal/class/class_ga10b.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2021 NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -21,7 +21,6 @@
*/ */
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/barrier.h> #include <nvgpu/barrier.h>
#include "hal/class/class_tu104.h" #include "hal/class/class_tu104.h"

1
drivers/gpu/nvgpu/hal/gr/gr/gr_ga10b.c
View File

@@ -46,7 +46,6 @@
#include <nvgpu/nvgpu_err.h> #include <nvgpu/nvgpu_err.h>
#include <nvgpu/netlist.h> #include <nvgpu/netlist.h>
#include <nvgpu/gr/obj_ctx.h> #include <nvgpu/gr/obj_ctx.h>
#include <nvgpu/nvgpu_next_litter.h>
#include "gr_ga10b.h" #include "gr_ga10b.h"
#include "hal/gr/gr/gr_gk20a.h" #include "hal/gr/gr/gr_gk20a.h"

3
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga100_fusa.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/io.h> #include <nvgpu/io.h>
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/nvgpu_err.h> #include <nvgpu/nvgpu_err.h>

3
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_ga10b_fusa.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/io.h> #include <nvgpu/io.h>
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/engines.h> #include <nvgpu/engines.h>
#include <nvgpu/nvgpu_err.h> #include <nvgpu/nvgpu_err.h>

1
drivers/gpu/nvgpu/hal/init/hal_ga100_litter.c
View File

@@ -22,7 +22,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/hw/ga100/hw_proj_ga100.h> #include <nvgpu/hw/ga100/hw_proj_ga100.h>

2
drivers/gpu/nvgpu/hal/init/hal_ga10b_litter.c
View File

@@ -22,8 +22,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/class.h> #include <nvgpu/class.h>
#include <nvgpu/nvgpu_next_class.h>
#include <nvgpu/nvgpu_next_litter.h>
#include <nvgpu/hw/ga10b/hw_proj_ga10b.h> #include <nvgpu/hw/ga10b/hw_proj_ga10b.h>

1
drivers/gpu/nvgpu/hal/power_features/cg/ga100_gating_reglist.c
View File

@@ -31,7 +31,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h> #include <nvgpu/fifo.h>
#include <nvgpu/runlist.h> #include <nvgpu/runlist.h>
#include <nvgpu/nvgpu_next_runlist.h>
#include "hal/power_features/cg/gating_reglist.h" #include "hal/power_features/cg/gating_reglist.h"
#include "ga100_gating_reglist.h" #include "ga100_gating_reglist.h"

1
drivers/gpu/nvgpu/hal/power_features/cg/ga10b_gating_reglist.c
View File

@@ -31,7 +31,6 @@
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/fifo.h> #include <nvgpu/fifo.h>
#include <nvgpu/runlist.h> #include <nvgpu/runlist.h>
#include <nvgpu/nvgpu_next_runlist.h>
#include "hal/power_features/cg/gating_reglist.h" #include "hal/power_features/cg/gating_reglist.h"
#include "ga10b_gating_reglist.h" #include "ga10b_gating_reglist.h"

64
drivers/gpu/nvgpu/include/nvgpu/cic.h
View File

@@ -23,10 +23,72 @@
#ifndef NVGPU_CIC_H #ifndef NVGPU_CIC_H
#define NVGPU_CIC_H #define NVGPU_CIC_H
#include <nvgpu/types.h>
#include <nvgpu/static_analysis.h>
#include <nvgpu/log.h> #include <nvgpu/log.h>
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_cic.h" #define U32_BITS 32U
#define DIV_BY_U32_BITS(x) ((x) / U32_BITS)
#define MOD_BY_U32_BITS(x) ((x) % U32_BITS)
#define RESET_ID_TO_REG_IDX(x) DIV_BY_U32_BITS((x))
#define RESET_ID_TO_REG_BIT(x) MOD_BY_U32_BITS((x))
#define RESET_ID_TO_REG_MASK(x) BIT32(RESET_ID_TO_REG_BIT((x)))
#define GPU_VECTOR_TO_LEAF_REG(i) DIV_BY_U32_BITS((i))
#define GPU_VECTOR_TO_LEAF_BIT(i) MOD_BY_U32_BITS((i))
#define GPU_VECTOR_TO_LEAF_MASK(i) (BIT32(GPU_VECTOR_TO_LEAF_BIT(i)))
#define GPU_VECTOR_TO_SUBTREE(i) ((GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
#define GPU_VECTOR_TO_LEAF_SHIFT(i) \
(nvgpu_safe_mult_u32(((GPU_VECTOR_TO_LEAF_REG(i)) % 2U), 32U))
#define HOST2SOC_0_SUBTREE 0U
#define HOST2SOC_1_SUBTREE 1U
#define HOST2SOC_2_SUBTREE 2U
#define HOST2SOC_3_SUBTREE 3U
#define HOST2SOC_NUM_SUBTREE 4U
#define HOST2SOC_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
#define HOST2SOC_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
#define HOST2SOC_SUBTREE_TO_LEAF0(i) \
(nvgpu_safe_mult_u32((i), 2U))
#define HOST2SOC_SUBTREE_TO_LEAF1(i) \
(nvgpu_safe_add_u32((nvgpu_safe_mult_u32((i), 2U)), 1U))
#define STALL_SUBTREE_TOP_IDX 0U
#define STALL_SUBTREE_TOP_BITS \
((BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) | \
(BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) | \
(BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE))))
/**
* These should not contradict NVGPU_CIC_INTR_UNIT_* defines.
*/
#define NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR 10U
#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR 11U
#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR 12U
#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT 13U
#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT 14U
#define NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT 15U
#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 16U
#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1 17U
#define NVGPU_CIC_INTR_UNIT_GR_STALL 18U
#define NVGPU_CIC_INTR_UNIT_CE_STALL 19U
#define NVGPU_CIC_INTR_UNIT_MAX 20U
#define NVGPU_CIC_INTR_VECTORID_SIZE_MAX 32U
#define NVGPU_CIC_INTR_VECTORID_SIZE_ONE 1U
#define RUNLIST_INTR_TREE_0 0U
#define RUNLIST_INTR_TREE_1 1U
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries);
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask);
#endif #endif
struct nvgpu_err_desc; struct nvgpu_err_desc;

12
drivers/gpu/nvgpu/include/nvgpu/class.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -103,6 +103,16 @@
#define TURING_CHANNEL_GPFIFO_A 0xC46FU #define TURING_CHANNEL_GPFIFO_A 0xC46FU
#define TURING_COMPUTE_A 0xC5C0U #define TURING_COMPUTE_A 0xC5C0U
#define TURING_DMA_COPY_A 0xC5B5U #define TURING_DMA_COPY_A 0xC5B5U
#define AMPERE_SMC_PARTITION_REF 0xC637U
#define AMPERE_B 0xC797U
#define AMPERE_A 0xC697U
#define AMPERE_DMA_COPY_A 0xC6B5U
#define AMPERE_DMA_COPY_B 0xC7B5U
#define AMPERE_COMPUTE_A 0xC6C0U
#define AMPERE_COMPUTE_B 0xC7C0U
#define AMPERE_CHANNEL_GPFIFO_A 0xC56FU
#define AMPERE_CHANNEL_GPFIFO_B 0xC76FU
#endif #endif
#endif /* NVGPU_CLASS_H */ #endif /* NVGPU_CLASS_H */

37
drivers/gpu/nvgpu/include/nvgpu/device.h
View File

@@ -31,10 +31,7 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
#include <nvgpu/list.h> #include <nvgpu/list.h>
#include <nvgpu/pbdma.h>
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_device.h"
#endif
struct gk20a; struct gk20a;
@@ -93,6 +90,38 @@ struct gk20a;
#define NVGPU_DEVICE_TOKEN_INIT 0U #define NVGPU_DEVICE_TOKEN_INIT 0U
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
struct nvgpu_device_next {
/**
* True if the device is an method engine behind host.
*/
bool engine;
/**
* Runlist Engine ID; only valid if #engine is true.
*/
u32 rleng_id;
/**
* Runlist PRI base - byte aligned based address. CHRAM offset can
* be computed from this.
*/
u32 rl_pri_base;
/**
* PBDMA info for this device. It may contain multiple PBDMAs as
* there can now be multiple PBDMAs per runlist.
*
* This is in some ways awkward; devices seem to be more directly
* linked to runlists; runlists in turn have PBDMAs. Granted that
* means there's a computable relation between devices and PBDMAs
* it may make sense to not have this link.
*/
struct nvgpu_next_pbdma_info pbdma_info;
};
#endif
/** /**
* Structure definition for storing information for the devices and the engines * Structure definition for storing information for the devices and the engines
* available on the chip. * available on the chip.

18
drivers/gpu/nvgpu/include/nvgpu/ecc.h
View File

@@ -173,7 +173,10 @@ struct nvgpu_ecc {
/** SM icache uncorrected error count. */ /** SM icache uncorrected error count. */
struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count; struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count;
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/gr/nvgpu_next_gr_ecc.h" /** SM RAMS corrected error count. */
struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count;
/** SM RAMS uncorrected error count. */
struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count;
#endif #endif
/** GCC l1.5-cache corrected error count. */ /** GCC l1.5-cache corrected error count. */
@@ -226,7 +229,18 @@ struct nvgpu_ecc {
/** hubmmu fillunit uncorrected error count. */ /** hubmmu fillunit uncorrected error count. */
struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count; struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_err_count;
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_ecc.h" /* Leave extra tab to fit into nvgpu_ecc.fb structure */
struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count;
/** hubmmu l2tlb uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_unique_err_count;
/** hubmmu hubtlb corrected unique error count. */
struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_unique_err_count;
/** hubmmu hubtlb uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_unique_err_count;
/** hubmmu fillunit corrected unique error count. */
struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count;
/** hubmmu fillunit uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count;
#endif #endif
} fb; } fb;

15
drivers/gpu/nvgpu/include/nvgpu/engine_status.h
View File

@@ -23,10 +23,6 @@
#ifndef NVGPU_ENGINE_STATUS_H #ifndef NVGPU_ENGINE_STATUS_H
#define NVGPU_ENGINE_STATUS_H #define NVGPU_ENGINE_STATUS_H
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_engine_status.h"
#endif
/** /**
* @file * @file
* *
@@ -95,13 +91,20 @@ enum nvgpu_engine_status_ctx_status {
NVGPU_CTX_STATUS_CTXSW_SWITCH, NVGPU_CTX_STATUS_CTXSW_SWITCH,
}; };
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_HAL_NON_FUSA)
struct nvgpu_next_engine_status_info {
/** Engine status_1 h/w register's read value. */
u32 reg1_data;
};
#endif
struct nvgpu_engine_status_info { struct nvgpu_engine_status_info {
/** Engine status h/w register's read value. */ /** Engine status h/w register's read value. */
u32 reg_data; u32 reg_data;
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
/* nvgpu next engine status additions */ /* Ampere+ engine status additions */
struct nvgpu_next_engine_status_info nvgpu_next; struct nvgpu_next_engine_status_info nvgpu_next;
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#endif #endif
/** Channel or tsg id that is currently assigned to the engine. */ /** Channel or tsg id that is currently assigned to the engine. */

8
drivers/gpu/nvgpu/include/nvgpu/engines.h
View File

@@ -30,9 +30,15 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct gk20a;
struct nvgpu_device;
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_engines.h" #define ENGINE_PBDMA_INSTANCE0 0U
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

9
drivers/gpu/nvgpu/include/nvgpu/errata.h
View File

@@ -35,7 +35,14 @@ struct gk20a;
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_errata.h" #define ERRATA_FLAGS_NEXT \
/* GA100 */ \
DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"), \
/* GA10B */ \
DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"), \
DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"), \
DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"), \
DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"),
#else #else
#define ERRATA_FLAGS_NEXT #define ERRATA_FLAGS_NEXT
#endif #endif

39
drivers/gpu/nvgpu/include/nvgpu/fb.h
View File

@@ -24,7 +24,44 @@
#define NVGPU_FB_H #define NVGPU_FB_H
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_fb.h" /* VAB track all accesses (read and write) */
#define NVGPU_VAB_MODE_ACCESS BIT32(0U)
/* VAB track only writes (writes and read-modify-writes) */
#define NVGPU_VAB_MODE_DIRTY BIT32(1U)
/* No change to VAB logging with VPR setting requested */
#define NVGPU_VAB_LOGGING_VPR_NONE 0U
/* VAB logging disabled if vpr IN_USE=1, regardless of PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_IN_USE_DISABLED BIT32(0U)
/* VAB logging disabled if vpr PROTECTED_MODE=1, regardless of IN_USE */
#define NVGPU_VAB_LOGGING_VPR_PROTECTED_DISABLED BIT32(1U)
/* VAB logging enabled regardless of IN_USE and PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_ENABLED BIT32(2U)
/* VAB logging disabled regardless of IN_USE and PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_DISABLED BIT32(3U)
struct nvgpu_vab_range_checker {
/*
* in: starting physical address. Must be aligned by
* 1 << (granularity_shift + bitmask_size_shift) where
* bitmask_size_shift is a HW specific constant.
*/
u64 start_phys_addr;
/* in: log2 of coverage granularity per bit */
u8 granularity_shift;
u8 reserved[7];
};
struct nvgpu_vab {
u32 user_num_range_checkers;
struct nvgpu_mem buffer;
};
int nvgpu_fb_vab_init_hal(struct gk20a *g);
int nvgpu_fb_vab_teardown_hal(struct gk20a *g);
#endif #endif
/** /**

38
drivers/gpu/nvgpu/include/nvgpu/fuse.h
View File

@@ -33,7 +33,43 @@ struct gk20a;
#include <nvgpu/errno.h> #include <nvgpu/errno.h>
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_fuse.h" struct nvgpu_fuse_feature_override_ecc {
/** overide_ecc register feature */
/** sm_lrf enable */
bool sm_lrf_enable;
/** sm_lrf override */
bool sm_lrf_override;
/** sm_l1_data enable */
bool sm_l1_data_enable;
/** sm_l1_data overide */
bool sm_l1_data_override;
/** sm_l1_tag enable */
bool sm_l1_tag_enable;
/** sm_l1_tag overide */
bool sm_l1_tag_override;
/** ltc enable */
bool ltc_enable;
/** ltc overide */
bool ltc_override;
/** dram enable */
bool dram_enable;
/** dram overide */
bool dram_override;
/** sm_cbu enable */
bool sm_cbu_enable;
/** sm_cbu overide */
bool sm_cbu_override;
/** override_ecc_1 register feature */
/** sm_l0_icache enable */
bool sm_l0_icache_enable;
/** sm_l0_icache overide */
bool sm_l0_icache_override;
/** sm_l1_icache enable */
bool sm_l1_icache_enable;
/** sm_l1_icache overide */
bool sm_l1_icache_override;
};
#endif #endif
#define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK BIT32(0) #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK BIT32(0)

5
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -267,6 +267,11 @@ struct railgate_stats {
#define GPU_LIT_MAX_RUNLISTS_SUPPORTED 49 #define GPU_LIT_MAX_RUNLISTS_SUPPORTED 49
#define GPU_LIT_NUM_LTC_LTS_SETS 50 #define GPU_LIT_NUM_LTC_LTS_SETS 50
#define GPU_LIT_NUM_LTC_LTS_WAYS 51 #define GPU_LIT_NUM_LTC_LTS_WAYS 51
#define GPU_LIT_ROP_IN_GPC_BASE 52
#define GPU_LIT_ROP_IN_GPC_SHARED_BASE 53
#define GPU_LIT_ROP_IN_GPC_PRI_SHARED_IDX 54
#define GPU_LIT_ROP_IN_GPC_STRIDE 55
/** @endcond */ /** @endcond */
/** Macro to get litter values corresponding to the litter defines. */ /** Macro to get litter values corresponding to the litter defines. */

2
drivers/gpu/nvgpu/include/nvgpu/gops/ce.h
View File

@@ -147,7 +147,7 @@ struct gops_ce {
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_ce.h" void (*intr_retrigger)(struct gk20a *g, u32 inst_id);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

15
drivers/gpu/nvgpu/include/nvgpu/gops/cg.h
View File

@@ -62,7 +62,20 @@ struct gops_cg {
void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod); void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_cg.h" void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
/* Ring station slcg prod gops */
void (*slcg_rs_ctrl_fbp_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_ctrl_gpc_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_ctrl_sys_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_fbp_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_gpc_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_sys_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod);
void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
}; };

4
drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h
View File

@@ -103,7 +103,9 @@ struct gops_perf {
int (*wait_for_idle_pmm_routers)(struct gk20a *g); int (*wait_for_idle_pmm_routers)(struct gk20a *g);
int (*wait_for_idle_pma)(struct gk20a *g); int (*wait_for_idle_pma)(struct gk20a *g);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_perf.h" void (*enable_hs_streaming)(struct gk20a *g, bool enable);
void (*reset_hs_streaming_credits)(struct gk20a *g);
void (*enable_pmasys_legacy_mode)(struct gk20a *g, bool enable);
#endif #endif
}; };
struct gops_perfbuf { struct gops_perfbuf {

45
drivers/gpu/nvgpu/include/nvgpu/gops/fb.h
View File

@@ -162,7 +162,41 @@ struct gops_fb_ecc {
}; };
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_fb_vab.h" struct nvgpu_vab_range_checker;
struct gops_fb_vab {
/**
* @brief Initialize VAB
*
*/
int (*init)(struct gk20a *g);
/**
* @brief Initialize VAB range checkers and enable VAB tracking
*
*/
int (*reserve)(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
struct nvgpu_vab_range_checker *vab_range_checker);
/**
* @brief Trigger VAB dump, copy buffer to user and clear
*
*/
int (*dump_and_clear)(struct gk20a *g, u64 *user_buf,
u64 user_buf_size);
/**
* @brief Disable VAB
*
*/
int (*release)(struct gk20a *g);
/**
* @brief Free VAB resources
*
*/
int (*teardown)(struct gk20a *g);
};
#endif #endif
/** /**
@@ -441,7 +475,14 @@ struct gops_fb {
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_fb.h" u32 (*get_num_active_ltcs)(struct gk20a *g);
#ifdef CONFIG_NVGPU_MIG
int (*config_veid_smc_map)(struct gk20a *g, bool enable);
int (*set_smc_eng_config)(struct gk20a *g, bool enable);
int (*set_remote_swizid)(struct gk20a *g, bool enable);
#endif
struct gops_fb_vab vab;
#endif #endif
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU

2
drivers/gpu/nvgpu/include/nvgpu/gops/fifo.h
View File

@@ -215,7 +215,7 @@ struct gops_fifo {
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_fifo.h" void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

7
drivers/gpu/nvgpu/include/nvgpu/gops/fuse.h
View File

@@ -224,7 +224,12 @@ struct gops_fuse {
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_fuse.h" void (*write_feature_override_ecc)(struct gk20a *g, u32 val);
void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val);
void (*read_feature_override_ecc)(struct gk20a *g,
struct nvgpu_fuse_feature_override_ecc *ecc_feature);
u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g);
u32 (*opt_sec_source_isolation_en)(struct gk20a *g);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
}; };

28
drivers/gpu/nvgpu/include/nvgpu/gops/gr.h
View File

@@ -454,7 +454,8 @@ struct gops_gr_intr {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_gr_intr.h" void (*retrigger)(struct gk20a *g);
u32 (*enable_mask)(struct gk20a *g);
#endif #endif
int (*handle_fecs_error)(struct gk20a *g, int (*handle_fecs_error)(struct gk20a *g,
struct nvgpu_channel *ch, struct nvgpu_channel *ch,
@@ -835,7 +836,11 @@ struct gops_gr_init {
bool (*is_allowed_sw_bundle)(struct gk20a *g, bool (*is_allowed_sw_bundle)(struct gk20a *g,
u32 bundle_addr, u32 bundle_value, int *context); u32 bundle_addr, u32 bundle_value, int *context);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_gr_init.h" void (*auto_go_idle)(struct gk20a *g, bool enable);
void (*eng_config)(struct gk20a *g);
int (*reset_gpcs)(struct gk20a *g);
int (*sm_id_config_early)(struct gk20a *g,
struct nvgpu_gr_config *config);
#endif #endif
/** @endcond */ /** @endcond */
}; };
@@ -967,7 +972,21 @@ struct gops_gr_ctxsw_prog {
u32 aperture_mask); u32 aperture_mask);
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_gr_ctxsw_prog.h" #ifdef CONFIG_NVGPU_DEBUGGER
u32 (*hw_get_main_header_size)(void);
u32 (*hw_get_gpccs_header_stride)(void);
u32 (*get_compute_sysreglist_offset)(u32 *fecs_hdr);
u32 (*get_gfx_sysreglist_offset)(u32 *fecs_hdr);
u32 (*get_ltsreglist_offset)(u32 *fecs_hdr);
u32 (*get_compute_gpcreglist_offset)(u32 *gpccs_hdr);
u32 (*get_gfx_gpcreglist_offset)(u32 *gpccs_hdr);
u32 (*get_compute_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num);
u32 (*get_gfx_tpcreglist_offset)(u32 *gpccs_hdr, u32 tpc_num);
u32 (*get_compute_ppcreglist_offset)(u32 *gpccs_hdr);
u32 (*get_gfx_ppcreglist_offset)(u32 *gpccs_hdr);
u32 (*get_compute_etpcreglist_offset)(u32 *gpccs_hdr);
u32 (*get_gfx_etpcreglist_offset)(u32 *gpccs_hdr);
#endif
#endif #endif
}; };
/** @endcond */ /** @endcond */
@@ -1283,7 +1302,8 @@ struct gops_gr {
struct gops_gr_zcull zcull; struct gops_gr_zcull zcull;
#endif /* CONFIG_NVGPU_GRAPHICS */ #endif /* CONFIG_NVGPU_GRAPHICS */
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_gr.h" void (*vab_init)(struct gk20a *g, u32 vab_reg);
void (*vab_release)(struct gk20a *g, u32 vab_reg);
#endif #endif
/** @endcond */ /** @endcond */
}; };

12
drivers/gpu/nvgpu/include/nvgpu/gops/grmgr.h
View File

@@ -77,8 +77,16 @@ struct gops_grmgr {
void (*get_gpcgrp_count)(struct gk20a *g); void (*get_gpcgrp_count)(struct gk20a *g);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG) #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
#include "include/nvgpu/nvgpu_next_gops_grmgr.h" u32 (*get_max_sys_pipes)(struct gk20a *g);
const struct nvgpu_mig_gpu_instance_config* (*get_mig_config_ptr)(
struct gk20a *g);
u32 (*get_allowed_swizzid_size)(struct gk20a *g);
int (*get_gpc_instance_gpcgrp_id)(struct gk20a *g,
u32 gpu_instance_id, u32 gr_syspipe_id, u32 *gpcgrp_id);
int (*get_mig_gpu_instance_config)(struct gk20a *g,
const char **config_name, u32 *num_config_supported);
void (*load_timestamp_prod)(struct gk20a *g);
#endif #endif
}; };
#endif /* NVGPU_NEXT_GOPS_GRMGR_H */ #endif /* NVGPU_GOPS_GRMGR_H */

6
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
View File

@@ -53,7 +53,8 @@ struct gops_ltc_intr {
void (*configure)(struct gk20a *g); void (*configure)(struct gk20a *g);
void (*en_illegal_compstat)(struct gk20a *g, bool enable); void (*en_illegal_compstat)(struct gk20a *g, bool enable);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_ltc_intr.h" void (*isr_extra)(struct gk20a *g, u32 ltc, u32 slice, u32 *reg_value);
void (*ltc_intr3_configure_extra)(struct gk20a *g, u32 *reg);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
}; };
@@ -161,7 +162,8 @@ struct gops_ltc {
int (*set_l2_sector_promotion)(struct gk20a *g, struct nvgpu_tsg *tsg, int (*set_l2_sector_promotion)(struct gk20a *g, struct nvgpu_tsg *tsg,
u32 policy); u32 policy);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_ltc.h" u32 (*pri_shared_addr)(struct gk20a *g, u32 addr);
void (*ltc_lts_set_mgmt_setup)(struct gk20a *g);
#endif #endif
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

31
drivers/gpu/nvgpu/include/nvgpu/gops/mc.h
View File

@@ -259,7 +259,36 @@ struct gops_mc {
#endif #endif
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_mc.h" /**
* @brief Reset HW engines.
*
* @param g [in] The GPU driver struct.
* @param devtype [in] Type of device.
*
* This function is invoked to reset the engines while initializing
* GR, CE and other engines during #nvgpu_finalize_poweron.
*
* Steps:
* - Compute reset mask for all engines of given devtype.
* - Disable given HW engines.
* - Acquire g->mc.enable_lock spinlock.
* - Read mc_device_enable_r register and clear the bits in read value
* corresponding to HW engines to be disabled.
* - Write mc_device_enable_r with the updated value.
* - Poll mc_device_enable_r to confirm register write success.
* - Release g->mc.enable_lock spinlock.
* - If GR engines are being reset, reset GPCs.
* - Enable the HW engines.
* - Acquire g->mc.enable_lock spinlock.
* - Read mc_device_enable_r register and set the bits in read value
* corresponding to HW engines to be enabled.
* - Write mc_device_enable_r with the updated value.
* - Poll mc_device_enable_r to confirm register write success.
* - Release g->mc.enable_lock spinlock.
*/
int (*reset_engines_all)(struct gk20a *g, u32 devtype);
void (*elpg_enable)(struct gk20a *g);
bool (*intr_get_unit_info)(struct gk20a *g, u32 unit);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

6
drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h
View File

@@ -90,7 +90,11 @@ struct gops_pbdma {
void (*dump_status)(struct gk20a *g, void (*dump_status)(struct gk20a *g,
struct nvgpu_debug_context *o); struct nvgpu_debug_context *o);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_pbdma.h" u32 (*set_channel_info_chid)(u32 chid);
u32 (*set_intr_notify)(u32 eng_intr_vector);
u32 (*get_mmu_fault_id)(struct gk20a *g, u32 pbdma_id);
void (*pbdma_force_ce_split)(struct gk20a *g);
u32 (*get_num_of_pbdmas)(void);
#endif #endif
}; };

2
drivers/gpu/nvgpu/include/nvgpu/gops/pmu.h
View File

@@ -218,7 +218,7 @@ struct gops_pmu {
* @param void * @param void
* *
* @return Chip specific PMU Engine Falcon2 base address. * @return Chip specific PMU Engine Falcon2 base address.
* For NEXT_GPUID, NEXT_GPUID PMU Engine Falcon2 base address * For Ampere+, PMU Engine Falcon2 base address
* will be returned. * will be returned.
*/ */
u32 (*falcon2_base_addr)(void); u32 (*falcon2_base_addr)(void);

6
drivers/gpu/nvgpu/include/nvgpu/gops/priv_ring.h
View File

@@ -146,8 +146,10 @@ struct gops_priv_ring {
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_MIG)
#include "include/nvgpu/nvgpu_next_gops_priv_ring.h" int (*config_gr_remap_window)(struct gk20a *g, u32 gr_syspipe_indx,
bool enable);
int (*config_gpc_rs_map)(struct gk20a *g, bool enable);
#endif #endif
}; };

10
drivers/gpu/nvgpu/include/nvgpu/gops/runlist.h
View File

@@ -90,7 +90,15 @@ struct gops_runlist {
void (*init_enginfo)(struct gk20a *g, struct nvgpu_fifo *f); void (*init_enginfo)(struct gk20a *g, struct nvgpu_fifo *f);
u32 (*get_tsg_max_timeslice)(void); u32 (*get_tsg_max_timeslice)(void);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_gops_runlist.h" u32 (*get_runlist_id)(struct gk20a *g, u32 runlist_pri_base);
u32 (*get_engine_id_from_rleng_id)(struct gk20a *g,
u32 rleng_id, u32 runlist_pri_base);
u32 (*get_chram_bar0_offset)(struct gk20a *g, u32 runlist_pri_base);
void (*get_pbdma_info)(struct gk20a *g, u32 runlist_pri_base,
struct nvgpu_next_pbdma_info *pbdma_info);
u32 (*get_engine_intr_id)(struct gk20a *g, u32 runlist_pri_base,
u32 rleng_id);
u32 (*get_esched_fb_thread_id)(struct gk20a *g, u32 runlist_pri_base);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

2
drivers/gpu/nvgpu/include/nvgpu/gr/fs_state.h
View File

@@ -53,7 +53,7 @@ struct nvgpu_gr_config;
int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config); int nvgpu_gr_fs_state_init(struct gk20a *g, struct nvgpu_gr_config *config);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_HAL_NON_FUSA) #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/gr/nvgpu_next_fs_state.h" int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

4
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -118,6 +118,7 @@
struct gk20a; struct gk20a;
struct nvgpu_gr; struct nvgpu_gr;
struct nvgpu_gr_config; struct nvgpu_gr_config;
struct netlist_av_list;
/** /**
* @brief Allocate memory for GR struct and initialize the minimum SW * @brief Allocate memory for GR struct and initialize the minimum SW
@@ -353,7 +354,8 @@ int nvgpu_gr_reset(struct gk20a *g);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */ /** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/gr/nvgpu_next_gr.h" void nvgpu_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g);
void nvgpu_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g);
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

31
drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_fs_state.h
View File

@@ -1,31 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_FS_STATE_H
#define NVGPU_NEXT_FS_STATE_H
struct gk20a;
struct nvgpu_gr_config;
int nvgpu_gr_init_sm_id_early_config(struct gk20a *g, struct nvgpu_gr_config *config);
#endif

37
drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr.h
View File

@@ -1,37 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GR_H
#define NVGPU_NEXT_GR_H
/**
* @file
*
*/
#include <nvgpu/types.h>
struct gk20a;
struct netlist_av_list;
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_local(struct gk20a *g);
void nvgpu_next_gr_init_reset_enable_hw_non_ctx_global(struct gk20a *g);
#endif /* NVGPU_NEXT_GR_H */

30
drivers/gpu/nvgpu/include/nvgpu/gr/nvgpu_next_gr_ecc.h
View File

@@ -1,30 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GR_ECC_H
#define NVGPU_NEXT_GR_ECC_H
/** SM RAMS corrected error count. */
struct nvgpu_ecc_stat **sm_rams_ecc_corrected_err_count;
/** SM RAMS uncorrected error count. */
struct nvgpu_ecc_stat **sm_rams_ecc_uncorrected_err_count;
#endif /* NVGPU_NEXT_GR_ECC_H */

43
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -117,14 +117,11 @@
#include <nvgpu/atomic.h> #include <nvgpu/atomic.h>
#include <nvgpu/lock.h> #include <nvgpu/lock.h>
#include <nvgpu/bitops.h> #include <nvgpu/bitops.h>
#include <nvgpu/cic.h>
struct gk20a; struct gk20a;
struct nvgpu_device; struct nvgpu_device;
#if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_mc.h"
#endif
#define MC_ENABLE_DELAY_US 20U #define MC_ENABLE_DELAY_US 20U
#define MC_RESET_DELAY_US 20U #define MC_RESET_DELAY_US 20U
#define MC_RESET_CE_DELAY_US 500U #define MC_RESET_CE_DELAY_US 500U
@@ -163,6 +160,44 @@ struct nvgpu_device;
/** Bit offset of the Architecture field in the HW version register */ /** Bit offset of the Architecture field in the HW version register */
#define NVGPU_GPU_ARCHITECTURE_SHIFT 4U #define NVGPU_GPU_ARCHITECTURE_SHIFT 4U
#if defined(CONFIG_NVGPU_NON_FUSA)
struct nvgpu_intr_unit_info {
/**
* top bit 0 -> subtree 0 -> leaf0, leaf1 -> leaf 0, 1
* top bit 1 -> subtree 1 -> leaf0, leaf1 -> leaf 2, 3
* top bit 2 -> subtree 2 -> leaf0, leaf1 -> leaf 4, 5
* top bit 3 -> subtree 3 -> leaf0, leaf1 -> leaf 6, 7
*/
/**
* h/w defined vectorids for the s/w defined intr unit.
* Upto 32 vectorids (32 bits of a leaf register) are supported for
* the intr units that support multiple vector ids.
*/
u32 vectorid[NVGPU_CIC_INTR_VECTORID_SIZE_MAX];
/** number of vectorid supported by the intr unit */
u32 vectorid_size;
u32 subtree; /** subtree number corresponding to vectorid */
u64 subtree_mask; /** leaf1_leaf0 value for the intr unit */
/**
* This flag will be set to true after all the fields
* of nvgpu_intr_unit_info are configured.
*/
bool valid;
};
struct nvgpu_next_mc {
/**
* intr info array indexed by s/w defined intr unit name
*/
struct nvgpu_intr_unit_info intr_unit_info[NVGPU_CIC_INTR_UNIT_MAX];
/**
* Leaf mask per subtree. Subtree is a pair of leaf registers.
* Each subtree corresponds to a bit in intr_top register.
*/
u64 subtree_mask_restore[HOST2SOC_NUM_SUBTREE];
};
#endif
/** /**
* This struct holds the variables needed to manage the configuration and * This struct holds the variables needed to manage the configuration and
* interrupt handling of the units/engines. * interrupt handling of the units/engines.

3
drivers/gpu/nvgpu/include/nvgpu/mm.h
View File

@@ -457,7 +457,8 @@ struct mm_gk20a {
struct nvgpu_mem mmu_rd_mem; struct nvgpu_mem mmu_rd_mem;
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
#include "include/nvgpu/nvgpu_next_mm.h" /** VAB struct */
struct nvgpu_vab vab;
#endif #endif
}; };

60
drivers/gpu/nvgpu/include/nvgpu/netlist.h
View File

@@ -29,6 +29,7 @@
#include <nvgpu/types.h> #include <nvgpu/types.h>
struct gk20a; struct gk20a;
struct nvgpu_netlist_vars;
/** /**
* Description of netlist Address-Value(av) structure. * Description of netlist Address-Value(av) structure.
@@ -347,11 +348,6 @@ u32 *nvgpu_netlist_get_gpccs_inst_list(struct gk20a *g);
*/ */
u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g); u32 *nvgpu_netlist_get_gpccs_data_list(struct gk20a *g);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
#if defined(CONFIG_NVGPU_NON_FUSA)
#include <nvgpu/nvgpu_next_netlist.h>
#endif
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER
struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_sys_ctxsw_regs(struct gk20a *g);
struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g); struct netlist_aiv_list *nvgpu_netlist_get_gpc_ctxsw_regs(struct gk20a *g);
@@ -410,6 +406,60 @@ struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);
void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set); void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size); void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index); void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);
bool nvgpu_next_netlist_handle_sw_bundles_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code);
void nvgpu_next_netlist_deinit_ctx_vars(struct gk20a *g);
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_compute_load_av_list(
struct gk20a *g);
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_compute_load_av_list(
struct gk20a *g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_local_gfx_load_av_list(
struct gk20a *g);
struct netlist_av_list *nvgpu_next_netlist_get_sw_non_ctx_global_gfx_load_av_list(
struct gk20a *g);
#endif /* CONFIG_NVGPU_GRAPHICS */
#ifdef CONFIG_NVGPU_DEBUGGER
bool nvgpu_next_netlist_handle_debugger_region_id(struct gk20a *g,
u32 region_id, u8 *src, u32 size,
struct nvgpu_netlist_vars *netlist_vars, int *err_code);
void nvgpu_next_netlist_deinit_ctxsw_regs(struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_compute_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_compute_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_compute_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_compute_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_compute_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_lts_ctxsw_regs(
struct gk20a *g);
#ifdef CONFIG_NVGPU_GRAPHICS
struct netlist_aiv_list *nvgpu_next_netlist_get_sys_gfx_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_gpc_gfx_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_tpc_gfx_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_ppc_gfx_ctxsw_regs(
struct gk20a *g);
struct netlist_aiv_list *nvgpu_next_netlist_get_etpc_gfx_ctxsw_regs(
struct gk20a *g);
#endif /* CONFIG_NVGPU_GRAPHICS */
u32 nvgpu_next_netlist_get_sys_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_next_netlist_get_ppc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_next_netlist_get_gpc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_next_netlist_get_tpc_ctxsw_regs_count(struct gk20a *g);
u32 nvgpu_next_netlist_get_etpc_ctxsw_regs_count(struct gk20a *g);
void nvgpu_next_netlist_print_ctxsw_reg_info(struct gk20a *g);
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif #endif
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */ /** @endcond DOXYGEN_SHOULD_SKIP_THIS */

9
drivers/gpu/nvgpu/include/nvgpu/nvgpu_err.h
View File

@@ -101,6 +101,11 @@ struct mmu_fault_info;
#define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U) #define GPU_SM_L1_TAG_S2R_PIXPRF_ECC_UNCORRECTED (17U)
#define GPU_SM_MACHINE_CHECK_ERROR (18U) #define GPU_SM_MACHINE_CHECK_ERROR (18U)
#define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U) #define GPU_SM_ICACHE_L1_PREDECODE_ECC_UNCORRECTED (20U)
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#define GPU_SM_RAMS_ECC_CORRECTED (21U)
#define GPU_SM_RAMS_ECC_UNCORRECTED (22U)
#endif
/** /**
* @} * @}
*/ */
@@ -814,8 +819,4 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid, void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
u32 mailbox_value); u32 mailbox_value);
#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
#include "include/nvgpu/nvgpu_next_err.h"
#endif
#endif /* NVGPU_NVGPU_ERR_H */ #endif /* NVGPU_NVGPU_ERR_H */

95
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_cic.h
View File

@@ -1,95 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_CIC_H
#define NVGPU_NEXT_CIC_H
/**
* @file
*
* Declare intr specific struct and defines.
*/
#include <nvgpu/types.h>
#include <nvgpu/static_analysis.h>
#define U32_BITS 32U
#define DIV_BY_U32_BITS(x) ((x) / U32_BITS)
#define MOD_BY_U32_BITS(x) ((x) % U32_BITS)
#define RESET_ID_TO_REG_IDX(x) DIV_BY_U32_BITS((x))
#define RESET_ID_TO_REG_BIT(x) MOD_BY_U32_BITS((x))
#define RESET_ID_TO_REG_MASK(x) BIT32(RESET_ID_TO_REG_BIT((x)))
#define GPU_VECTOR_TO_LEAF_REG(i) DIV_BY_U32_BITS((i))
#define GPU_VECTOR_TO_LEAF_BIT(i) MOD_BY_U32_BITS((i))
#define GPU_VECTOR_TO_LEAF_MASK(i) (BIT32(GPU_VECTOR_TO_LEAF_BIT(i)))
#define GPU_VECTOR_TO_SUBTREE(i) ((GPU_VECTOR_TO_LEAF_REG(i)) / 2U)
#define GPU_VECTOR_TO_LEAF_SHIFT(i) \
(nvgpu_safe_mult_u32(((GPU_VECTOR_TO_LEAF_REG(i)) % 2U), 32U))
#define HOST2SOC_0_SUBTREE 0U
#define HOST2SOC_1_SUBTREE 1U
#define HOST2SOC_2_SUBTREE 2U
#define HOST2SOC_3_SUBTREE 3U
#define HOST2SOC_NUM_SUBTREE 4U
#define HOST2SOC_SUBTREE_TO_TOP_IDX(i) ((i) / 32U)
#define HOST2SOC_SUBTREE_TO_TOP_BIT(i) ((i) % 32U)
#define HOST2SOC_SUBTREE_TO_LEAF0(i) \
(nvgpu_safe_mult_u32((i), 2U))
#define HOST2SOC_SUBTREE_TO_LEAF1(i) \
(nvgpu_safe_add_u32((nvgpu_safe_mult_u32((i), 2U)), 1U))
#define STALL_SUBTREE_TOP_IDX 0U
#define STALL_SUBTREE_TOP_BITS \
((BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_1_SUBTREE))) | \
(BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_2_SUBTREE))) | \
(BIT32(HOST2SOC_SUBTREE_TO_TOP_BIT(HOST2SOC_3_SUBTREE))))
/**
* These should not contradict NVGPU_CIC_INTR_UNIT_* defines.
*/
#define NVGPU_CIC_INTR_UNIT_MMU_FAULT_ECC_ERROR 10U
#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT_ERROR 11U
#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT_ERROR 12U
#define NVGPU_CIC_INTR_UNIT_MMU_NON_REPLAYABLE_FAULT 13U
#define NVGPU_CIC_INTR_UNIT_MMU_REPLAYABLE_FAULT 14U
#define NVGPU_CIC_INTR_UNIT_MMU_INFO_FAULT 15U
#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_0 16U
#define NVGPU_CIC_INTR_UNIT_RUNLIST_TREE_1 17U
#define NVGPU_CIC_INTR_UNIT_GR_STALL 18U
#define NVGPU_CIC_INTR_UNIT_CE_STALL 19U
#define NVGPU_CIC_INTR_UNIT_MAX 20U
#define NVGPU_CIC_INTR_VECTORID_SIZE_MAX 32U
#define NVGPU_CIC_INTR_VECTORID_SIZE_ONE 1U
#define RUNLIST_INTR_TREE_0 0U
#define RUNLIST_INTR_TREE_1 1U
void nvgpu_cic_intr_unit_vectorid_init(struct gk20a *g, u32 unit, u32 *vectorid,
u32 num_entries);
bool nvgpu_cic_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
bool nvgpu_cic_intr_get_unit_info(struct gk20a *g, u32 unit, u32 *subtree,
u64 *subtree_mask);
#endif /* NVGPU_NEXT_CIC_H */

36
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_class.h
View File

@@ -1,36 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_CLASS_H
#define NVGPU_NEXT_CLASS_H
#define AMPERE_SMC_PARTITION_REF 0xC637U
#define AMPERE_B 0xC797U
#define AMPERE_A 0xC697U
#define AMPERE_DMA_COPY_A 0xC6B5U
#define AMPERE_DMA_COPY_B 0xC7B5U
#define AMPERE_COMPUTE_A 0xC6C0U
#define AMPERE_COMPUTE_B 0xC7C0U
#define AMPERE_CHANNEL_GPFIFO_A 0xC56FU
#define AMPERE_CHANNEL_GPFIFO_B 0xC76FU
#endif /* NVGPU_NEXT_CLASS_H */

58
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_device.h
View File

@@ -1,58 +0,0 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_TOP_H
#define NVGPU_NEXT_TOP_H
#include <nvgpu/pbdma.h>
struct nvgpu_device_next {
/**
* True if the device is an method engine behind host.
*/
bool engine;
/**
* Runlist Engine ID; only valid if #engine is true.
*/
u32 rleng_id;
/**
* Runlist PRI base - byte aligned based address. CHRAM offset can
* be computed from this.
*/
u32 rl_pri_base;
/**
* PBDMA info for this device. It may contain multiple PBDMAs as
* there can now be multiple PBDMAs per runlist.
*
* This is in some ways awkward; devices seem to be more directly
* linked to runlists; runlists in turn have PBDMAs. Granted that
* means there's a computable relation between devices and PBDMAs
* it may make sense to not have this link.
*/
struct nvgpu_next_pbdma_info pbdma_info;
};
#endif

38
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_ecc.h
View File

@@ -1,38 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ECC_H
#define NVGPU_NEXT_ECC_H
/* Leave extra tab to fit into nvgpu_ecc.fb structure */
struct nvgpu_ecc_stat *mmu_l2tlb_ecc_corrected_unique_err_count;
/** hubmmu l2tlb uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_l2tlb_ecc_uncorrected_unique_err_count;
/** hubmmu hubtlb corrected unique error count. */
struct nvgpu_ecc_stat *mmu_hubtlb_ecc_corrected_unique_err_count;
/** hubmmu hubtlb uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_hubtlb_ecc_uncorrected_unique_err_count;
/** hubmmu fillunit corrected unique error count. */
struct nvgpu_ecc_stat *mmu_fillunit_ecc_corrected_unique_err_count;
/** hubmmu fillunit uncorrected unique error count. */
struct nvgpu_ecc_stat *mmu_fillunit_ecc_uncorrected_unique_err_count;
#endif /* NVGPU_NEXT_ECC_H */

37
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engine_status.h
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@@ -1,37 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ENGINE_STATUS_H
#define NVGPU_NEXT_ENGINE_STATUS_H
/**
* @file
*
* Declare device info specific struct and defines.
*/
#include <nvgpu/types.h>
struct nvgpu_next_engine_status_info {
/** Engine status_1 h/w register's read value. */
u32 reg1_data;
};
#endif /* NVGPU_NEXT_ENGINE_STATUS_H */

41
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_engines.h
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@@ -1,41 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ENGINES_H
#define NVGPU_NEXT_ENGINES_H
/**
* @file
*
* Declare engine info specific struct and defines.
*/
#include <nvgpu/types.h>
struct gk20a;
struct nvgpu_device;
#define ENGINE_PBDMA_INSTANCE0 0U
int nvgpu_next_engine_init_one_dev(struct gk20a *g,
const struct nvgpu_device *dev);
#endif /* NVGPU_NEXT_ENGINES_H */

32
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_err.h
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@@ -1,32 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ERR_H
#define NVGPU_NEXT_ERR_H
/*
* Error IDs for SM unit.
*/
#define GPU_SM_RAMS_ECC_CORRECTED (21U)
#define GPU_SM_RAMS_ECC_UNCORRECTED (22U)
#endif /* NVGPU_NEXT_ERR_H */

35
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_errata.h
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@@ -1,35 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_ERRATA_H
#define NVGPU_NEXT_ERRATA_H
#define ERRATA_FLAGS_NEXT \
/* GA100 */ \
DEFINE_ERRATA(NVGPU_ERRATA_200601972, "GA100", "LTC TSTG"), \
/* GA10B */ \
DEFINE_ERRATA(NVGPU_ERRATA_2969956, "GA10B", "FMODEL FB LTCS"), \
DEFINE_ERRATA(NVGPU_ERRATA_200677649, "GA10B", "UCODE"), \
DEFINE_ERRATA(NVGPU_ERRATA_3154076, "GA10B", "PROD VAL"), \
DEFINE_ERRATA(NVGPU_ERRATA_3288192, "GA10B", "L4 SCF NOT SUPPORTED"),
#endif /* NVGPU_NEXT_ERRATA_H */

65
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fb.h
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@@ -1,65 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_FB_H
#define NVGPU_NEXT_FB_H
/* VAB track all accesses (read and write) */
#define NVGPU_VAB_MODE_ACCESS BIT32(0U)
/* VAB track only writes (writes and read-modify-writes) */
#define NVGPU_VAB_MODE_DIRTY BIT32(1U)
/* No change to VAB logging with VPR setting requested */
#define NVGPU_VAB_LOGGING_VPR_NONE 0U
/* VAB logging disabled if vpr IN_USE=1, regardless of PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_IN_USE_DISABLED BIT32(0U)
/* VAB logging disabled if vpr PROTECTED_MODE=1, regardless of IN_USE */
#define NVGPU_VAB_LOGGING_VPR_PROTECTED_DISABLED BIT32(1U)
/* VAB logging enabled regardless of IN_USE and PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_ENABLED BIT32(2U)
/* VAB logging disabled regardless of IN_USE and PROTECTED_MODE */
#define NVGPU_VAB_LOGGING_VPR_DISABLED BIT32(3U)
struct nvgpu_vab_range_checker {
/*
* in: starting physical address. Must be aligned by
* 1 << (granularity_shift + bitmask_size_shift) where
* bitmask_size_shift is a HW specific constant.
*/
u64 start_phys_addr;
/* in: log2 of coverage granularity per bit */
u8 granularity_shift;
u8 reserved[7];
};
struct nvgpu_vab {
u32 user_num_range_checkers;
struct nvgpu_mem buffer;
};
int nvgpu_fb_vab_init_hal(struct gk20a *g);
int nvgpu_fb_vab_teardown_hal(struct gk20a *g);
#endif /* NVGPU_NEXT_FB_H */

71
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_fuse.h
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@@ -1,71 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_FUSE_H
#define NVGPU_NEXT_FUSE_H
/**
* @file
*
* Declare device info specific struct and defines.
*/
#include <nvgpu/types.h>
struct nvgpu_fuse_feature_override_ecc {
/** overide_ecc register feature */
/** sm_lrf enable */
bool sm_lrf_enable;
/** sm_lrf override */
bool sm_lrf_override;
/** sm_l1_data enable */
bool sm_l1_data_enable;
/** sm_l1_data overide */
bool sm_l1_data_override;
/** sm_l1_tag enable */
bool sm_l1_tag_enable;
/** sm_l1_tag overide */
bool sm_l1_tag_override;
/** ltc enable */
bool ltc_enable;
/** ltc overide */
bool ltc_override;
/** dram enable */
bool dram_enable;
/** dram overide */
bool dram_override;
/** sm_cbu enable */
bool sm_cbu_enable;
/** sm_cbu overide */
bool sm_cbu_override;
/** override_ecc_1 register feature */
/** sm_l0_icache enable */
bool sm_l0_icache_enable;
/** sm_l0_icache overide */
bool sm_l0_icache_override;
/** sm_l1_icache enable */
bool sm_l1_icache_enable;
/** sm_l1_icache overide */
bool sm_l1_icache_override;
};
#endif /* NVGPU_NEXT_FUSE_H */

29
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_ce.h
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@@ -1,29 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_CE_H
#define NVGPU_NEXT_GOPS_CE_H
/* Leave extra tab to fit into gops_ce structure */
void (*intr_retrigger)(struct gk20a *g, u32 inst_id);
#endif /* NVGPU_NEXT_GOPS_CE_H */

42
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_cg.h
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@@ -1,42 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_CG_H
#define NVGPU_NEXT_GOPS_CG_H
/* Leave extra tab to fit into gops_cg structure */
void (*slcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
void (*blcg_runlist_load_gating_prod)(struct gk20a *g, bool prod);
/* Ring station slcg prod gops */
void (*slcg_rs_ctrl_fbp_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_ctrl_gpc_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_ctrl_sys_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_fbp_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_gpc_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_rs_sys_load_gating_prod)(struct gk20a *g, bool prod);
void (*slcg_timer_load_gating_prod)(struct gk20a *g, bool prod);
void (*elcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
#endif /* NVGPU_NEXT_GOPS_CG_H */

36
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb.h
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@@ -1,36 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_FB_H
#define NVGPU_NEXT_GOPS_FB_H
/* Leave extra tab to fit into gops_fb structure */
u32 (*get_num_active_ltcs)(struct gk20a *g);
#ifdef CONFIG_NVGPU_MIG
int (*config_veid_smc_map)(struct gk20a *g, bool enable);
int (*set_smc_eng_config)(struct gk20a *g, bool enable);
int (*set_remote_swizid)(struct gk20a *g, bool enable);
#endif
struct gops_fb_vab vab;
#endif /* NVGPU_NEXT_GOPS_FB_H */

61
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fb_vab.h
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@@ -1,61 +0,0 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_FB_VAB_H
#define NVGPU_NEXT_GOPS_FB_VAB_H
struct nvgpu_vab_range_checker;
struct gops_fb_vab {
/**
* @brief Initialize VAB
*
*/
int (*init)(struct gk20a *g);
/**
* @brief Initialize VAB range checkers and enable VAB tracking
*
*/
int (*reserve)(struct gk20a *g, u32 vab_mode, u32 num_range_checkers,
struct nvgpu_vab_range_checker *vab_range_checker);
/**
* @brief Trigger VAB dump, copy buffer to user and clear
*
*/
int (*dump_and_clear)(struct gk20a *g, u64 *user_buf,
u64 user_buf_size);
/**
* @brief Disable VAB
*
*/
int (*release)(struct gk20a *g);
/**
* @brief Free VAB resources
*
*/
int (*teardown)(struct gk20a *g);
};
#endif /* NVGPU_NEXT_GOPS_FB_VAB_H */

29
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fifo.h
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@@ -1,29 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_FIFO_H
#define NVGPU_NEXT_GOPS_FIFO_H
/* Leave extra tab to fit into gops_fifo structure */
void (*runlist_intr_retrigger)(struct gk20a *g, u32 intr_tree);
#endif /* NVGPU_NEXT_GOPS_FIFO_H */

34
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_fuse.h
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@@ -1,34 +0,0 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_FUSE_H
#define NVGPU_NEXT_GOPS_FUSE_H
/* Leave extra tab to fit into gops_fuse structure */
void (*write_feature_override_ecc)(struct gk20a *g, u32 val);
void (*write_feature_override_ecc_1)(struct gk20a *g, u32 val);
void (*read_feature_override_ecc)(struct gk20a *g,
struct nvgpu_fuse_feature_override_ecc *ecc_feature);
u32 (*fuse_opt_sm_ttu_en)(struct gk20a *g);
u32 (*opt_sec_source_isolation_en)(struct gk20a *g);
#endif /* NVGPU_NEXT_GOPS_FUSE_H */

29
drivers/gpu/nvgpu/include/nvgpu/nvgpu_next_gops_gr.h
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@@ -1,29 +0,0 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_NEXT_GOPS_GR_H
#define NVGPU_NEXT_GOPS_GR_H
/* Leave extra tab to fit into gops_gr_intr structure */
void (*vab_init)(struct gk20a *g, u32 vab_reg);
void (*vab_release)(struct gk20a *g, u32 vab_reg);
#endif /* NVGPU_NEXT_GOPS_GR_H */

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