Address MISRA Rule 20.7 violation: Macro parameter expands into an
expression without being wrapped by parentheses.
Some of the exception the coverity is not able to catch are:
1. Macro parameters passed as parameter to another macro.
i.e NVGPU_ACCESS_ONCE. Fixing these by additional parantheses.
2. Macro parameter used as type. i.e. type parameter in container_of.
While at it, update copyright date rage for list.h and types.h.
JIRA NVGPU-841
Change-Id: I4b793981d671069289720e8c041bad8125961c0c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929823
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Fixed timeout checking flow in sync-unmap where timeout message could
be printed while there is not a timeout.
The original codeflow doesn't check refcount of a mapped_buffer again
after 10ms waiting. So if the buffer is released during the last
round of waiting, the timeout message will still be printed. The new
codeflow combines refcount and timeout checking. So that there won't
be an inconsistency between the two.
Bug 200434475
Change-Id: Id0a0aebcb24906a1ec7113e669227788e729564b
Signed-off-by: Kyle Guo <kyleg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930236
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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struct gk20a from gk20a.h needs defination of struct gk20a_ce_app
and ce2_gk20a.h needs defination of struct gk20a. This creates
a circular dependency.
Fix this by making gk20a_ce_app a pointer to skip knowing the
complete type details and using forward declarations for struct
gk20a_ce_app and struct gk20a.
The gk20a_ce_app pointer is alloc'ed in gk20a_init_ce_support()
and free'ed in gk20a_ce_destroy.
JIRA NVGPU-611
Change-Id: I4d62d5f2b2d1492db73bae69f90a1fe5586fba76
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917945
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This patch moves the increment and decrement of the user mapped
buffer count to the insert/remove mapped buffer functions since
this value should only ever change when these functions are called.
Bug 200105199
Change-Id: I5b0a86d00e9e948c48e313153a668eb2e10fca49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917791
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Nvgpu uses many ways to check if sync points are enabled. The four
ways used to be:
platform->has_syncpoints
g->has_syncpoints
nvgpu_is_enabled(g, NVPGU_HAS_SYNCPOINTS)
gk20a_platform_has_syncpoints()
This patch standardizes all usage to now be nvgpu_has_syncpoints()
which is based on gk20a_platform_has_syncpoints() - just renamed to
be general to nvgpu.
All usage of the other forms have now been consolidated. However,
under the hood nvgpu_has_syncpoints() does check the is_enabled
flag. This flag is now set where g->has_syncpoints used to be set
based on the platform data.
The basic dependency chain is this:
nvgpu_has_syncpoints -> NVGPU_HAS_SYNCPOINTS ->
platform->has_syncpoints
However, note: there are several places where syncpoints can be
disabled if some other driver initialization fails (for ex. host1x).
Also note that nvgpu_has_syncpoints() also considers a disable
variable set by debugfs.
Bug 2327574
Change-Id: Ia2375a80f5f2e27285e6175568dd13e6bb25fd33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803975
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Input paran VM Will be used to get PTE size for GVA spaces and it can be
NULL if buddy_allocator initialization is not for GVA space. As part of
recent changes VM was being accessed for non GVA space case and for that
VM was NULL, causing the crash.
In this fix added a prior check and VM will be accessed only if input
flag is set to GPU_ALLOC_GVA_SPACE.
Bug 200452730
Change-Id: I9dcb1f2bd5e639c37a7152b99453bb5b46fe4087
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1842530
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Tested-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in common directory
by renaming them to follow the convention,
'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition
between file name and directory or 'NVGPU_HEADER-NAME' when there
is repetition.
JIRA NVGPU-1028
Change-Id: Idf10f6b179cfd96bfb8ab8e9e2bf79c26591905d
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809086
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We have a h/w bug on some chips and we need to support below additional
HALs to implement a s/w WAR
gops.fifo.init_pdb_cache_war()
gops.fifo.deinit_pdb_cache_war()
gops.fb.apply_pdb_cache_war()
Add new API nvgpu_init_mm_pdb_cache_war() to initialize WAR sequence
and call this from MM initialization and before setting up rest of the
memory management units
Deinitialize WAR while cleaning up MM support
Add pdb_cache_war_mem member to gk20a to hold all the memory needed
for the WAR
Bug 200449545
Change-Id: Id2ac0d940c7881c7b0cf396413273c0f329a1a1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1834901
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-Created struct nvgpu_acr to hold acr module related member
within single struct which are currently spread across multiple structs
like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr to perform ACR specific operation,
currently ACR ops were part PMU which caused to have always dependence
on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
gk20a_remove_support() method, earlier acr cleanup was part of
pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
statically for chip currently in execution & assign ops to point to
needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
HAL for all chips to bootstrap ACR, earlier had 3 different function for
gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.
JIRA NVGPU-1148
Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
Fixes for all the pd_cache functions that use '__' prefixes. This
was trivial: the '__' prefix was simply deleted.
JIRA NVGPU-1029
Change-Id: Ia91dabe3ef97fb17a2a85105935fb3a72d7c2c5e
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813643
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
Handle the 21.2 fixes for nvgpu_mem.c and mm.c; this deletes the
'__' prefixes and slightly renames the __nvgpu_aperture_mask()
function since there's a coherent version and a general version.
Change-Id: Iee871ad90db3f2622f9099bd9992eb994e0fbf34
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813623
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
Fixes for the buddy allocator. These are all pretty trivial; mostly
the '__' prefix is simply deleted since the functions are all static.
The one exception is the list accessors were also renamed slightly to
include a 'do' component to show more clearly that the other list
accessors are convenience functions.
JIRA NVGPU-1029
Change-Id: Ia39cdde9a81e740537fc9b4d70d87eadc12f8d4d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813601
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This fixes places in the public allocator APIs. This consists of
the various init routines which are used to create an allocator
and the debug macro used within the allocator code.
The buddy allocator was handled by collapsing the internal
'__' prepended version with the non-prefixed version. The only
required change was in the page_allocator code which now had to
pass in a NULL vm pointer (since the VM is not needed for managing
VIDMEM).
JIRA NVGPU-1029
Change-Id: I484a144e61789bf594c525c1ca307b96d120830f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813578
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Debug page was allocated and programmed to HUB MMU in GR code. This
introduces a dependency from GR to FB and is anyway the wrong place.
Move the code to allocate memory to generic MM code, and the code
to program the addresses to FB.
Change-Id: Ib6d3c96efde6794cf5e8cd4c908525c85b57c233
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801423
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The issues are:
1. Non-fixed allocs must take into account explicit PTE size
requests. Previously the PTE size was determines from the
allocation size which was incorect. To do this, the PTE size
is now plumbed through all GPU VA allocations. This is what
the new alloc_pte() op does.
2. Fix buddy PTE size assignment. This changes a '<=' into a
'<' in the buddy allocation logic. Effectively this is now
leaving the PTE size for buddy blocks equal to the PDE block
size as 'ANY'.
This prevents a buddy block of PDE size which has yet to be
allocated from having a specific PDE size. Without this its
possible to do a fixed alloc that fails unexpectedly due to
mismatching PDE sizes.
Consider two PDE block sized fixed allocs that are contained
in one buddy twice the size of a PDE block. Let's call these
fixed allocs S and B (small and big). Let's assume that two
fixed allocs are done, each targeting S and B, in that order.
With the current logic the first alloc, when we create the
two buddies S and B, causes both S and B to have a PTE size of
SMALL. Now when the second alloc happens we attempt to find
a buddy B with a PTE size of either BIG or ANY. But we cannot
becasue B already has size SMALL. This casues us to appear
like we have a conflicting fixed alloc despite this not being
the case.
3. Misc cleanups & bug fixes:
- Clean up some MISRA issues
- Delete an extraneous unlock that could have caused a
deadlock.
Bug 200105199
Change-Id: Ib5447ec6705a5a289ac0cf3d5e90c79b5d67582d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1768582
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We use bootstrap vidmem allocator for all the vidmem allocations that happen
boot time
And we need to program physical address for all the potential vidmem buffers
that we program into h/w and are needed during boot
So force the allocator to allocate contigous memory
We otherwise see a warning dump when we program physical address of memory which
is allocated in multiple pages
Bug 2180284
Jira NVGPUT-12
Change-Id: Ib9c2d42ea463bc424c2cb4da8ffd8ebae436e0f6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805467
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We right now have a bootstrap carveout in vidmem of size 16M and having base
address at {total_vidmem_size - 256M}
So this design divides rest of the vidmem into two chunks
And the size of bootstrap carveout is also small and insufficient for vidmem
allocations during boot
Hence increase the bootstrap vidmem carevout to 256M and move it to the end
of entire vidmem
Rename the carevout name for wpr_co to bootstrap_co as it is more appropriate
Also update __nvgpu_vidmem_do_clear_all() to clear only one chunk of vidmem
instead of two
Bug 2180284
Jira NVGPUT-12
Change-Id: I9c8d62bcd705c7112385df3d4f714e0190b48e17
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805466
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change fixes uses of '__' prepended to static functions defined
in page_allocator.c. Since these funcitons were static and had no
naming conflicts the '__' was simply removed. For free_pages() this
also needed to have a nvgpu specific prefix since free_pages()
conflicts with a Linux kernel function name.
JIRA NVGPU-1029
Change-Id: I8b96e55244bd2de166f7dcc64d2b30427757ea8f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812826
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_mutex_init and
improves related error handling.
JIRA NVGPU-677
Change-Id: I609fa138520cc7ccfdd5aa0e7fd28c8ca0b3a21c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805598
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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This migrates the common DMA code (os agnostic) to the
common directory. This new unit will be the common DMA
allocator that lets users allocate SYSMEM, VIDMEM, or
either. Other units will be responsible for actually
handling the mechanics of allocating VIDMEM or SYSMEM.
Also update the names of the DMA related files so that
tmake doesn't complain about duplicate C file names. To
do this call the common DMA file dma.c and prepend the
OS to the other DMA files. So now we have:
common/mm/dma.c
os/posix/posix-dma.c
os/linux/linux-dma.c
JIRA NVGPU-990
Change-Id: I22d2d41803ad89be7d9c28f87864ce4fedf10836
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1799807
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__nvgpu_gmmu_map() does not currently have a mechanism for returning an
error code if something goes wrong; it just returns zero on error, or a
nonzero address when mapping was successful. Change it to return 0
instead of -ENOMEM if the creation of nvgpu_sgt from mem fails. Out of
memory is the only meaningful failure case anyway, and this -ENOMEM
would just look like a (huge) memory address.
Change-Id: If176e165b1f9a8fa84a1bdf3080c9059a193081f
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1812491
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fix violations where an arithmetic operation is performed on
signed and unsigned int types.
In balloc_get_order_list() the argument "int order" has been changed to
a u64 because all callers of this function pass a u64 argument.
JIRA NVGPU-992
Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784419
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: I553a66a3d7d2c6bb21ba0a45e29a1d01f7b89f49
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: Ic39213ab800e92c6815ce5b9deb22520aa6d0630
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803352
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MISRA 21.2 states that we may not use reserved identifiers; since
all identifiers beginning with '_' are reserved by libc, the usage
of '__' as a prefix is disallowed.
This change removes the usage of the '__a' argument scattered
throughout the nvgpu allocator code.
JIRA NVGPU-1029
Change-Id: I5a9b8a3e0602ba4d519ca19080951402b6f3287d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1803351
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Changed the enum gmmu_pgsz_gk20a into macros and changed all the
instances of it.
The enum gmmu_pgsz_gk20a was being used in for loops, where it was
compared with an integer. This violates MISRA rule 10.4, which only
allows arithmetic operations on operands of the same essential type
category. Changing this enum into macro will fix this violation.
JIRA NVGPU-993
Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3
Signed-off-by: Amulya <Amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795593
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Add a WAR for gm20b that allows us to force the PMU VM to use
128K large pages. For some reason setting the small page size
to 64K breaks the PMU boot. Unclear why. Bug needs to be filed
and fixed. Once fixed this patch can and should be reverted.
Bug 200105199
Change-Id: I2b4c9e214e2a6dff33bea18bd2359c33364ba03f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1782769
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MISRA Rule 10.3 states that the value of an expression shall not be
assigned to an object with a narrower essential type or of a
different essential type category.
We have cases where we are converting to/from char and non char types
and this fix 10.3 violations resulting from these conversions.
This also fix violations in conversions between s8 and non-s8 types
as s8 can be typedefed as char.
Jira NVGPU-1010
Change-Id: I150dd633eb7575de9ea2bedd598b7af74d1fcbd9
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801613
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This flag - has_physical_mode - doesn't seem to do much other than
force the PTE/PDE and inst block addresses to be physical instead
of potentially IOMMUed.
There is a reason to do this on volta (nvlink not being IOMMU'able
being the primary reason) but this flag is too general it seems.
The flag was being enabled on all native platforms. The problem is
that some page tables (the maxwell small page directories) could
be larger than 4KB which meant that the allocation used for them
could be potentially discontiguous. Discontiguous page directories
obviously is incorrect.
This patch deletes the has_physical_mode flag and instead replaces
the places where it's checked with a check for nvlink being
enabled. Since we _do_ want to program phyiscal PDEs and PTEs for
NVLINK devices (regardless of IOMMU status they always access
memory by physical address) we need a check for NVLINK state.
Bug 200414723
Change-Id: I09ad86b12d8aabcf9648a22503f4747fd63514dd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1792163
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
FB fault buffer is enabled on finalize poweron. Disable the buffer
in prepare poweroff. This also eliminates the need to disable
the buffer in fault info mem destroy which otherwise accesses
GPU registers after these are locked in prepare poweroff.
Bug 200427479
Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
