Falcon safety debug flag was previously disabled for safety debug
profile. This patch enables the flag support for safety debug.
copy_from_dmem function is required to copy the debug info from
dmem debug buffer whenever there's an error generated.
Hence, moved copy_from_dmem function to fusa file from non-fusa
and added ifdef condition to only enable when non-fusa or falcon debug
flag is set.
Also, some fixes for type conversion error in falcon_debug.c during
compilation.
Bug 3482988
Change-Id: Ic0ea32b3227b84d4ba0835e6e1aeb40f58ec7327
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673900
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Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.
Other noteworthy changes in this patch related to safety build:
- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
in those files is required for GA10B. Unnecessary code will be
compiled out later on.
hal/gr/init/gr_init_tu104.c
hal/class/class_tu104.c
hal/mc/mc_tu104.c
hal/fifo/usermode_tu104.c
hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
to work around compilation errors seen with keeping this config
enabled. Config will be re-enabled in safety debug build later.
Jira NVGPU-7276
Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
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- Fix GSP/PMU registers priv errors which are seen as part of boot sequence.
- Couple of GSP/PMU Falcon/NVRISCV registers are allowed to access
upon NVRISCV bootrom completion but these registers were needed
to configure on legacy chips to bootstrap/configure Falcon.
- Add is_falcon2_enabled or NVGPU_PMU_NEXT_CORE_ENABLED check
to skip these registers.
JIRA NVGPU-7025
Change-Id: I087a477ade6736398dea113f89894a0ff73ae647
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2553127
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Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.
Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.
With these changes, we get 100% line coverage for common.falcon unit.
JIRA NVGPU-2214
Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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Functions for copying to falcon memory typecast from pointer to char of
input buffer to pointer to u32 since falcon data registers are written
in 4-bytes. Firmware data is generally byte stream and hence we won't
be able to deal with input buffer as pointer to u32.
Hence, misra rule 11.3 deviation is required for these casts. Firmware
data is also not aligned at word boundary sometimes hence we need to
copy it to aligned buffer to conform to the deviation recommendation.
hal/falcon/falcon_gk20a_fusa.c:136
Checker: MISRA C-2012 Rule 11.3 (Required)
misra_c_2012_rule_11_3_violation: The object pointer expression "src"
of type "u8 *" is cast to type "u32 *".
This patch implements copy to falcon memory from unaligned source byte
by byte and casts the input buffer to u32 pointer otherwise.
JIRA NVGPU-4128
Change-Id: Iff3cc1010b8e209ec453c10c6d46953cf5a8adbe
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210321
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.
The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.
JIRA NVGPU-3820
Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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This patch reverts the following commit 13a7ef2cc7
The bios devinit for tu104 encountered the unaligned buffer scenario.
However bios devinit functionality is now removed from nvgpu. Other
than that there are no firmwares where we expect the input/output
buffer addresses to be un-aligned, hence removing the logic added
to handle un-aligned addresses.
JIRA NVGPU-3271
Change-Id: Ifd24cc5b50b9d2548878436befb2220e7bf02ed4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2161735
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.
Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.
Jira NVGPU-3690
Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Function for copying to/form IMEM/DMEM cast pointer to char to
pointer to u32 since falcon data registers are read/written in
4-bytes. Firmware data is generally byte stream and hence we
won't be able to deal in pointer to u32. Hence we need deviate
from misra rule 11.3.
Firmware data is also not aligned at word boundary sometimes
hence we need to copy it byte by byte to conform to the dev-
iation recommendation.
Error: MISRA C-2012 Rule 11.3: ./hal/falcon/falcon_gk20a.c:296:
misra_violation: The object pointer expression "src" of type
"u8 *" is cast to type "u32 *".
JIRA NVGPU-3271
Change-Id: Ic081f97226dbbcf08402970829624933402066eb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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