Instead of just the base address of the main register range, store
(also) the base address of usermode area. All regs may not be always
available; on vgpu guests we have only the usermode regs.
Store the usermode addr we get from a platform resource directly in
gv11b_vgpu_probe() for vgpu. In that case the main reg addr is unset.
The base address is computed in gk20a_pm_finalize_poweron() for native
environments; when the reg addr is read from a resource, the chip is
still unknown and as such the HAL op for reading the usermode base
offset is unavailable.
Bug 200145225
Bug 200467197
Change-Id: I8855bb54a6456eb63b69559c84398f7eeaec3513
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951524
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Enable the unified address space config for
o gp10b
o gv11b
gm20b is suffering from a problem in a T214 MODS test. This should
work for the time being in more recent chips. Also this will
increase the soak time these changes get before being released.
Other chips (vGPUs, dGPUs) will (possibly) be enabled at a later
date.
Bug 200105199
Change-Id: I03a6803c6369d89e8a318886fc642b55c5538dd9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951858
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Currently has_timedout variable is protected by wmb at places
where it is being set and there is no correspoding rmb whenever
has_timedout variable is read. This is prone to errors for
concurrent execution. This change is supposed to fix this issue.
Rename has_timedout variable of channel struct to ch_timedout.
Also to avoid rmb every time ch_timedout is read,
ch_timedout_spinlock is added to protect ch_timedout
variable for taking care of concurrent execution.
Bug 2404865
Bug 2092051
Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930935
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MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.
JIRA NVGPU-847
Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
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Add a flag to nvgpu_gpu_characteristics to expose FECS tracing capability to
userspace.
This is required for adding nvrm_gpu APIs for CTXSW set of IOCTLs which were
requested in several bugs.
nvrm_gpu APIs would query this flag to check the availability of IOCTLs.
Bug 2169678
Bug 2169677
Bug 2169675
Bug 2169674
Bug 2169673
Bug 2168342
Change-Id: Ie6ba80a4144637546b97fa93baae67b8d0c4d425
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950559
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
While linux os code does not need to be MISRA-compliant this
change switches over all memcpy() uses to nvgpu_memcpy()
with appropriate casts applied to maintain consistency within
the nvgpu source base.
JIRA NVGPU-849
Change-Id: I2c21a7845df5709dafa19508c121f8afa27cc4fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950995
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I7ced14d6629e033b0ccef3a93a3dbf099e43ba4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946662
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.
Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.
JIRa NVGPU-596
Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822587
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gk20a.c is used only in Linux build. It's in theory common code, but
in practice implements OS specific policies. Also implement
os/posix/gk20a.c to implement gk20a_init_gpu_characteristics(),
gk20a_get() and gk20a_put() which are called from common code.
JIRA NVGPU-596
Change-Id: I6a6079ca6d4c6a225f0dd0e1cd7c439333a704bf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1944884
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Update the debug crash dump to be clearer, more concise and
avoid many of the misformatting issues that have crept in over
the last couple years.
This also changes the debug prints to move from pr_err() in
the Linux kernel to nvgpu_err(). This makes it easier to
filter all nvgpu messages in a log file with a single grep
command.
Change-Id: I00ca9e6c32da7a79c8f6903a139bf6b43e89618a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940515
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Originally the order for output was:
1. Dump platform deps (sync-points/host1x stuff)
2. Dump PBDMA status
3. Dump engine status
4. Dump channel status
The updated ordering is:
1. Dump channel status
2. Dump PBDMA status
3. Dump engine status
4. Dump platform deps (sync-points/host1x stuff)
The purpose of this is to put the useful information first and
relegate the less useful info to later in the dump. We naturally
scan downwards and treat stuff at the top as most important.
The end goal is to make the debug dump as useful in as little
time as possible. So instead of making an engineer dig through
a complex jumble of information to find the useful stuff the
hope is that the useful stuff is immediately available.
Change-Id: I9d2b755676b7e5dc2f8949f14dc36f3d337e2a3f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1940514
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This function returns a boolean describing if a given log
mask is enabled for a given GPU. Previously this returned
and int but the bool type is far better suited for this.
Also implement this function in posix, as it may be useful
to have implemented there if any common code chooses to
use this function.
Change-Id: I7382e73df83282763df1bdbccbbb219c9f3e6f1b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938341
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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Add a fifo HAL for querying the doorbell token of a specific channel and
call it instead of doing the calculation directly. For Volta the token
is just the channel id plus the possible base number.
Bug 200145225
Change-Id: Ifbb150191575fdc72e413a14c799cab7e52d8c14
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1849639
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MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.
JIRA NVGPU-775
Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Linux interface.
JIRA NVGPU-1036
Change-Id: I39b20f1d0e1a1da56d452f2c3d5ee049666cefe8
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929900
Reviewed-by: Automatic_Commit_Validation_User
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Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.
To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.
Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.
Bug 200145225
Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795821
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Add a mmap callback on the control device node for mapping the usermode
register region to userspace. Each such mapping is removed when the GPU
railgates, and brought back again on unrailgate.
The mapping offset must be 0 and its size must be 4 KB.
Bug 200145225
Change-Id: Ie8d3758da745b958376292691d7d1d02a24e7815
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1795819
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Usermode submit needs to access the usermode region of registers from
userspace. Store the start address of register resource in struct
nvgpu_os_linux to be used in remap to userspace.
Bug 200145225
Change-Id: I3796b6bf67942af0cc16c86accb82a013032bfc8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1811838
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struct nvgpu_channel_sync is moved to a private header i.e.
channel_sync_priv.h present in common/sync/. All accesses to callback
functions inside the struct nvgpu_channel_sync in NVGPU driver is replaced by
the public channel_sync specific APIs.
Jira NVGPU-1093
Change-Id: I52d57b3d458993203a3ac6b160fb569effbe5a66
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929783
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The nvlink needs to be de-initialized as part of system
shutdown or reboot. Add the shutdown callback of pci driver
and use it to trigger nvlink de-initialization.
Bug 200422323
Change-Id: Iec8193d9665bc77ddbf3680ea130dfa4c1b3b0ad
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928821
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Background:
In Hypervisor mode dGPU device is configured in pass through mode for
the Guest (QNX/Linux). GMMU programming is handled by the guest which
converts a mapped buffer's GVA into SGLes in IPA (Intermediate/Guest
Physical address) which is then translated into PA (Acutual Physical
address) and programs the GMMU PTEes with correct GVA to PA mapping.
Incase of the vgpu this work is delegated to the RM server which takes care
of the GMMU programming and IPA to PA conversion.
Problem:
The current GMMU mapping logic in the guest assumes that PA range is
continuous over a given IPA range. Hence, it doesn't account for holes being
present in the PA range. But this is not the case, a continous IPA range
can be mapped to dis-contiguous PA ranges. In this situation the mapping
logic sets up GMMU PTEes ignoring the holes in physical memory and
creates GVA => PA mapping which intrudes into the PA ranges which are
reserved. This results in memory being corrupted.
This change takes into account holes being present in a given PA range and
for a given IPA range it also identifies the discontiguous PA ranges and
sets up the PTE's appropriately.
Bug 200451447
Jira VQRM-5069
Change-Id: I354d984f6c44482e4576a173fce1e90ab52283ac
Signed-off-by: aalex <aalex@nvidia.com>
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
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Rename gk20a/dbg_gpu_gk20a.c to common/debugger.c and make it a
separate common unit
Also rename gk20a/dbg_gpu_gk20a.h to include/nvgpu/debugger.h
We had two different HALs for debugger - gops.debugger and
gops.dbg_session_ops
Combine them into one single HAL gops.debugger and remove
gops.dbg_session_ops
Rename all exported APIs from debugger.h to be in the form of
nvgpu_*()
Jira NVGPU-1013
Change-Id: I136dc7786e3b2065921eb03b99f16049212f3cd2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1920075
Reviewed-by: Sachin Jadhav <sachinj@nvidia.com>
Tested-by: Sachin Jadhav <sachinj@nvidia.com>
For a long time now, the ALLOC_GPFIFO_EX channel IOCTL has done much
more than just gpfifo allocation, and its signature does not match
support that's needed soon. Add a new one called SETUP_BIND to hopefully
cover our future needs and deprecate ALLOC_GPFIFO_EX.
Change nvgpu internals to match this new naming as well.
Bug 200145225
Change-Id: I766f9283a064e140656f6004b2b766db70bd6cad
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1835186
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When turning off CONFIG_DEBUG_FS, there are build errors:
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o: In function `nvgpu_fecs_trace_init_debugfs':
os_ops_gp106.c:(.text+0x8): multiple definition of `nvgpu_fecs_trace_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp10b.o:os_ops_gp10b.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o: In function `gp106_therm_init_debugfs':
os_ops_gv100.c:(.text+0x0): multiple definition of `gp106_therm_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gp106.o:os_ops_gp106.c:(.text+0x0): first defined here
drivers/gpu/nvgpu/os/linux/os_ops_tu104.o: In function `gv100_clk_init_debugfs':
os_ops_tu104.c:(.text+0x0): multiple definition of `gv100_clk_init_debugfs'
drivers/gpu/nvgpu/os/linux/os_ops_gv100.o:os_ops_gv100.c:(.text+0x10): first defined here
This is because those functions aren't marked as static.
So this patch just simply fixes the bug.
Bug 2284925
Change-Id: I1da39345c653dfb50c509adb0c822b4657646c56
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929355
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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The chid member of the channel_gk20a struct was being used as a unsigned
value. By being declared as an int, it was causing MISRA 10.3 violations
for implicit assignment of different types.
JIRA NVGPU-647
Change-Id: I7477fad6f0c837cf7ede1dba803158b1dda717af
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918470
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Move the wait_cmd_buffer programming for channel_sync->wait_fd to
channel_sync.c. nvgpu_os_fence->program_waits
interface is now removed. channel_sync can directly retrieve
syncpt/semaphore from the interfaces of struct nvgpu_os_fence_syncpt
and struct nvgpu_os_fence_sema and use it for the wait programming.
Also, change int to u32 for some variables such as num_fences,
max_wait_size and wait_cmd_size.
Jira NVGPU-1093
Change-Id: I19c1b10d676caff49ce57861091f7f0ea65e7676
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829719
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channel_sync->wait_fd depends upon nvgpu_os_fence->program_waits which
invokes a channel_sync method and this leads to a circular dependency.
In order to resolve the above, constructed struct nvgpu_os_fence_sema and
struct nvgpu_os_fence_syncpt with interfaces that support conversion
between struct nvgpu_os_fence to above. Also, added the following
interfaces for retrieving syncpts and semaphore from the above structs
respectively.
void nvgpu_os_fence_sema_extract_nth_semaphore(...)
int nvgpu_os_fence_sema_get_num_semaphores(...)
void nvgpu_os_fence_syncpt_extract_nth_syncpt(...)
int nvgpu_os_fence_syncpt_get_num_syncpoints(...)
These enable channel_sync code to directly program the cmd_bufs
based on the syncpts and semaphore received using the above APIs
instead of the current state of doing the wait programming from
within nvgpu_os_fence's interfaces.
Jira NVGPU-1093
Change-Id: Ie411f0ba60bca38f66a0024f5dfca03ef0b836eb
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827475
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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struct gk20a from gk20a.h needs defination of struct gk20a_ce_app
and ce2_gk20a.h needs defination of struct gk20a. This creates
a circular dependency.
Fix this by making gk20a_ce_app a pointer to skip knowing the
complete type details and using forward declarations for struct
gk20a_ce_app and struct gk20a.
The gk20a_ce_app pointer is alloc'ed in gk20a_init_ce_support()
and free'ed in gk20a_ce_destroy.
JIRA NVGPU-611
Change-Id: I4d62d5f2b2d1492db73bae69f90a1fe5586fba76
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917945
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new separate unit common/perf/cyclestats_snapshot.c and add
corresponding header file include/nvgpu/cyclestats_snapshot.h
This unit is h/w independent and simply calls gops.perf.* HALs
exposed by perf unit to do the h/w configurations
Also remove gv11b/css_gr_gv11b.* files as h/w specific sequence
implemented in them is already moved to perf unit
Rename all cyclestats_snapshot HALs in the form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I303f6becb313ac918e06c495a5fe299947a1f0b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1916652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add sysfs nodes to manage power of dGPU. Writing
pci dev name to poweroff/poweron sysfs node powers
off/on dGPU.
The format of pci dev name is DDDD:BB:DD.F i.e.
domain:bus:device.function
echo 0001:01:00.0 > /sys/bus/pci/drivers/nvgpu/poweroff
echo 0001:01:00.0 > /sys/bus/pci/drivers/nvgpu/poweron
The permissions of nodes are set such that only root
user can write to the sysfs node to control dGPU power
state.
JIRA NVGPU-1100
Change-Id: I904881cab58c5f553e94510a3a10000194238433
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1749848
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
