This change fixes a number of This is a MISRA 10.3 rule violation due to
the implicit casts of sizeof() to u32's. This change adds u32 casts to
each of these violations. This should be safe because a 4GB type size
would be very unlikely in this driver.
JIRA NVGPU-1008
Change-Id: Icb6dd719b167fd48b86d89837897f1501fd24794
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959429
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Some buffers like userd are physically addressed. If nvlink is
enabled, or device is not iommuable, this requires buffer to be
physically contiguous.
Add NVGPU_DMA_PHYSICALLY_ADDRESSED to identify such buffers, in
order to force physically contiguous allocation, only in above
cases.
Bug 2422486
Change-Id: I6426e23b064904e812e6b33e6d706391648a51ae
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ie3d1a46c082d7589ea5d00c3d769086f046ae101
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1829916
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Add gk20a_channel_from_id() to retrieve a channel, given a raw channel
ID, with a reference taken (or NULL if the channel was dead). This makes
it harder to mistakenly use a channel that's dead and thus uncovers bugs
sooner. Convert code to use the new lookup when applicable; work remains
to convert complex uses where a ref should have been taken but hasn't.
The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is
returned for such IDs. This is often useful and does not hurt when
unnecessary.
However, this does not prevent the case where a channel would be closed
and reopened again when someone would hold a stale channel number. In
all such conditions the caller should hold a reference already.
The only conditions where a channel can be safely looked up by an id and
used without taking a ref are when initializing or deinitializing the
list of channels.
Jira NVGPU-1460
Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as
boolean in the controlling expression of if and loop statements.
Changed few enums into macros because they were used in bit-shift &
bitwise operations and MISRA rule 10.1 forbids the usage of signed
types in bit-shift & bitwise operations.
JIRA NVGPU-1020
Change-Id: Ibc81c1e951342a5faf422ea73d13ef583535b768
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions. Also set pointer to NULL when freed.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I21ff1ae93ac7b92a71502f97785252c04964e72f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954003
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The BIOS_GET_FIELD() macro does a simple bit mask and shift operation.
The value of this macro is assigned to variables of different data
types. Casting the macro to different data types causes MISRA rule
10.8 violations. This issue is resolved by doing the cast inside the
macro and returning the value in the correct data type. These changes
also clear MISRA rule 10.1, 10.3 and 10.4 violations.
JIRA NVGPU-992
JIRA NVGPU-1006
JIRA NVGPU-1010
Change-Id: I16345865d107f0ff0b34daa8b17d7d576eafcfbf
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936357
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The return type of the function pointer *calc_global_ctx_buffer_size()
is changed from int to u32 and all its implementations.
The arg type of size in *set_big_page_size() is changed from int to
u32 and all it implementations. These changes are necessary because
size should be an unsigned value.
JIRA NVGPU-992
Change-Id: I3e4cd1d83749777aa8588a44a48772e26f190c4d
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950503
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Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm and vpr flag instead of the whole channel as
only those are needed.
Jira NVGPU-1149
Change-Id: Ic0921ccaf65f208105b25f08f8d7b581a56b40fe
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations in posix code by casting them
to an appropriate type or using the relevant BITxx() macros.
JIRA NVGPU-666
Change-Id: Ibc428ee71977685f413ca0f972efeff34268da62
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1954303
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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MISRA rule 8.2 requires that all function prototypes have
return type mentioned and have named parameters. The prototype
for sort function is in violation of this rule. This patch will
fix the same by naming the parameters.
JIRA NVGPU-861
Change-Id: I493d36e9d83234233da1d3d65d0e4ce4881d026d
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1947843
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Currently, we assume the VBIOS base ROM size is 64KB. We use
this hardcoding to determine when the bios offset lies beyond
the Base ROM.
This assumption fails on Turing when we try to parse the
clock programming tables which are present in expansion ROM
but have an offset < 64KB.
Remove the hardcoding by storing the base rom size.
Also, replace some magic numbers with macros for readability.
Bug 200455202
Change-Id: Ic4b8c113cfb5ee3e860f7692f5851cdd0ab45d50
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955973
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- For debugging events to user we need a
separate logging type for QNX. This is required
as earlier we were using nvhost logging APIs
but now we are removing all dependency from
nvhost. Linux too can use this type if required.
Change-Id: I57a2a566be9208bb444cba72645eda06acc3d496
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955222
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The problem here, and the solution, requires some background
so let's start there.
During page table programming page directories (PDs) are
allocated as needed. Each PD can range in size, depending on
chip, from 256 bytes all the way up to 32KB (gk20a 2-level
page tables).
In HW, two distinct PTE sizes are supported: large and small.
The HW supports mixing these at will. The second to last level
PDE has pointers to both a small and large PD with
corresponding PTEs. Nvgpu doesn't handle that well and as a
result historically we split the GPU virtual address space
up into a small page region and a large page region. This
makes the GMMU programming logic easier since we now only have
to worry about one type of PD for any given region.
But this presents issues for CUDA and UVM. They want to be
able to mix PTE sizes in the same GPU virtual memory range.
In general we still don't support true dual page directories.
That is page directories with both the small and large next
level PD populated. However, we will allow adjecent PDs to
have different sized next-level PDs.
Each last level PD maps the same amount. On Pascal+ that's
2MB. This is true regardless of the PTE coverage (large or
small). That means the last level PD will be different in
size depending on the PTE size.
So - going back to the SW we allocate PDs as needed when
programming the page tables. When we do this allocation we
allocate just enough space for the PD to contain the
necessary number of PTEs for the page size. The problem
manifests when a PD flips in size from large to small PTEs.
Consider the following mapping operations:
map(gpu_va -> phys) [large-pages]
unmap(gpu_va)
map(gpu_va -> phys) [small-pages]
In the first map/unmap we go and allocate all the necessary
PDs and PTEs to build this translation. We do so assuming a
large page size. When unmapping, as an optimzation/quirk of
nvgpu, we leave the PDs around. We know they may well be used
again in the future.
But if we swap the size of the mapping from large to small
then we now need more space in the PD for PTEs. But the logic
in the GMMU coding assumes if the PD has memory allocated then
that memory is sufficient. This worked back when there was no
potential for a PD to swap in page size. But now that there is
we have to re-allocate the PD doesn't have enough space for
the required PTEs.
So that's the fix - reallocate PDs when they require more
space than they currently have.
Change-Id: I9de70da6acfd20c13d7bdd54232e4d4657840394
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933076
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I2e7ad84751aa8b7e55946bb1f7e15e4af4cbf245
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827823
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The clk module was using u8's and u32's for the regime ID. Since the
regime id is only a byte, just use u8's.
This eliminates MISRA rule 10.3 violations for implicit assignments to
different types.
JIRA NVGPU-1008
Change-Id: Id3d1394402b248818cf959b46cd48611755f6912
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946259
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There are places where function prototypes have been declared
using typedef. These are being considered as type mismatch
and flagged as MISRA rule 8.3 violations. This patch will
fix such cases by removing typedef for function declarations.
JIRA NVGPU-847
Change-Id: Ide72c53d7f3a2d8d5f088c42d8e0318b04d2e9be
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
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Currently has_timedout variable is protected by wmb at places
where it is being set and there is no correspoding rmb whenever
has_timedout variable is read. This is prone to errors for
concurrent execution. This change is supposed to fix this issue.
Rename has_timedout variable of channel struct to ch_timedout.
Also to avoid rmb every time ch_timedout is read,
ch_timedout_spinlock is added to protect ch_timedout
variable for taking care of concurrent execution.
Bug 2404865
Bug 2092051
Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.
JIRA NVGPU-847
Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: Ie6af057f6948ac3b67f1c8beb7cce95165bd48d4
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939227
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I65c37f6b515aaa10c5945e9b68180e92e40c1f61
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1939226
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I70a2dded2e6cd5c04b54bf208d77a8d40a8f7af0
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933534
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I1d71d7e62ce1a6331a4f33740a814bb3aa0309aa
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933533
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I1bca4258614d4c5feb75a47b3a98d2f385731bfb
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933532
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: I7e39bc38b620c8a521a4a75d41379b8fb107f347
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933531
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MISRA Rule 12.2 states that the right hand operand of a shift operator
shall lie in the range zero to one less than the width in bits of the
essential type of the left hand operand.
The left hand operands in these shift operations are unsigned integer
literals which can be u16 or u32 dependent on the platform.
The maximum value of right hand operand of the shift is 31, so make
the left hand operand a u32 using the U32() Macro.
JIRA NVGPU-1054
Change-Id: Ia0f4bcf1a8629d77ff9ae3c75e683ebd34929d7f
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1933514
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I7ced14d6629e033b0ccef3a93a3dbf099e43ba4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946662
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gk20a.h depends on definition of struct therm_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I67010a979ed7f874070796dd834b9b3d1d9dad4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I2442eba6231c52cca2db0f0ed42cf0a419bc4c10
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945307
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945286
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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.
Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.
JIRa NVGPU-596
Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA rule 12.2 states that the right hand operand of a shift
operator shall lie in the range zero to one less than the width
in bits of the essential type of the left hand operand. This
patch will fix these violations by casting them to an appropriate
type or using the relevant BITxx() macros.
JIRA NVGPU-666
Change-Id: I57b6081e9bd98c45ca9f7aa5f35e1d2d66ed0134
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945655
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.
JIRA NVGPU-1020
Change-Id: I6a756ee1bbb45d43f424d2251eebbc26278db417
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936334
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I36494e84ee6cd4a108e2a539f48f102e47e2f7f4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926820
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I4c04e2720a3b068909cc4af6847d4718568c13ea
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822740
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822587
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
