Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525714
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Replace securegpccs boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_SECUREGPCCS
Jira NVGPU-74
Change-Id: I487aa5e8545027a3b5bbe33ce68b2715cc2eb39a
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514096
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522554
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
priv_ring sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Idee9e8a3a5bfa65b350f0e9fb14c4364c4d6f1d2
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514103
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
bus sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514661
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
css sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Change-Id: I04177d6c9eb4f3c433d493c815ad15cf7b755910
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514206
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
- Created HAL to configure gpc mmu unit for gv11b.
- Earlier chips needs writes to NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS
register to know supported number of LTCS by reading NUM_ACTIVE_LTCS
but gv11b support auto update from fuse upon reset, so skipped
LTCS update for GPCS & skipping helps to fix compression failure
issue.
Bug 1950234
Change-Id: I628af7d1399e4fe3126895e3a703a19147f7a12f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517733
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
fault_addr "0" is not supposed to be fixed ever.
For the first time when prev = 0, next = 0 and
fault addr is also 0 then handle_mmu_fault_common will
not be called. Fix by checking fault_addr not equal to 0
Bug 200277163
Change-Id: I532bca54a85e540415b9f5f5e71daec9cf0e0619
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields
in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is
used by the user space driver to disable enough ROP optimizations
to maintain ZBC state of target tiles.
Bug 1942454
Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1516205
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch covers the debug
and dbg_session_ops sub-modules of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514820
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Move non-function pointer members out of the mc substruct of
gpu_ops. Ideally gpu_ops will have only function ponters, better
matching its intended purpose and improving readability.
gops.mc.intr_mask_restore is now mc_intr_mask_restore
Jira NVGPU-74
Change-Id: I789087704fb5e6338f6010f18457948d0ee6c630
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509604
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the mc
sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1509603
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
falcon sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514013
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This is needed as BAR1 support is removed and
there is no way to know if gpu successfully accessed memory.
JIRA GPUT19X-115
Change-Id: I5d18b6bf73e11b103d1951d2e28fb1f895e72c85
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1515813
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Host will no longer receive replayable or non-replayable fault requests.
MMU will handle both types of fault reporting. This means that Host will no
longer automatically disable scheduling or preempt a PBDMA when an engine
page faults. After fault happens, engine will stall on its own fault and
will not context switch until the fault is serviced
JIRA GPUT19X-7
Change-Id: I8039e6f50d87f43e101d1372faa5ca6fb739036e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493417
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
HUB reports following memory sub-system interrupts:
a) ACCESS_COUNTER_NOTIFY:
GET != PUT for access counter notify buffer
b) ACCESS_COUNTER_ERROR:
HUB received a NACK (BAR2 fault) when writing the
notify buffer out to memory
c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY:
Uncorrected ECC error detected by HUB MMU
d) MMU_REPLAYABLE_FAULT_NOTIFY:
GET != PUT for replayable fault buffer
e) MMU_REPLAYABLE_FAULT_OVERFLOW:
Overflow when writing to the replayable fault buffer
f) MMU_NONREPLAYABLE_FAULT_NOTIFY:
GET != PUT for non-replayable fault buffer
g) MMU_NONREPLAYABLE_FAULT_OVERFLOW:
Overflow when writing to the non-replayable fault buffer
h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU
This change is to :
-Detect other fault notify
-Copy fault info from fault snap register for other fault notify
interrupt
-Detect and handle nonreplay/replay fault notify and fault overflow
-Copy fault info from fault buffer for nonreplay/replay fault
-Print fault info
JIRA GPUT19X-7
JIRA GPUT19X-12
Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1493394
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
-implement mm ops init_mm_setup_hw
This will also call *fault*setup* that will do s/w and h/w
set up required to get mmu fault info
-implement s/w set up for copying mmu faults
Two shadow fault buffers are pre allocated which will be used to copy
fault info. One for copying from fault snap registers/nonreplayable h/w
fault buffers and one for replay h/w fault buffers
-implement s/w set up for buffering mmu faults
Replayable/Non-replayable fault buffers are mapped in BAR2
virtual/physical address space. These buffers are circular buffers in
terms of address calculation. Currently there are num host channels
buffers
-configure h/w for buffering mmu faults
if s/w set up is successful, configure h/w registers to enable
buffered mode of mmu faults
-if both s/w and h/w set up are successful, enable corresponding
hub interrupts
-implement new ops, fault_info_buf_deinit
This will be called during gk20a_mm_destroy to disable hub intr and
de-allocate shadow fault buf that is used to copy mmu fault info during
mmu fault handling
-implement mm ops remove_bar2_vm
This will also unmap and free fault buffers mapped in BAR2 if fault
buffers were allocated
JIRA GPUT19X-7
JIRA GPUT19X-12
Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1492682
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add gv11b implementation of gpu_phys_addr() that checks the t19x
GMMU attributes struct to determine if L3 allocation should be
enabled. If L3 alloc is enabled then a special physical address
bit is set.
Add flag NVGPU_AS_MAP_BUFFER_FLAGS_L3_ALLOC to struct
nvgpu_as_map_buffer_ex_args so that User space can add a hint to
allocate buffer in L3 cache
Jira GPUT19X-10
Bug 200279508
Change-Id: I1bb9876a670b252980922aa50e3e69b802be137f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master/r/1512602
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
gr_gk20a_handle_sm_exception is initialized to
handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception
is initialized to gr_gv11b_handle_tpc_sm_ecc_exception
to handle sm ecc errors per tpc.
JIRA GPUT19X-75
JIRA GPUT19X-109
Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514039
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch covers the lone
function pointers of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1510390
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC
Currently all subcontexts with in a tsg can have only
single address space.
Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for
selecting subctx id by client.
Bug 1842197
Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master/r/1511145
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Ia5c0a3d1dead9c6094ca28716c06929dd3461814
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512210
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I0ebbfdad73d6212997a21f9240f5d4bc2f28ab2f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512209
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: I46b7d58ed02710339aa27cd9db999aa60fbd4dd9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512208
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Instead of assuming mask_0 and mask_1 as consecutive registers,
use mask_1 and mask_0 registers for reading/writing sm dbgr warp
and bpt mask registers
JIRA GPUT19X-75
Change-Id: Ib6843d13828d899d4bd3f12bdf6701325ea760fd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511736
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
When Host receives a page fault signal from a CE, Host will immediately
set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel
and will trigger a preempt of the TSG/channel.
A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0
and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel.
If a TSG has a faulted channel, Host will not schedule the entire TSG
agin until all _FAULTED bits from channels in the TSG are cleared by SW.
This function will be required for ce page fault handling.
JIRA GPUT19X-46
JIRA GPUT19X-12
Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1509776
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
