- Added nvgpu_flcn_clear_halt_intr_status() to
Wait for halt interrupt status clear by
clear_halt_interrupt_status() HAL within timeout
- Added gk20a_flcn_clear_halt_interrupt_status()
to clear falcon controller halt interrupt status
- Replaced flacon halt interrupt clear with
nvgpu_flcn_clear_halt_intr_status() method
NVGPU JIRA-99
Change-Id: I762a3c01cd1d02028eb6aaa9898a50be94376619
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1511333
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
- Updated falcon controller HAL to support SEC2 falcon
& used "is_falcon_supported" flag to know the support on chip.
- Created falcon HAL flcn_gp106.c/h under gp106 to enable
support for SEC2 & inherited gk20a flcn support.
- Deleted SEC2 falcon related methods to make use of
generic flacon controller methods for SEC2.
- GP106 SEC2 code cleanup
NVPU JIRA-99
Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1510200
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Enabled GM20B GPCPLL revision C1 during internal calibration in order
to read calibration status and results.
Bug 1942225
Change-Id: I8fb5f43669bb308de7439792033f640d26f8a3dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1504228
(cherry picked from commit a5bed86858fe0e28482bea1a57ecd3085f146ad1)
Reviewed-on: https://git-master/r/1511085
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Samuel Payne <spayne@nvidia.com>
Tested-by: Samuel Payne <spayne@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Convert a few calls from dev_*() logging to nvgpu_*(). This reduces
dependency to Linux specific struct device pointer.
JIRA NVGPU-38
Change-Id: Ib51a6b1287db25b7dd4d164aec3ac75fa2801ebf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507929
GVS: Gerrit_Virtual_Submit
Make default big page size query a HAL op instead of per-platform
constant. This allows querying for default big page size without
accessing Linux specific gk20a_platform structure.
JIRA NVGPU-38
Change-Id: Ibfbd1319764fdae5fdb06700fb64d23f6f3dd01a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507928
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Remove gk20a support. Leave only gk20a code which is reused by other
GPUs.
JIRA NVGPU-38
Change-Id: I3d5f2bc9f71cd9f161e64436561a5eadd5786a3b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master/r/1507927
GVS: Gerrit_Virtual_Submit
Rename files, as they are not directly related to PMU.
They just send commands to PMU, similar to all other clock
change codes.
Bug 1921094
Change-Id: I4a67d4c950d995c68cfce464108cd36104f44080
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master/r/1508820
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Remove mem_config_idx from platform data, and instead let
HAL determine which memory configuration to use. For this
purpose, HAL may use PCI device identifiers, VBIOS version
and possibly RAMCFG strap register.
Bug 1929155
Change-Id: I6633e9e0c79728c8e3740f3f956b53b3abfc667b
Reviewed-on: http://git-master/r/1497812
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit b7141ff5441b7ea95f9826eb37ae869f408e1414)
Reviewed-on: https://git-master/r/1506584
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Remove mem_config_idx from platform data, and instead let
HAL determine which memory configuration to use. For this
purpose, HAL may use PCI device identifiers, VBIOS version
and possibly RAMCFG strap register.
Bug 1929155
Change-Id: I9fcd67ff407382839ff81470789043fae1c81283
Reviewed-on: http://git-master/r/1497813
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit 3f722945213bacfc5f6707059b9baccebd92cef1)
Reviewed-on: https://git-master/r/1506583
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Supply the log type argument as text from the table as the log format
string specifies for trace_printk.
Change-Id: I9e0f2dd8bffeeb0f8cbdba95d9969403d7161474
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master/r/1509334
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Depend on the main GK20A config for all subitems so that they get
grouped properly under the top level item in the menuconfig.
Also remove an extraneous CONFIG_ to make the trace printk config
visible in the menu when its deps are there.
Change-Id: I03ee5b8dff9ad02342ab31d0faad9549e8352059
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master/r/1509333
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.
- Created ops to do PMU engine reset & to
know the engine reset status
- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)
- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.
JIRA NVGPU-99
Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-Add sm input param for handle_sm_exception and
pre_process_sm_exception for gr ops/functions.
-Add functions to calculate gpc and tpc reg offsets.
-Add function to find SMs which raised SM exception.
JIRA GPUT19X-75
Change-Id: I257e7342ddabadb1556c9551c50a54d34b0f9d1e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1476108
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Remove dependency for nvgpu to invoke devfreq govenor on every
gk20a_busy/idle() call. This dependency was originally necessary to
track GPU load (busy vs idle) in software. However, since we currently
read the load GPU from HW/PMU there is no need to invoke the devfreq
governor in this path. Instead it can use timer-based polling.
Jira NVGPU-20
Change-Id: Id09f89a8a562ed49164a2e06dcbb901e4a46e7d5
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: https://git-master/r/1473140
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add vgpu support for ModeE perfbuffers
- VM allocation is handled by the kernel, with final mapping
handled by the RM server
- Enabling/disabling the perfbuffer is handled by the RM server
Bug 1880196
JIRA EVLR-1074
Change-Id: Ifbeb5ede6b07e2e112b930c602c22b66a58ac920
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master/r/1506747
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Remove the special cases for fmodel in the GMMU allocation code. There
is no reason to treat fmodel any different than regular DMA memory.
If there is no IOMMU the DMA api will handle that perfectly acceptably.
JIRA NVGPU-30
Change-Id: Icceb832735a98b601b9f41064dd73a6edee29002
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master/r/1507562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ltc
sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I1110e301e57b502cf7f97e6739424cb33cc52a69
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507564
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Remove ltc_common.c and integrate the included functions
into device specific ltc_gXXXX.c files. Merge non-device reg
definition dependent ltc functions into ltc_gk20a.c/h.
Prior to this patch, ltc_common.c was being directly included
into the device specific ltc source files as a workaround to
allow different devices to share the same code but still include
in different hw reg definitions.
Given that this approach was not adopted for other
systems, this code has been separated out for readability and
consistency.
Jira NVGPU-74
Change-Id: I4eea301927418532cc150b029535f165928cab89
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
It'll let gpu tests pass by using sem before enabling syncpt.
Especially for vgpu, the plat data is shared across different GPUs, so
we can use dt to override and disable syncpt.
Jira VFND-3796
Change-Id: I2cc32a1ea1cc1097047427eb1e52ec50c3a0bf90
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/1507494
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
- set nvgpu_flcn_reset() to point to gk20a_pmu_reset()
- set PMU interrupt using nvgpu_flcn_enable_irq()
- replace pmu_idle with nvgpu_flcn_wait_idle()
JIRA NVGPU-57
Change-Id: I50d0310ae78ad266da3c1e662f1598d61ff7abb6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1469478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
