Commit Graph

61 Commits

Author SHA1 Message Date
rmylavarapu
eaf6aa07f9 gpu: nvgpu: Fix MISRA viaolation in clk_prog unit
Fixed following MISRA violations:
-MISRA C-2012 Rule 11.3
-MISRA C-2012 Rule 16.1

NVGPU-3223

Change-Id: I7587477e03bacc974e0243041347cb76d7ee7348
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108483
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 04:05:59 -07:00
rmylavarapu
5ed6909d07 gpu: nvgpu: Fix MISRA violations in clk_domain unit
Fixed following MISRA violations:
-MISRA C-2012 Rule 11.3
-MISRA C-2012 Rule 16.1

NVGPU-3222

Change-Id: I9dcb6c5c3fab6be0135919dfbcf273f7ee44949b
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107418
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-05-06 04:05:25 -07:00
Vedashree Vidwans
c90fcbae2a gpu: nvgpu: fix MISRA Rule 2.2 no dead code
MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.

This patch fixes some of these reported violations.

Jira NVGPU-858

Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
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2019-05-02 15:56:56 -07:00
rmylavarapu
3af5242bb0 gpu: nvgpu: Clean clk_vf_point unit
-Removed clk_fll.h file include and calling the
function using pointer.
-Removed whitespaces.

NVGPU-1965

Change-Id: Ie0678961e4261be89c72a6fb99c00e275437eb29
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109919
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-02 05:26:48 -07:00
rmylavarapu
368b1ccf50 gpu: nvgpu: Remove GV100 code from vf_point unit
Removed GV100 code from clk_vf_point unit.

NVGPU-1965

Change-Id: Ibed5d3495fd75025a60dc72dc758d03d6260511d
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107226
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-02 05:25:09 -07:00
Sagar Kamble
1262df6d70 gpu: nvgpu: fix misra rule 5.7 violations in pmuif headers
Identifier names used were already used to represent types. Fix those.
for e.g. pwr_channel in nv_pmu_pmgr_pwr_channel_union.
pmu_init_msg identifier name changed to init_msg as that is used to
represent a type.

JIRA NVGPU-3272

Change-Id: I887b66f08df1e00803d872873f6447f563675d44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108548
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2019-05-02 04:18:49 -07:00
Nicolas Benech
3a3d78adf2 gpu: nvgpu: fix MISRA 17.7 in nvgpu.common.pmu.clk*
MISRA Rule-17.7 requires the return value of all functions to be
used. Fix is either to use the return value or change the function
to return void. This patch contains fixes for all 17.7 violations
in the nvgpu.common.pmu.clk.* units.

JIRA NVGPU-3035

Change-Id: I13863f43c6bea76917978a12df091a672a3e5098
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108887
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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2019-05-01 10:05:03 -07:00
Abdul Salam
bc10ef568e gpu: nvgpu: Restructure boardobjgrpmask unit
This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-04-29 11:04:46 -07:00
rmylavarapu
be0eabeb6c gpu:nvgpu: Move nvgpu_clk_pmupstate into nvgpu_pmu
Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.

NVGPU-3220

Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-04-26 02:55:02 -07:00
rmylavarapu
6e67eec8d5 gpu:nvgpu: Restructure P-state unit
Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.

Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.

NVGPU-1958

Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
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2019-04-23 07:14:09 -07:00
Sagar Kamble
1eb8abe0de gpu: nvgpu: fix MISRA rule 5.7 and 4.7 violations
nvgpu_pmu_cmd_post return value was not used in some call sites in
pmu perfmon. data structures were forward declared where not reqd
are removed and header included where needed.

JIRA NVGPU-1971

Change-Id: I8714ed138d1c0b897540b624ae73c70c0a0318e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-04-13 12:34:01 -07:00
Sagar Kamble
bcbc87dc2e gpu: nvgpu: move pmu interface headers to include/nvgpu/pmu
Interface header files for PMU features are now moved under PMU header
files directory include/nvgpu/pmu. And fix bulk of coding style issues.
Update header file names and guards.

JIRA NVGPU-1971

Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093006
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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2019-04-13 12:33:52 -07:00
rmylavarapu
ad003964d3 gpu: nvgpu: Clean clk_freq_controller unit
-Removed nvgpu_ tag for clk_freq_ctlr_rpc_pmucmdhandler
function and made static as it is used only by
clk_freq_controller unit.
-Removed whitespaces
-Remvode nvgpu_clk_freq_controller_load as it is
not used.

NVGPU-1969

Change-Id: I7fc46489c64d00eaf57e466fbc18ea4b1682a5b5
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092272
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-04-11 03:53:38 -07:00
Abdul Salam
364c780469 gpu: nvgpu: Remove cyclic dependency between arb & vf
Remove cyclic dependency between arb and vf point units.
Remove the header files and call the functions with funciton pointers.
Remove lpwr.h as they are not used.

Jira: NVGPU-1966

Change-Id: I64b1eb810fc343d8930857793f0d00a683cfd05d
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094043
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2019-04-10 13:55:04 -07:00
rmylavarapu
295ff82fc9 gpu: nvgpu: Clean clk_vin unit
-Removed nvgpu_ tag for clk_vin_rpc_pmucmdhandler
function and made static as it is used only by
clk_vin unit.
-Removed Whitespaces
-Fix ACV errors

NVGPU-1964

Change-Id: I05634a5128d0c73b15a22786efcc164270eb8668
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090553
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-04-08 17:33:54 -07:00
rmylavarapu
0d901ede6e gpu: nvgpu: Remove ADC Cal Type ADC_CAL_V10 support
-Removed ADC_CAL_V10 support as this is no longer used in our
VBIOS. 

NVGPU-1964

Change-Id: I8735477650c29cfa04a4c529bce482013a10cd01
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089560
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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2019-04-08 17:33:46 -07:00
rmylavarapu
ff69c5c210 gpu: nvgpu: Restructure clk_fll unit
-Removed whitespaces
-Removed nvgpu_ tag for clk_get_vbios_clk_domain
function and made it as static because it is called
by clk_fll unit.
-Removed FLL_DESCRIPTOR_HEADER_10_SIZE_4 macro
which is no longer used.

NVGPU-1967

Change-Id: I74758738b3bc582514d0344592647cf69d1afe0f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086375
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-04-08 00:47:25 -07:00
Sagar Kamble
16953b9622 gpu: nvgpu: prepare pmu command unit
pmu_ipc.c had functionality for rpc response handling and message cond
checks. This patch moves them to msg unit. And prepare cmd.h to group
together structs and functions related PMU commands.

JIRA NVGPU-1970

Change-Id: Iec5d72d02ab3ee51963631c828b301c56af8dc48
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079146
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2019-04-05 05:06:22 -07:00
Sagar Kamble
499da418c1 gpu: nvgpu: prepare pmu sequences unit
PMU commands and messages management is based on sharing the data
through sequences. Functions for sending commands/allocating
payload update sequence data acquiring lock and those for
working on received messages read/free the sequence data
releasing lock.

JIRA NVGPU-1970

Change-Id: I4204dbfbf6f57b0f5a7016aed74ffea6e91ab06c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079141
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2019-04-05 05:05:11 -07:00
Sagar Kamble
2250ccbe35 gpu: nvgpu: remove seq_desc parameter of pmu callbacks
This parameter isn't used by the callbacks and plan is to keep
access to sequence struct members within IPC units.

JIRA NVGPU-1970

Change-Id: Idcdf4e8f493386be38a5c8a63a741ac06ce1b06e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079140
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-04-05 05:04:56 -07:00
Sagar Kamble
817e8f28c1 gpu: nvgpu: remove unneeded seq_desc and msg parameter of *_pmu_cmd_post functions
These parameters are not required. Removing those will simplify the
refactoring of the IPC units.

JIRA NVGPU-1970

Change-Id: Id381ba18b87ea21860c05cad1fa64dad8e1a59a1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079139
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-04-05 05:04:46 -07:00
rmylavarapu
5965b7ebb4 gpu: nvgpu: Restructure of clk_prog unit
Changes: Removed whitespaces

NVGPU-1968

Change-Id: Ie1471add5500a15a2a0c564024555af0d554e473
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087688
Reviewed-by: Automatic_Commit_Validation_User
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2019-04-03 00:15:12 -07:00
rmylavarapu
e117806371 gpu: nvgpu: Restructure of clk_prog unit
Changes: Removed GV100 code

NVGPU-1968

Change-Id: I4b8450632c8d0b34463d3891a877799b6133098a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081898
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-04-03 00:14:48 -07:00
rmylavarapu
6177eacc71 gpu: nvgpu: Restructure clk_domain unit
Changes: 
1) Removed PSTATE30 code.
2) Whitespace clean-up.

NVGPU-1962

Change-Id: I258ba5b5711c642de4ec9af98f08c02ff6c45efc
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2078148
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-04-02 03:28:48 -07:00
rmylavarapu
722fe30d50 gpu: nvgpu: Restructure clk unit
Description:
nvgpu_clk_pmupstate is the global structure in clk units. It is declared
in clk.h and all clk units will include clk.h header.
nvgpu_clk_pmupstate struct will have structure pointers to all clk units
and will include genereic function pointers which are  used by most clk
units. The reason why the function pointers is defined in this sturct,
and not included inside g->ops is because, these are only clk specific
functions and rest of the driver code is not dependent on this.

Each unit will have init function to allocate memory for its structure
and will initialize its local functions.

Changes:
1) Introduced nvgpu_clk_pmupstate in clk.h file. All the changes needed
   to call the above struct from individual clk units.
2) Removed cyclic dependency headers in clk units by calling function
   through pointers defined in clk.h.
3) Initialization of each unit is done in respective unit instead of
   doing it in clk unit. Added *_init_pmupstate and *_free_pmupstate to
   individual clk units.
4) Each unit clean up will be done separately while refactoring that
   unit.

NVGPU-1963
NVGPU-2965

Change-Id: Iee79d7a812b62407252636057b104f952c94a229
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033537
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2019-03-29 05:34:26 -07:00
Seema Khowala
a8587d5ee3 gpu: nvgpu: rename gr_idle_timeout_default to poll_timeout_default
Rename gr_idle_timeout_default to poll_timeout_default

Rename NVGPU_DEFAULT_GR_IDLE_TIMEOUT to
NVGPU_DEFAULT_POLL_TIMEOUT_MS

Rename gk20a_get_gr_idle_timeout to nvgpu_get_poll_timeout

JIRA NVGPU-1313

Change-Id: I17314f0fa4a386f806f6940073649a9082ee21ad
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083130
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2019-03-28 16:07:45 -07:00
Abdul Salam
2c9eddf719 gpu: nvpgu: Set voltage step size to 6250uV
Currently volt step size for freq calculation is 2*lut_step_size_uv.
This causes P0 max freq to be dropped at temperature corners.
At higher temperature same voltage cannot give P0 Max and needs more volt.
With lut_step_size_uv we get more fine grained freq values with P0 Max.

Bug 2540811

Change-Id: I8851513ec07672c94dc166ea80d5ef386907aa91
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081711
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GVS: Gerrit_Virtual_Submit
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2019-03-27 14:36:02 -07:00
Abdul Salam
e943e6278a gpu: nvgpu: Restructure nvgpu.common.volt
This patch does the following.
1. Remove unused functions from volt_pmu.c.
2. Append public functions with nvgpu.
3. Remove GP106 functions and rename TU104 to generic functions.
4. Rename volt struct from gpu_ops.
5. Remove the unused volt.h header file.
6. Make local functions as static and put in order.
7. Remove unused inclusion on header files.
8. After 4, generic functions can be called directly instead of g->ops.

Jira NVGPU-1956

Change-Id: Icaea0ca817d37cccfc09241baa2f047ec2688169
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2076535
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-21 10:55:29 -07:00
Mahantesh Kumbar
c7ce4a4465 gpu: nvgpu: disable VFE frequency margin request
Disabled VFE frequency margin request to PMU as TU104 don't support
this feature currently. 

Bug 200499055

Change-Id: I8e217cae9a0cbb6f388fb3376efc22f6e40e5c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034728
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-07 22:54:42 -08:00
Philip Elcan
767dc82ccf gpu: nvgpu: clk: clean up casts for MISRA 10.3
In a previous commit the macro NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET was
updated to be defined with the cast. This eliminates the need to cast
when used in clk.c.

JIRA NVGPU-1008

Change-Id: Iea2a42f3ec0d1c9e8e8e71f69bb87fc8231ad8da
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2028634
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-07 11:44:26 -08:00
Philip Elcan
967f6defd0 gpu: nvgpu: clk: fix MISRA 10.3 violations
This fixes MISRA 10.3 violations for assignment to narrower or different
type with the use of for_each_set_bit macros.

JIRA NVGPU-1008

Change-Id: If90428047115b09c4172252857a6b22a86197b77
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027653
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-03-07 11:43:45 -08:00
Abdul Salam
492b3e05fe gpu: nvgpu: Reorganize clk_arb unit
As a part of regoranizing clk_arb code, This patch does the folowing
1. Move clk_arb HAL files under common/clk_arb unit.
2. Move clk_arb from common/pmu to common/clk_arb.
3. Append public functions with nvgpu.
4. Make local functions as static.

Jira NVGPU-1966

Change-Id: If45c3dbfc4bbe74fe8d30e33e64894d553f3cda5
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027335
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-28 07:34:40 -08:00
Abdul Salam
6a6c2ec0b0 gpu: nvgpu: Create common.pmu.clk.vf_point unit
This patch does the following.
1. Append public functions with nvgpu.
2. Move public functions & structure to include/pmu/clk.
3. Remove inclusion of HW header files in common.
4. Move FREQ_STEP_SIZE_MHZ to clk_prog.h as it is used there.
5. Fix 16.3 and 11.3 Misra Violations.

Jira NVGPU-1965

Change-Id: I268d257d6de9c986e456a666cf6d633fe10fc440
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2024992
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-28 07:34:31 -08:00
Abdul Salam
4c8a320f2c gpu: nvgpu: Add support for guaranteed frequency
1. Check for volt margin and freq margin in VBIOS.
2. If it is valid (!255) send RPC to get margin, else ignore.
3. Get freq margin followed by volt margin.
4. Add this to requested voltage/freq based on output type.

Bug 200492048

Change-Id: I513c6cdebcc7c2db348e3be37258e7657b48eb7e
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021974
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-26 07:55:18 -08:00
Philip Elcan
c02bccd6db gpu: nvgpu: cond: use u32 for COND_WAIT timeout
The type for the timeout parameter to the NVGPU_COND_WAIT and
NVGPU_COND_WAIT_INTERRUPTIBLE macros was too weak. This updates these
macros to require a u32 for the timeout.

Users of the macros are updated to be compliant as necessary.

This addresses MISRA 10.3 violations for implicit conversions of types
of different size or essential type.

JIRA NVGPU-1008

Change-Id: I12368dfa81b137c35bd056668c1867f03a73b7aa
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2017503
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-21 10:24:24 -08:00
rmylavarapu
8daafcbae8 gpu: nvgpu: Restructuring clk.h into different units
Changes:
1) Separated clk.h which is in /nvgpu/include/pmu
 into different units
2) Renamed global functions

Intention: At present /nvgpu/include/pmu/clk.h
consists of structures and functions of different
clock units. It is difficult to work on individual
clk units if this file is not separated into
individual units. All stucts and functions in clk.h
are seperated into different clk units.
Individual private clk units were not touched.
Post this patch, the sebsequent patches would make
changes in the individual clk units.

NVGPU-2707

Change-Id: I7bf9fab38a73bceb451291530a67c70ed343b0cb
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2021704
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-19 01:55:54 -08:00
Abdul Salam
6945209418 gpu: nvgpu: Add unified check for clk_arb support
Currently clk_arb needs PSTATE to be true for dGPU.
Setting PSTATE only FALSE, causes issue as clk_arb fails.
There is no such dependency of PSTATE on iGPU.
Making it unified with a call to check_clk_arb_support().
This call is implemented based on its dependency in iGPU, dGPU.
check_clk_arb_support returns true if supported, else false.

Jira NVGPU-1948

Change-Id: I108dc12bd6ad8d0e074352080c978b7dda9bee05
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014775
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-12 08:54:49 -08:00
Philip Elcan
2beed190a7 gpu: nvgpu: clk: update type for size param
Update interfaces to use size_t to align with boardobj_construct_super()
and avoid unnecessary casts.

JIRA NVGPU-1008

Change-Id: Ib4539239363f106f1fba8d523072b28d0b8369ad
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011434
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-11 14:04:25 -08:00
Mahantesh Kumbar
9dda177510 gpu: nvgpu: use common BOARDOBJGRP SET/GET_STATUS construct
Currently there are multiple BOARDOBJGRP SET/GET_STATUS construct
added to support for 3.5 pstate, _pack boardobjs & to fetch respective
offset/size of boardobjs from PMU super surface.
With super surface member descriptor(SSMD) support, boardobj offset
will be part of SSMD lookup table which is part of PMU super surface
buffer & updated by PMU RTOS during init stage,
So, making changes to use common BOARDOBJGRP SET/GET_STATUS
construct define which fetchs offset/size from SSMD,
& deleting other BOARDOBJGRP construct defines.

JIRA NVGPU-1874

Change-Id: I4e3d9ad31da33a836c5e9219321c68d867c2a172
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000860
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-07 04:15:31 -08:00
Abdul Salam
59b93d1572 gpu: nvgpu: Add exit condition in clk_arb wq.
Currently clk_arb wq waits only for tasks.
Sometimes this doesnt invoke wq when thread_stop is called.
Add a check for thread_stop when waiting in wq.
Remove atomic_inc when no job is submitted.
Use current_time_ns() instead of ptimer to get time.

Bug 200488054

Change-Id: I770d566dd29371bd189d30dd5e60a6b23a9c98ff
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2012244
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-06 03:45:59 -08:00
Adeel Raza
d828e013db gpu: nvgpu: common: MISRA rule 15.6 fixes
MISRA rule 15.6 requires that all if/else/loop blocks should be enclosed
by brackets. This patch adds brackets to single line if/else/loop blocks
in the common directory.

JIRA NVGPU-775

Change-Id: I0dfb38dbf256d49bc0391d889d9fbe5e21da5641
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011655
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Scott Long <scottl@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-05 19:23:47 -08:00
Philip Elcan
75e4e7c9bc gpu: nvgpu: clk: address MISRA 10.3 violations
This fixes a number of miscellaneous MISRA 10.3 violations in
common/pmu/clk/ for assignment of objects of different size or essential
type.

JIRA NVGPU-1008

Change-Id: If93aa9fc4f0f49ea678e39111f323ef4d53f5ec5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2008771
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-02-01 13:45:22 -08:00
Philip Elcan
182aadfd71 gpu: nvgpu: clk: fix MISRA 10.3 issues in clk_arb
MISRA Rule 10.3 prohibits direct assignment of an object of different
essential type or narrower type. This change addresses a number of
miscellaneous violations in clk_arb.

JIRA NVGPU-1008

Change-Id: Iac21ee0c658d55b0c9f7b2d8ea0e134d6fc3c6c5
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001231
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-31 11:05:00 -08:00
Philip Elcan
a2ce1dfd37 gpu: nvgpu: clk: casts for atomic ops in clk_arb
Add the appropriate casts for the atomic ops in clk_arb.c to eliminate a
number of MISRA 10.3 violations.

JIRA NVGPU-1008

Change-Id: Ie098969584734f366901f8b2aaf1e2788fc18753
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001230
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-31 11:04:56 -08:00
Philip Elcan
65c20fe411 gpu: nvgpu: clk: pass u32 for event number
Change the type of the event_number parameter of
nvgpu_clk_notification_queue_alloc() from size_t to u32 since it's
used everywhere as a u32.

JIRA NVGPU-1008

Change-Id: I4305a3816a55a9f5c91439e141d0811bd1b422e8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001229
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-31 11:04:52 -08:00
Philip Elcan
b502e5405a gpu: nvgpu: clk: return u32 for pstate
Change the return type for the HAL API get_current_pstate() from int to
u32 since that's the real type of the pstate and how the callers are
using it.

JIRA NVGPU-1008

Change-Id: Idc6d458212045ceaab724500976cb41d5b1ffc39
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2001228
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-31 11:04:49 -08:00
Abdul Salam
e2a29dbb96 gpu: nvgpu: Align the nvrm freq to match latest VF point
In the below scenario
1. nvrm app requests & gets all VF points from nvgpu.
2. nvrm stores all the VF points and starts setting each point.
3. During step 2, VF gets updated in nvgpu due to some events.
4. There is a mismatch b/w points in nvrm and VF table in nvgpu.
5. If nvrm freq is less than nvgpu freq , PMU cant program.
Makesure highest between nvrm and VF table goes to PMU

Bug 200454682

Change-Id: I9c58f129ff1c0dfb3f4759242469b3622fe11bb2
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2000238
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-01-30 10:06:22 -08:00
Vaibhav Kachore
3c55163713 Revert "Revert "gpu: nvgpu: Reading Vmin and Volt_rail get status""
This reverts commit dcd4673e38.

Bug 2487534

Change-Id: I855e610b8fa46c12ca52c16edc247e5bbe9908b6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003914
Reviewed-by: Pekka Pessi <ppessi@nvidia.com>
Tested-by: Pekka Pessi <ppessi@nvidia.com>
2019-01-29 07:55:43 -08:00
Vaibhav Kachore
f13b5d90e3 Revert "Revert "gpu: nvgpu: Add quantization to slave VF Points""
This reverts commit 8f3bf00b5a.

Bug 2487534

Change-Id: I6d2ce7229adf010080b4a04386c449f2433fedae
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003915
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
2019-01-29 07:53:59 -08:00
Vaibhav Kachore
dcd4673e38 Revert "gpu: nvgpu: Reading Vmin and Volt_rail get status"
This reverts commit f048bb5a71.

Bug 2487534

Change-Id: Ie96351b09e658d8e4c0307c8f73a524e9c532ee7
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2003148
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Tested-by: Konsta Holtta <kholtta@nvidia.com>
2019-01-25 00:49:50 -08:00