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520b461aa7b1befdeee9d4226904f2a1ed370e82
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1721 Commits

Author SHA1 Message Date
Seshendra Gadagottu
520b461aa7 gpu: nvgpu: gp10b: enable dma for firmware loading 
Bug 1692799

Change-Id: Idf825c954c646f649d85b8fa7f76b5b45150bfe5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812442
(cherry picked from commit f72c0738238c3f9a034c6a8b064226f0d7d5dd63)
Reviewed-on: http://git-master/r/813978
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
8066fc9b7b gpu:nvgpu: gp10b: modify gpmu hw init 
Modify gpmu hwinit to take gp10b specific register offsets in
non-secure GPMU boot path.

Bug 1685722

Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/812271
(cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e)
Reviewed-on: http://git-master/r/813979
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
8d864432f5 gpu: nvgpu: set wdt timeout for gp10b 
set platform specific channel watchdog timeout to 5s
for gp10b

Bug 200133289

Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/811509
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Matt Craighead
6f4d1bb2e7 gpu: nvgpu: gp10b: skip powergate if no BPMP 
The powergating APIs only work if the BPMP is running.  Skip
these calls if it's not available, instead of relying on
is_linsim, which doesn't work under all environments.

Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/812415
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
1ba28cf44d gpu: nvgpu: gp10b: Force always SMMU bypass 
Bug 1688709

Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/807030
(cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1)
Reviewed-on: http://git-master/r/808243
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Seshendra Gadagottu
9fb5c25782 gpu: nvgpu: gp10b: update slcg xbar prod settings 
Bug 1689806

Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/806115
(cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd)
Reviewed-on: http://git-master/r/805482
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Vijayakumar
c6766cc798 gpu :nvgpu: gp10b: add ptimer scaling factor as 1x 
bug 1603226

t18x fixes ptimer bug and ticks at 1ns.

Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/799989
(cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1)
Reviewed-on: http://git-master/r/707810
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Jussi Rasanen
040d71d07b gpu: nvgpu: fix ctag computation overflow with 8GB 
Bug 1689976

Change-Id: Ibf1c296fac4f2a2c6fcf062cbd80b3526a4fd4ed
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/806588
(cherry picked from commit 24b57989dc9636b41004bac32ee56dce90318350)
Reviewed-on: http://git-master/r/808242
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
f2b4fcdce7 gpu: nvgpu: implement set_gpc_tpc_mask for gp10b 
Bug 200137963

Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797151
(cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f)
Reviewed-on: http://git-master/r/808241
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Deepak Nibade
d3c12a335d gpu: nvgpu: implement reset_assert/deassert for gp10b 
Implement platform specific reset_assert() and reset_deassert()
calls for gp10b

These APIs will in turn will use reset_control APIs to do
their work

Also, set force_reset_in_do_idle = true for gp10b, since
railgating is not supported yet

Bug 200137963

Change-Id: I2c0fe1273d3ecfd0c46704a44374712052ff51d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/797150
(cherry picked from commit 6ac04ca84cee8a4d3b089678c81534799880712d)
Reviewed-on: http://git-master/r/808240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
d1331bd07d gpu: nvgpu: gp10b: Implement SetCoalesceBufferSize 
Implement method for setting the coalesce buffer size at runtime.

Bug 1681992

Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/802366
(cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611)
Reviewed-on: http://git-master/r/808239
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:08 +05:30
Deepak Nibade
c9da53da4e gpu: nvgpu: fix sparse warning 
fix below sparse warning
drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol
'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static?

Bug 200088648

Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/810394
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:08 +05:30
Leonid Moiseichuk
177a9716e2 gpu: nvgpu: enabling cyclestats for gp10b 
Enabling cyclestats and cyclestats snapshot support for gp10b (t186) devices.

Bug 1674079

Change-Id: I2e14801de3c61d180630bb9dcd2c607749814893
Signed-off-by: Leonid Moiseichuk <lmoiseichuk@nvidia.com>
Reviewed-on: http://git-master/r/792953
Reviewed-on: http://git-master/r/806190
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
0b0ce7de09 gpu: nvgpu: gp10b: Fix steady state beta CB size 
We program the default steady state beta CB size. The default is
for deep binning, but we've disabled deep binning. As result steady
state CB size was left too high.

Bug 1683535

Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/795306
Reviewed-on: http://git-master/r/806189
 2016-12-27 15:22:08 +05:30
Terje Bergstrom
0e6a87cf22 gpu: nvgpu: gp10b: Fix CB size for GfxP 
Program correct CB size for GfxP channels. We were accidentally
using the context image size.

Change-Id: I273215256e41e89b7d76f3294a73641804beeb79
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/792713
Reviewed-on: http://git-master/r/806188
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
1ef64423f9 gpu: nvgpu: ELPG init & statistics update 
- Required init param to start elpg
- change in statistics dump

Bug  1684939

Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/802455
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/806194
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
e51dfa9d61 gpu: nvgpu: gp10b: Use clock API to enable clocks 
Use CCF to enable GPU clocks. Keep an extra reference to prevent
runtime PM callbacks from disabling clocks while GPU is powered up.

Bug 1673672

Change-Id: I8c34be5ec338fedea62aa3e05bd6bed0513bf1b6
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/788814
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-on: http://git-master/r/785265
 2016-12-27 15:22:07 +05:30
Kirill Artamonov
3b08d73568 gpu: nvgpu: gp10b: add debug features for gfxp and cilp 
Add debugfs switch to force cilp and gfx preemption
Add debugfs switch to dump context switch stats on channel
destruction.

bug 1525327
bug 1581799

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66
Reviewed-on: http://git-master/r/794976
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677231
 2016-12-27 15:22:07 +05:30
Kirill Artamonov
6434195dc7 gpu: nvgpu: gp10b: update headers 
Add counters for GFXP, WFI, CTA and CILP context switches

bug 1525327
bug 1581799

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: Ifd6ee08af8a83ed827a8996725139416d81ca10e
Reviewed-on: http://git-master/r/794977
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/778761
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
3e3d83aff1 gpu: nvgpu: enable gp10b rail calls to bpmp 
Bug 200086985

Change-Id: I9eaa135b96629636a6b949ae1e3874dd3abd5138
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/794723
Reviewed-on: http://git-master/r/743217
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Aingara Paramakuru
01ba044bdb gpu: nvgpu: vgpu: add gp10b support 
Add support for gp10b in a virtualized environment.

Bug 1677153
VFND-693

Change-Id: I919ffa44c6773940a7a3411ee8bbc403a992b7cb
Signed-off-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-on: http://git-master/r/792556
Reviewed-on: http://git-master/r/806193
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
8e1c566896 gpu: nvgpu: gp10b: Always disable security in sim 
Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/801850
Reviewed-on: http://git-master/r/806192
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
71afbe484f gpu: nvgpu: fuse read to boot in SECURE mode 
-Read fuse to boot in secure/production
 mode else non sercure mode.

Bug N/A

Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/791323
Reviewed-on: http://git-master/r/806191
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Robert Morell
e7ab0321d3 gpu: nvgpu: gp10b: Correct C097_SET_GO_IDLE_TIMEOUT offset 
Bug 1678603

Change-Id: I1c2c3c9395e068fabf554779ded6f0f536622c90
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/792831
Reviewed-on: http://git-master/r/806187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
cc182623ab gpu: nvgpu: gp10b: Disable deep binning 
Disable deep binning by default.

Change-Id: I75da95984ac314015c6927e099a3eaa37fcc26fc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790403
Reviewed-on: http://git-master/r/806186
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
c54ebdd78a gpu: nvgpu: gp10b: Implement NVC0_SET_GO_IDLE_TIMEOUT 
Bug 1678603

Change-Id: Ib8fb09dace864567b1ce574c216a584831723684
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/790402
Reviewed-on: http://git-master/r/806185
 2016-12-27 15:22:07 +05:30
Sami Kiminki
48cbfac597 gpu: nvgpu: Add CDE scatter buffer code for GP10B 
Add GP10B-specific code for populating the scatter buffer. Essentially,
this enables the use of SMMU bypass mode with 4-kB page compression.

Bug 1604102

Change-Id: Ic586e2f93827b9aa1c7b73b53b8f65d518588c26
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/789434
Reviewed-on: http://git-master/r/806184
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
5df1bc28b3 gpu: nvgpu: gp10b: Choose netlist A 
Force usage of netlist slot A.

Change-Id: Ib507b0e0c7ff6d0dbb43f91b6c7264424975d681
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/789060
Reviewed-on: http://git-master/r/806183
 2016-12-27 15:22:07 +05:30
Deepak Nibade
17bc6e6457 gpu: nvgpu: fix sparse warning 
Fix below sparse warning by declaring gp10b_write_dmatrfbase()
as static

kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol
'gp10b_write_dmatrfbase' was not declared. Should it be static?

Bug 200088648

Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/801213
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
cc1b124d5a gpu: nvgpu: HAL to write DMATRFBASE 
- Must write DMATRFBASE1 to 0 whenever
  DMATRFBASE is written.

Bug 200137618

Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798780
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Mahantesh Kumbar
83955e553c gpu: nvgpu: priv load for gpccs load. 
- clear mask to load gpcss with priv load.

Bug n/a

Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798406
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Sami Kiminki
4711d41bdf gpu: nvgpu: Separate kernel and user GPU VA regions (gp10b) 
Specify that everything in bar2 VM is kernel reserved.

Bug 200077571

Change-Id: I8f6c6ac6352ffd64eedc09187593b6c8d05757ef
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/746802
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Supriya
892ed4317b gpu: nvgpu: gp10b: Fix NS boot transcfg 
Bug 1667322

Accomodate for transcfg address change

Change-Id: I83c5d4921040258a480df44a69792c721ff88f05
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/779764
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Sami Kiminki
95a2719059 gpu: nvgpu: Add CDE program number selection for GP10B 
Add CDE program number selection for GP10B.

Bug 1604102

Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/785459
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Vijayakumar
6b2bfcbfe7 gpu: nvgpu: update t186 slcg prod settings 
bug 1675413

work around for timestamp slcg bug

Change-Id: I0950403b89e9ea161bd7eb7052f47de3f9733240
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/785854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:07 +05:30
Terje Bergstrom
8ae3f0ac28 gpu: nvgpu: gp10b: Use phys addresses in PDEs 
Use physical addresses in PDEs. All page table levels fit in 4k, so no
need for SMMU mapping.

Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/783748
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
 2016-12-27 15:22:07 +05:30
Matt Craighead
b0667dcd8a Revert "gpu: nvgpu: gp10b: Phys addresses for page tables" 
This reverts commit f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5.

Change-Id: I0acfa18e9cf9bedd4051ec00faa497b3cdb9454b
Signed-off-by: Matt Craighead <mcraighead@nvidia.com>
Reviewed-on: http://git-master/r/768599
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
 2016-12-27 15:22:07 +05:30
Vijayakumar
c965e66558 gpu: nvgpu: gp10b: make local function 'static' 
Fixed the following sparse warning by making the local function as static:
- symbol 'gp10b_pmu_load_multiple_falcons' was not declared.
    Should it be static?
- symbol 'gp10b_load_falcon_ucode' was not declared.
    Should it be static?

bug 200067946

Change-Id: I67d865aef6f57bf614db351929cd4bb1b6077c00
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/764646
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Amit Sharma (SW-TEGRA) <amisharma@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
6a071e5ad5 gpu: nvgpu: gp10b: Implement priv pages 
Implement support for privileged pages. Use them for kernel allocated buffers.

Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/761920
 2016-12-27 15:22:06 +05:30
Vijayakumar
4c074ba302 gpu: nvgpu: gp10b: dma support for secure gpccs 
bug 200080684

Change-Id: I013a0ca7762f6cca0498bd282303597bf683cb7d
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/746737
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
8d354418ec gpu: nvgpu: gp10b: Phys addresses for page tables 
Use always physical addresses for page tables. In gp10b new format
each level fits in one page, so we do not need SMMU translation.

Change-Id: Ie46b2bce0f7a4e8d2904d74b1df616e389874141
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/758181
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
4b806879d5 gpu: nvgpu: gp10b: Add regops whitelists 
Add regops whitelists for gp10b. The whitelist is generated, and is the
same for context switched and global registers.

Bug 1633363

Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760935
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
a22aa6d4d3 gpu: nvgpu: gp10b: Do not set up gm20b clocks 
gm20b clock registers do not exist in gp10b. Skip setting the clock
HAL to gm20b variants.

Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
d42ca3a0fc gpu: nvgpu: gp10b: Lazy sync point update 
Update sync point protection field only when we have a valid sync
point id, and the new id is different from old id.

Bug 1653328

Change-Id: Ie07e26f8abd7c8239ad562603b62fda00164cbc7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/757102
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
3b5a1295fa gpu: nvgpu: gp10b: Disable RE suppression 
Bug 1642669

Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/755150
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
910bb6ad0d gpu: nvgpu: gp10b: Set address check mode 
Set address check mode for SM.

Bug 1625763

Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752139
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
477ca4b648 gpu: nvgpu: gp10b: Fix clipping of alpha/beta size 
Alpha and beta sizes need to be clipped to a maximum value. For
alpha CB we were using beta size in clipping, and for both we were
not using number of TPCs to determine the max value.

Change-Id: I0c925464ba4c9f575e6e59dd5ba7759aa1cb6381
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752667
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
32002c59ba gpu: nvgpu: gp10b: Pascal specific global bundle CB 
Some fields have different widths, so duplicate the code to program
global bundle CB.

Change-Id: Ib6af5abf3e90dfa1bcda2fbc6b97ad1031e6ab16
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752635
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
888a27706b gpu: nvgpu: gp10b: Program TEX RM registers 
Program CB base to new gp10b registers.

Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752634
 2016-12-27 15:22:06 +05:30
Terje Bergstrom
4e55cfd995 gpu: nvgpu: gp10b: Use alpha+beta size for beta cb 
When allocating betacb for a GfxP channel, add both alpha and beta
cb sizes together.

Change-Id: I8cef62f6272bfb3b5e9a3835a51590e5eb91dc92
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752633
Reviewed-by: Automatic_Commit_Validation_User
 2016-12-27 15:22:06 +05:30