This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.
Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
Added all registers added to gk20a and gm20b to gp10b. Remove gp10b
trim registers, because they will not be accessed by CPU.
Bug 1567274
Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590312
GVS: Gerrit_Virtual_Submit
We use &ch->error_notifier_mutex to protect
writes and free of error notifier
But we currently do not protect reading of
notifier in gk20a_fifo_set_ctx_mmu_error()
and vgpu_fifo_set_ctx_mmu_error()
Add new API gk20a_set_error_notifier_locked()
which is same as gk20a_set_error_notifier()
but without the locks.
In *_fifo_set_ctx_mmu_error() APIs, acquire
the mutex explicitly, and then use this new
API
gk20a_set_error_notifier() will now just call
gk20a_set_error_notifier_locked() within
a mutex
Bug 1824788
Bug 1844312
Change-Id: I1f3831dc63fe1daa761b2e17e4de3c155f505d6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1273471
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Process long regops lists in 4-kB fragments, overcoming the overly
low limit of 128 reg ops per IOCTL call. Bump the list limit to 1024
and report the limit in GPU characteristics.
Bug 200248726
Change-Id: I3ad49139409f32aea8b1226d6562e88edccc8053
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: http://git-master/r/1253716
(cherry picked from commit 22314619b28f52610cb8769cd4c3f9eb01904eab)
Reviewed-on: http://git-master/r/1266652
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- PG statistics read support for multiple engines
- updated stat_dmem_offset member to array to hold
dmem offset of PG engines
- PMU allocates memory in DMEM for each PG engine requested,
updated gk20a_pmu_get_elpg_residency_gating() to get
engine statistics for requested PG engine
JIRA DNVGPU-71
Change-Id: I2ddade37f85716f757bf33034dbff816184577eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1250506
(cherry picked from commit 68ba7a97d6662b87d0e489365d8afb8e2d237a03)
Reviewed-on: http://git-master/r/1270972
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- Added enable_mscg, mscg_enabled & mscg_stat flags,
mscg_enabled flag can be used to controll
mscg enable/disable at runtime along with mscg_stat flag.
- Added defines & interface to support ms/mclk-change/post-init-param
- Added defines for lpwr tables read from vbios.
- HAL to support post init param which is require
to setup clockgating interface in PMU & interfaces used during
mscg state machine.
- gk20a_pmu_pg_global_enable() can be called when pg support
required to enable/disable, this also checks & wait
if pstate switch is in progress till it complets
- pg_mutex to protect PG-RPPG/MSCG enable/disable
JIRA DNVGPU-71
Change-Id: If312cefc888a4de0a5c96898baeaac1a76e53e46
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247554
(cherry picked from commit e6c94948b8058ba642ea56677ad798fc56b8a28a)
Reviewed-on: http://git-master/r/1270971
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
graphics and compute preemption modes are currently
defined as int
But it is more logical to have them as unsigned int
Also, we treat preemption modes as unsigned almost
everywhere in the code
Fix prints in gk20a_fifo_sched_debugfs_seq_show() to
print U32_MAX with %d which is same as printing -1
Bug 200263471
Change-Id: Iabd0ee3923b76d81620898e90a9b1fc5dd75b530
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1272514
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We use tegra_fuse_control_write() on k4.4 and
tegra_fuse_writel() on previous versions
But gr_gm20b_set_gpc_tpc_mask() currently broken
since we use tegra_fuse_writel() always to
update fuses
Hence define tegra_fuse_control_write() on
previous kernel versions as well and use
it everywhere
Bug 200262155
Change-Id: I116ed77d24018dae21884344373c9eaa1750c2bd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1270168
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
To floorsweep any TPC on gm20b, we first have to
set BIT(28) in CLK_RST_CONTROLLER_MISC_CLK_ENB_0
from nvgpu driver
But now this bit is set by default from clock
driver, hence remove clk_writel() from nvgpu
driver
Bug 200262155
Change-Id: I65bc60cb017109bdb882d83637f2a06d27586f18
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1265752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Make round_rate return max freq when called with a value greater than
the max clock frequency.
Bug 200233943
Change-Id: Id128611f2d09b17a0a0edfefd4b526fd8c215bce
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1272305
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Fix use-after-free overity defect in page allocator. The alloc struct
was getting used after a call for __gk20a_free_pages() which frees
the alloc struct passed in.
Coverity ID: 468942
Bug 200192125
Change-Id: I4f5d32f245efae967050f93c7806290b4bf3591c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1272730
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move the sw initialization of the gpcclk from gpu rail ungate path
to the nvgpu probe path. This allows gpcclk to register itself
successfully with CCF and makes it discoverable for other clients
early on during boot.
Bug 200233943
Bug 200259437
Change-Id: I88d94542092f92e68dc63c40444a70991d1f6129
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1265549
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Restoring original behavior. Use gbus instead of gpu_ref clk as the
argument to tegra_dvfs_get_fmax_at_vmin_safe_t(). Bug was introduced
due to refactoring in 01e61860fa,
changing behavior when nvgpu is compiled with
CONFIG_TEGRA_CLK_FRAMEWORK.
Bug 200233943
Change-Id: Id2deec0107bd0c26a12feb511db22fc69e09a985
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1269848
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
- pmu_init_powergating loops & init multiple
PG engines based on PG engines supported
- generalize pg init param HAL to support
multiple PG-engine init based on PG engine
parameter
- HAL's to return supported PG engines on chip &
its sub features of engine.
- Send Allow/Disallow for PG engines which are
enabled & supported.
- Added defines for pg engines
JIRA DNVGPU-71
Change-Id: I236601e092e519a269fcb17c7d1c523a4b51405f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247409
(cherry-picked from commit 1c138cc475bac7d3c3fbbd5fb18cfcb2e7fdf67a)
Reviewed-on: http://git-master/r/1269319
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Change "check" to "expired" in nvgpu_timeout_check* and append _expired
to nvgpu_timeout_peek to clarify what the boolean-like return value
means and thus avoid bugs.
Bug 200260715
Change-Id: I47e097ee922e856005a79fa9e27eddb1c8d77f8b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1269366
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JIRA DNVGPU-184
Add structures and commands to send noise unware vmin value
to pmu. This is needed to enable closed loop frequency controller
support
Change-Id: If2dfd5e76752a25765ba68821460b7fd2df23aed
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248208
(cherry picked from commit fcd73e0f0bca755ea745f62b52b9e641bc3aa1ae)
Reviewed-on: http://git-master/r/1267434
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
When the user-supplied ioctl argument size is too large, just return
-EINVAL from the ioctl instead of crashing on a BUG_ON (for as, ctrl,
ctxsw, dbg and tsg nodes - channel and sched nodes are already okay).
Bug 1849661
Change-Id: I5b0d1d0c4ee47ce0136c424dda5975353f110c7e
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1266606
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Store pending sema waits so that they can be explicitly handled when
the driver dies. If the sema_wait is freed before the pending wait is
either handled or canceled problems occur.
Internally the sync_fence_wait_async() function uses the kernel timers.
That uses a linked list of possible events. That means every so often
the kernel iterates through this list. If the list node that is in the
sync_fence_waiter struct is freed before it can be removed from the
pending timers list then the kernel timers list can be corrupted. When
the kernel then iterates through this list crashes and other related
problems can happen.
Bug 1816516
Bug 1807277
Change-Id: Iddc4be64583c19bfdd2d88b9098aafc6ae5c6475
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250025
(cherry picked from commit 01889e21bd31dbd7ee85313e98079138ed1d63be)
Reviewed-on: http://git-master/r/1261920
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Ensure that any open channel is definitely closed before freeing it.
Bug 1816516
Bug 1807277
Change-Id: I7f100db5ab6834176ec97d22374646d3336f2856
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250023
(cherry picked from commit 56f1b4b4312c5900f1c27eba55ad970c4b264f24)
Reviewed-on: http://git-master/r/1261919
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Allow forced channel freeing. This is useful when the driver is
being cleaned up and the gk20a_wait_until_counter_is_N() could
potentially hang.
Bug 1816516
Bug 1807277
Change-Id: I711f5f3f6413d0bb30b4857e785ca3b504b494ee
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250022
(cherry picked from commit e132d0e5ae77d758680ac708622a4883bbd69ba3)
Reviewed-on: http://git-master/r/1261918
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Check if the GPU is present after each register read. If the a register
read returns 0xffffffff then it's possible the GPU has fallen off the
bus for some reason or another. However, to confirm that a register read
is due to a dead GPU vs just a 0xffffffff being returned by happenstance
the chip ID register is read which should never return 0xffffffff. If
that read returns 0xffffffff as well then certainly the GPU is dead.
Bug 1805082
Bug 1816516
Bug 1807277
Change-Id: I4de61b56289217d9c0d8167e84615a67c8bde8a9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1239518
(cherry picked from commit bd50828de20aba9b2887ee99c2269602c21a793f)
Reviewed-on: http://git-master/r/1261916
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Allow SW to force a semaphore release. Typically SW waits for a
semaphore to reach the value right before the semaphore release
value before doing a release. For example, assuming a semaphore
is to be released by SW by writing a 10 into the semaphore, the
code waits for the semaphore to get to 9 before writing 10.
The problem with this happens when trying to shutdown the GPU
unexpectedly. When aborting a channel after the GPU has terminated
the GPU is potantially no longer processing anything. If a SW
semaphore release is waiting on the semaphore to reach N-1 before
writing N to the semaphore N-1 may never get written by the GPU.
This obviously causes a hang in the SW shutdown. The solution is
to let SW force a semaphore release in the channel_abort case.
Bug 1816516
Bug 1807277
Change-Id: Ib8b4afd86102eacf372362b1748fb6ca04e6fa66
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250021
(cherry picked from commit 2e9fa40902d2c4d5a1febe0bf2db420ce14bc633)
Reviewed-on: http://git-master/r/1261915
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add a private tsg struct for the TSG file descriptors. This allows
the TSG files to retain access to the gk20a struct without the TSG
data structure still being available.
Bug 1816516
Bug 1807277
Change-Id: If0e41d912bebb7906d72e7eee641f47604a16494
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1250020
(cherry picked from commit 5d8dbbb939e10fecde341891807a0201a63b2b23)
Reviewed-on: http://git-master/r/1261914
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The private_data field in the file pointer passed to release() for
channels originally pointed directly to the referenced channel. The
problem with this is that when the driver is killed and the channel
mmeory is freed that pointer becomes invalid.
The necessity of that channel is to get access to the gk20a struct that
owns the channel. This can instead be accomplished by making a new
private data struct that has a pointer to the gk20a struct directly
instead of requiring the channel to be valid. This lets the release()
function work even if the channels are gone (though in such cases the
release function doesn't do very much).
Change-Id: I5e50bb5b6dd08d38974f8e7b46ba125e9a3f1922
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1246586
(cherry picked from commit 14b7c380c74d2caeb04c47ad3e33332a423a84bb)
Reviewed-on: http://git-master/r/1261913
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Add HAL interface for TSG open, which is intended to
be called from the exisiting gk20a_tsg_open function.
The tsg_open entryoint is only implemented for vgpu,
as the server needs to clear metadata when a tsg is opened.
Bug 200215060
Change-Id: Icc8fd602f31e52d9fa9b2e7786b665b9e7b9294e
Signed-off-by: Sachit Kadle <skadle@nvidia.com>
Reviewed-on: http://git-master/r/1249218
(cherry picked from commit 35c86f7c796c6574d3dc336e20012ea5c16d7cb4)
Reviewed-on: http://git-master/r/1256468
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Update vsms_mapping ioctl to copy from the internal sm_to_cluster array to
new nvgpu_gpu_vsms_mapping_entry array before copying the latter back to user.
Bug 200260086
Change-Id: I0fccc6fb6e0d6b6f737b3a44818d2b47438cd3c8
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1266174
(cherry picked from commit e28882c05491cb8f9573ff71c2d7309e5714e385)
Reviewed-on: http://git-master/r/1269623
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JIRA DNVGPU-129
1)Add function hook for PMU VFE event handler which will do for VF
curve re-evaluation
2)Add function hook to send temperature limit of GPU sensor
3)Call VFE event handler from PMU's event handle function
Change-Id: I2e3577d3d895e97e6ad06e92f0f4827f9855d0b6
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1245393
(cherry picked from commit 1a5c6c32cdec73fb23735430f43577eda675e5af)
Reviewed-on: http://git-master/r/1268060
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use CPU timestamp in nanoseconds
define last event/alarm number
Jira DNVGPU-186
Change-Id: I769c8a7a41ac1fb49234f0d5144a78fa657ec230
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1260799
(cherry picked from commit 379171b43cb20d7a31b3966cad3696525e8cf7d9)
Reviewed-on: http://git-master/r/1267159
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In gk20a_scale_target(), to check for duplicate
freq requests we compare current frequency with
devfreq->previous_freq
But for very first request after boot, we have
devfreq->previous_freq set to MIN freq
And in case we evaluate new frew as MIN freq
then we skip calling postscale() and scaling
of EMC clock
This results in keeping EMC at MAX value
To fix this, add new variable last_freq in
gk20a structure.
Use this variable to store frequency value
and to compare for duplicate requests
Bug 200255163
Bug 200257544
Change-Id: Icfc57234c63f68cce8ccf8221237105272dad853
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1263747
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