Replace all nvgpu_next functions/structs either by 1) collapsing them
into nvgpu legacy functions/structs 2) renaming them as follows:
- nvgpu_next_*() => nvgpu_(ga10b/ga100)_*()
- nvgpu_next_*() => (ga10b/ga100)_*()
- nvgpu_next_*() => nvgpu_*() [only if this doesn't cause collision]
- nvgpu_next_*() = > nvgpu_*_extra()
Create hal.sim unit and move Ampere+ SIM code into it.
Jira NVGPU-4771
Change-Id: I215594a0d0df4bd663bd875a0d0db47bcb9ff6a2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2548056
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.
Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.
Jira NVGPU-4771
Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
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Query the num_perfmon requires golden context to be ready. Accessing
golden context might require gr_instance_id, specific to a GR engine.
On TOT, get_num_hwpm_perfmon() called from perfmon HAL which might
require to call nvgpu_gr_exec_with_err_for_instance().
It internally calls nvgpu_grmgr_config_gr_remap_window() to change
gr_window_remap register points to a current gr_instance_id for MIG.
This approach indirectly mandates to call
nvgpu_gr_exec_with_err_for_instance() which can be
completely avoided. get_num_hwpm_perfmon() is just a query call
which can be moved after the golden context creation.
Using this logic, we can avoid unnecessary invocation of
nvgpu_gr_exec_with_err_for_instance() during perform specific
HAL accesses.
1) Moved get_num_hwpm_perfmon() after golden context creation.
2) Added nvgpu_assert() if (g->num_sys_perfmon == 0U).
JIRA NVGPU-5656
Change-Id: I59a6ab4df93763adbc0765fa5e4d1712b2477521
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542438
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1) Expose logical mask instead of physical mask when MIG is enabled.
For legacy, NvGpu expose physical mask.
2) Added fb related info in struct nvgpu_gpu_instance().
4) Added utility api to get the logical id for a given local id
nvgpu_grmgr_get_gr_gpc_logical_id()
5) Added grmgr api to get max_gpc_count
nvgpu_grmgr_get_max_gpc_count().
5) Added grmgr's fbp api to get num_fbps and its enable masks.
nvgpu_grmgr_get_num_fbps()
nvgpu_grmgr_get_fbp_en_mask()
nvgpu_grmgr_get_fbp_rop_l2_en_mask()
6) Used grmgr's fbp apis in ioctl_ctrl.c
7) Moved fbp_init_support() in nvgpu_early_init()
8) Added nvgpu_assert handling in grmgr.c
9) Added vgpu hal for get_max_gpc_count().
JIRA NVGPU-5656
Change-Id: I90ac2ad99be608001e7d5d754f6242ad26c70cdb
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538508
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If user calls IOCTL to allocate object context for two channels in same
TSG in parallel, nvgpu_gr_setup_alloc_obj_ctx() could end up racing and
trying to allocate object context for both channels at the same time.
This could result in corrupting object context.
Fix this by introducing per-TSG mutex ctx_init_lock to serialize context
initialization for all channels within TSG.
In ideal scenario nvrm_gpu is the only caller of all the IOCTLs, and
nvrm_gpu makes sure to initialize object context for each channel in
serial order. Because of this new lock does not cause any contention.
Jira NVGPU-6431
Change-Id: Ibb1cbb4878748929bb7f23e8666c283c39ecbf5a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538333
(cherry picked from commit 8be447838dc1ecbd5637eb6bd13b8f338eaf33cd)
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CIC (Central Interrupt controller) will be responsible for the
interrupt handling. common.cic unit is the placeholder for all
interrupt related code. Move interrupt related defines and
Public APIs present in common.mc to common.cic.
Note: The common.mc interrupts related struct definitions are
not moved as part of this patch.
Adapt the code to use interrupt handling related defines and public
APIs migrated from common.mc to common.cic
JIRA NVGPU-6899
Change-Id: I747e2b556c0dd66d58d74ee5bb36768b9370d276
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2535618
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GFxP preemption for graphics contexts is not supported in safety.
But the support was enabled along with CONFIG_NVGPU_GRAPHICS since GFxP
preemption was protected under same config.
Add a separate config CONFIG_NVGPU_GFXP to protect all GFxP specific
code, enum values, and HALs.
Disable the config in safety profile.
Jira NVGPU-6893
Change-Id: Iebb5f754a1025dfa6e05a94704bdb8a7123b599a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2534986
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Some of the RTV circular buffer programming is under GRAPHICS config and
some is under DGPU config. For nvgpu-next, RTV circular buffer is
required even for iGPU so keeping the code under DGPU config does not
make sense.
Move all the code from DGPU config to GRAPHICS config.
Bug 3159973
Change-Id: I8438cc0e25354d27701df2fe44762306a731d8cd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
As there is no ACR running after boot, we need LSPMU to bootstrap LS
falcons to support recovery.
In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
not supported.
This CL will enable Low secure falcon manager(lsfm) to support
Lazy bootstrap feature. This will allow nvgpu to send cmds
to lspmu to bootstrap LS falcons.
Bug 200709761
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I65d17cf5e07a45c040a9bb75f75cf18eb509cd4f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506162
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All graphics code is under CONFIG_NVGPU_GRAPHICS and all the HALs are
in non-fusa files. In order to support graphics in safety,
CONFIG_NVGPU_GRAPHICS needs to be enabled. But since most of the HALs
are in non-fusa files, this causes huge compilation problem.
Fix this by moving all graphics specific HALs used on gv11b to fusa
files. Graphics specific HALs not used on gv11b remain in non-fusa files
and need not be protected with GRAPHICS config.
Protect call to nvgpu_pmu_save_zbc() also with config
CONFIG_NVGPU_POWER_PG, since it is implemented under that config.
Delete hal/ltc/ltc_gv11b.c since sole function in this file is moved to
fusa file.
Enable nvgpu_writel_loop() in safety build since it is needed for now.
This will be revisited later once requirements are clearer.
Move below CTXSW methods under CONFIG_NVGPU_NON_FUSA for now. Safety
CTXSW ucode does not support these methods. These too will be revisited
later once requirements are clearer.
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE
Jira NVGPU-6460
Change-Id: Ia095a04a9ba67126068aa7193f491ea27477f882
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2513675
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Add below updates to common.gr doxygen:
- Add doxygen comments for APIs that are mentioned in RM SWAD and in
RM-common.gr traceability document.
- Comment about valid ranges for input parameters of bunch of functions.
- Add nvgpu_assert() to ensure correct value is passed as input
parameter to number of functions.
- Add references to relevant functions with @see.
- Update Targets field for unit tests to cover newly doxygenated
functions.
- Update unit test test_gr_init_hal_pd_skip_table_gpc to take care of
new asserts added into some APIs.
Jira NVGPU-6180
Change-Id: Ie889bed96b6428b1fd86dcf30b322944464e9d12
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469397
(cherry picked from commit 5d7d7e9ce1c4efe836ab842d7962a3aee4e8972f)
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Starting with nvgpu-next, the ctxsw ucode computes the checksum for each
ctxsw'ed register list, this checksum is saved at the end of the same list;
This entry will be given a special placeholder address 0x00ffffff, which can
be used to distinguish it from other entries in the register list.
There is only one checksum per list, even if it has multiple subunits. Hence,
update "add_ctxsw_buffer_map_entries_subunits" to avoid adding checksum
entires for each subunit within a list.
Bug 2916121
Change-Id: Ia7abedc7467ae8158ce3e791a67765fb52889915
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457579
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Update gk20a_ctrl_dev_ioctl() to fetch gpu_instance_id with
nvgpu_get_gpu_instance_id_from_cdev() and gr_instance_id with
nvgpu_grmgr_get_gr_instance_id().
Get instance specific GR engine configuration pointer with
nvgpu_gr_get_gpu_instance_config_ptr()
Update gk20a_ctrl_ioctl_gpu_characteristics() to return instance
specific characteristics with below changes :
- 0th GPU instance is a physical instance. Set a limited and relevant
characteristics flags for 0th instance.
For rest of the instances and non-MIG mode, continue fetching flags
with nvgpu_ctrl_ioctl_gpu_characteristics_flags.
- nvgpu_set_preemption_mode_flags() should be set only for non-MIG mode
and non-zero instance in MIG mode.
- In MIG mode, 0th instance does not support any classes. Rest of the
instances support only compute, copy and gpfifo classes.
Non-MIG mode supports all the classes including graphics ones.
- Fetch gpu_instance_id/gr_sys_pipe_id/gr_instance_id from gpu_instance
pointer.
- Fetch max_veid_count_per_tsg from gpu_instance pointer.
Also update nvgpu_gr_get_zcull_ptr() and nvgpu_gr_get_zbc_ptr() to
return instance specific pointers. zcull/zbc are not supported in MIG
mode, this is just for consistency of the code.
Jira NVGPU-5648
Change-Id: I764526061542c48ed87659844e16dd0e0253c588
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2436752
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Fuse registers should be queried with physical gpc-id and not the
logical ones. For tu104 and before chips physical gpc-ids are same as
logical for non-floorswept config but for newer chips it may differ.
Also, logical to physical mapping is not present for a floorswept gpc so
query gpc_tpc mask only upto actual gpcs that are present.
Jira NVGPU-6080
Change-Id: I84c4a3c1f256fdd1927f4365af26e9892fe91beb
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417721
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The simulator ring buffer DMA interface supports buffers of the following sizes:
4, 8, 12 and 16K. At present, it is configured to 4K and it happens to match
with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once
4K is reached. However, this is not always true; for instance, take 64K pages.
Hence, replace PAGE_SIZE with SIM_BFR_SIZE.
Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace
latter with former.
Bug 200658101
Jira NVGPU-6018
Change-Id: I83cc62b87291734015c51f3e5a98173549e065de
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728
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Update nvgpu_gr_zbc as:
struct nvgpu_gr_zbc {
struct nvgpu_mutex zbc_lock; /* Lock to access zbc table */
struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
u32 min_color_index; /* Minimum valid color table index */
u32 min_depth_index; /* Minimum valid depth table index */
u32 min_stencil_index; /* Minimum valid stencil table index */
u32 max_color_index; /* Maximum valid color table index */
u32 max_depth_index; /* Maximum valid depth table index */
u32 max_stencil_index; /* Maximum valid stencil table index */
u32 max_used_color_index; /* Max used color table index */
u32 max_used_depth_index; /* Max used depth table index */
u32 max_used_stencil_index; /* Max used stencil table index */
};
Add global struct nvgpu_gr_zbc_table_indices
struct nvgpu_gr_zbc_table_indices {
u32 min_color_index;
u32 min_depth_index;
u32 min_stencil_index;
u32 max_color_index;
u32 max_depth_index;
u32 max_stencil_index;
};
Currently, hw zbc table registers are written during both
gr_init_setup_sw() and gr_init_setup_hw().
- Modify nvgpu_gr_zbc_load_default_table() to
nvgpu_gr_zbc_load_default_sw_table() to only update sw copy of zbc table
during gr_init_setup_sw().
- Modify nvgpu_gr_zbc_load_table() to write zbc values stored in sw zbc
table to hw registers.
Re-structure zbc function as per zbc type i.e. color, depth and stencil.
Add gr.zbc.init_table_indices() hal to initialize zbc indices. Valid ZBC
table indices start from 1. HW indices start from 0 for color, depth and
stencil tables. Note that the corresponding format registers follow ZBC
index range starting at 1.
- void (*init_table_indices)(struct gk20a *g,
struct nvgpu_gr_zbc_table_indices *zbc_indices);
- Add corresponding functions for legacy chips
- Add zbc color, depth and stencil table size hw defines
- Remove ltc.zbc_table_size() hal
- Update ltc.set_zbc_s_entry(), ltc.set_zbc_color_entry and
ltc.set_zbc_depth_entry() accordingly.
Bug 3122410
Bug 3122649
Change-Id: Ib799991ad35c6613534c0a6eb07f3bf24e600dc5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417620
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APIs to set preemption modes right now have config based code to set
default preemption modes or to check if given preemption mode is valid
or not. This makes code unreadable and complex.
Rework nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode() so that it checks
for initial preemption modes in the beginning. If no preemption mode is
passed while allocating context, get default preemption modes with
gops.gr.init.get_default_preemption_modes() and use them.
Rework nvgpu_gr_ctx_check_valid_preemption_mode() so that it is more
readable. Use gops.gr.init.get_supported_preemption_modes() to validate
incoming preemption modes against supported preemption modes.
Log preemption modes getting set in
nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode().
Disable failing unit test. It will need rework according to new code.
Jira NVGPU-5648
Change-Id: Ie1a3e1aeae7826a123e104d9d016f181bea3b271
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2419034
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common.gr defined a temporary macro NVGPU_GR_NUM_INSTANCES to enable or
disable multiple GR instances from common.gr unit.
Multiple GR instance boot is now verified, so we can remove this
temporary solution.
Note that nvgpu_grmgr_get_num_gr_instances() will return more than 1
instance only if NVGPU_SUPPORT_MIG is enabled.
Update unit tests to set number of syspipes to 1 to allow enumeration
of GR instance by grmgr.
Jira NVGPU-5648
Change-Id: I795901ae516843ae7b6c1794dae0f023a213ab1d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418377
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This CL covers the following code changes,
1) Added api to get the gr_config per gr_instance_id basis.
2) Added api to covert from gpu_instance_id to gr_instance_id.
3) Modified nvgpu_gr_exec_with_ret_for_instance() utility to handle
generic data return type.
JIRA NVGPU-5662
JIRA NVGPU-5663
Change-Id: I4ab732e15cdbda25672975f99e23b5e5d27decb0
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413195
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Add macros to get current GR instance id and the pointer
nvgpu_gr_get_cur_instance_ptr()
nvgpu_gr_get_cur_instance_id()
This approach makes sure that the caller is getting GR instance pointer
under mutex g->mig.gr_syspipe_lock in MIG mode. Trying to access
current GR instance outside of this lock in MIG mode dumps a warning.
Return 0th instance in case MIG mode is disabled.
Use these macros in nvgpu instead of direct reference to
g->mig.cur_gr_instance.
Store instance id in struct nvgpu_gr. This is to retrieve GR instance
id in functions where struct nvgpu_gr pointer is already available.
Jira NVGPU-5648
Change-Id: Ibfef6a22371bfdccfdc2a7d636b0a3e8d0eff6d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413140
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gr_gv100_init_hwpm_pmm_register() and gr_gv100_set_pmm_register() right
now assume common chiplet stride for all sys/fbp/gpc and use common API
g->ops.perf.get_pmm_per_chiplet_offset() to get the stride.
Chiplet strides are same for all partitions only by chance, and future
chip might change that.
Hence add and use below 3 separate HALs to get appropriate strides.
g->ops.perf.get_pmmsys_per_chiplet_offset()
g->ops.perf.get_pmmgpc_per_chiplet_offset()
g->ops.perf.get_pmmfbp_per_chiplet_offset()
Also store sys/fbp/gpc perfmon count in struct gk20a after first query
instead of querying them again and again. Querying the counts from HW
is time consuming.
Bug 2510974
Jira NVGPU-5360
Change-Id: I186009221009780d561617c0cd6f535854db585f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413108
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
