This CL covers the following modification,
1) Added multiple engine_info support
2) Added multiple runlist_info support
3) Initial changes for ASYNC CE support
4) Added ASYNC CE interrupt support for
Pascal GPU series
5) Removed hard coded engine_id logic and
made generic way
6) Code cleanup for readability
JIRA DNVGPU-26
Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1156022
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move per-chip constants to be returned by a chip specific function.
Implement get_litter_value() for each chip.
Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1121384
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Add regops whitelists for gp10b. The whitelist is generated, and is the
same for context switched and global registers.
Bug 1633363
Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760935
gm20b clock registers do not exist in gp10b. Skip setting the clock
HAL to gm20b variants.
Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/760854
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Fix sparse warnings of below type by making necessary
symbols static:
warning: symbol '<symbol>' was not declared. Should it be static?
Bug 200088648
Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
ce interrupts use different register mapping
and format from gk20a and gm20b.
Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/681646
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GPFIFO class was set to Maxwell class number. Also implement the
PBDMA signature HAL.
Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/672921
Remove hard coded NETB for gp10b. This enables cycling through
available firmware files.
Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/676557
Reviewed-by: Peng Du <pdu@nvidia.com>
GVS: Gerrit_Virtual_Submit
GP10B physical address width is 37 bits. Use old width for now,
and add gp10b specific definition. We can switch to new definition
once we've verified them.
Bug 1567274
Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601703
This change adds gp10b to the nvgpu build as
well as enabling CMA for buffer allocation.
Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76
Signed-off-by: Ken Adams <kadams@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/553324
GVS: Gerrit_Virtual_Submit
